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[qemu.git] / hw / intel-hda.c
CommitLineData
d61a4ce8
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Gerd Hoffmann <[email protected]>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "hw.h"
21#include "pci.h"
17786d52 22#include "msi.h"
d61a4ce8
GH		 23#include "qemu-timer.h"
24#include "audiodev.h"
25#include "intel-hda.h"
26#include "intel-hda-defs.h"
fa0ce55c 27#include "dma.h"
d61a4ce8
GH		 28
29/* --------------------------------------------------------------------- */
30/* hda bus */
31
32static struct BusInfo hda_codec_bus_info = {
33 .name = "HDA",
34 .size = sizeof(HDACodecBus),
35 .props = (Property[]) {
36 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
37 DEFINE_PROP_END_OF_LIST()
38 }
39};
40
41void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus,
42 hda_codec_response_func response,
43 hda_codec_xfer_func xfer)
44{
45 qbus_create_inplace(&bus->qbus, &hda_codec_bus_info, dev, NULL);
46 bus->response = response;
47 bus->xfer = xfer;
48}
49
50static int hda_codec_dev_init(DeviceState *qdev, DeviceInfo *base)
51{
52 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus);
53 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
54 HDACodecDeviceInfo *info = DO_UPCAST(HDACodecDeviceInfo, qdev, base);
55
56 dev->info = info;
57 if (dev->cad == -1) {
58 dev->cad = bus->next_cad;
59 }
df0db221 60 if (dev->cad >= 15) {
d61a4ce8 61 return -1;
df0db221 62 }
d61a4ce8
GH		 63 bus->next_cad = dev->cad + 1;
64 return info->init(dev);
65}
66
dc4b9240
GH		 67static int hda_codec_dev_exit(DeviceState *qdev)
68{
69 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
70
71 if (dev->info->exit) {
72 dev->info->exit(dev);
73 }
74 return 0;
75}
76
d61a4ce8
GH		 77void hda_codec_register(HDACodecDeviceInfo *info)
78{
79 info->qdev.init = hda_codec_dev_init;
dc4b9240 80 info->qdev.exit = hda_codec_dev_exit;
d61a4ce8
GH		 81 info->qdev.bus_info = &hda_codec_bus_info;
82 qdev_register(&info->qdev);
83}
84
85HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
86{
87 DeviceState *qdev;
88 HDACodecDevice *cdev;
89
d8bb00d6 90 QTAILQ_FOREACH(qdev, &bus->qbus.children, sibling) {
d61a4ce8
GH		 91 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
92 if (cdev->cad == cad) {
93 return cdev;
94 }
95 }
96 return NULL;
97}
98
99void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
100{
101 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
102 bus->response(dev, solicited, response);
103}
104
105bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
106 uint8_t *buf, uint32_t len)
107{
108 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
109 return bus->xfer(dev, stnr, output, buf, len);
110}
111
112/* --------------------------------------------------------------------- */
113/* intel hda emulation */
114
115typedef struct IntelHDAStream IntelHDAStream;
116typedef struct IntelHDAState IntelHDAState;
117typedef struct IntelHDAReg IntelHDAReg;
118
119typedef struct bpl {
120 uint64_t addr;
121 uint32_t len;
122 uint32_t flags;
123} bpl;
124
125struct IntelHDAStream {
126 /* registers */
127 uint32_t ctl;
128 uint32_t lpib;
129 uint32_t cbl;
130 uint32_t lvi;
131 uint32_t fmt;
132 uint32_t bdlp_lbase;
133 uint32_t bdlp_ubase;
134
135 /* state */
136 bpl *bpl;
137 uint32_t bentries;
138 uint32_t bsize, be, bp;
139};
140
141struct IntelHDAState {
142 PCIDevice pci;
143 const char *name;
144 HDACodecBus codecs;
145
146 /* registers */
147 uint32_t g_ctl;
148 uint32_t wake_en;
149 uint32_t state_sts;
150 uint32_t int_ctl;
151 uint32_t int_sts;
152 uint32_t wall_clk;
153
154 uint32_t corb_lbase;
155 uint32_t corb_ubase;
156 uint32_t corb_rp;
157 uint32_t corb_wp;
158 uint32_t corb_ctl;
159 uint32_t corb_sts;
160 uint32_t corb_size;
161
162 uint32_t rirb_lbase;
163 uint32_t rirb_ubase;
164 uint32_t rirb_wp;
165 uint32_t rirb_cnt;
166 uint32_t rirb_ctl;
167 uint32_t rirb_sts;
168 uint32_t rirb_size;
169
170 uint32_t dp_lbase;
171 uint32_t dp_ubase;
172
173 uint32_t icw;
174 uint32_t irr;
175 uint32_t ics;
176
177 /* streams */
178 IntelHDAStream st[8];
179
180 /* state */
234bbdf1 181 MemoryRegion mmio;
d61a4ce8
GH		 182 uint32_t rirb_count;
183 int64_t wall_base_ns;
184
185 /* debug logging */
186 const IntelHDAReg *last_reg;
187 uint32_t last_val;
188 uint32_t last_write;
189 uint32_t last_sec;
190 uint32_t repeat_count;
191
192 /* properties */
193 uint32_t debug;
17786d52 194 uint32_t msi;
d61a4ce8
GH		 195};
196
197struct IntelHDAReg {
198 const char *name; /* register name */
199 uint32_t size; /* size in bytes */
200 uint32_t reset; /* reset value */
201 uint32_t wmask; /* write mask */
202 uint32_t wclear; /* write 1 to clear bits */
203 uint32_t offset; /* location in IntelHDAState */
204 uint32_t shift; /* byte access entries for dwords */
205 uint32_t stream;
206 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
207 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
208};
209
210static void intel_hda_reset(DeviceState *dev);
211
212/* --------------------------------------------------------------------- */
213
214static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
215{
216 target_phys_addr_t addr;
217
218#if TARGET_PHYS_ADDR_BITS == 32
219 addr = lbase;
220#else
221 addr = ubase;
222 addr <<= 32;
223 addr |= lbase;
224#endif
225 return addr;
226}
227
d61a4ce8
GH		 228static void intel_hda_update_int_sts(IntelHDAState *d)
229{
230 uint32_t sts = 0;
231 uint32_t i;
232
233 /* update controller status */
234 if (d->rirb_sts & ICH6_RBSTS_IRQ) {
235 sts |= (1 << 30);
236 }
237 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
238 sts |= (1 << 30);
239 }
af93485c 240 if (d->state_sts & d->wake_en) {
d61a4ce8
GH		 241 sts |= (1 << 30);
242 }
243
244 /* update stream status */
245 for (i = 0; i < 8; i++) {
246 /* buffer completion interrupt */
247 if (d->st[i].ctl & (1 << 26)) {
248 sts |= (1 << i);
249 }
250 }
251
252 /* update global status */
253 if (sts & d->int_ctl) {
254 sts |= (1 << 31);
255 }
256
257 d->int_sts = sts;
258}
259
260static void intel_hda_update_irq(IntelHDAState *d)
261{
17786d52 262 int msi = d->msi && msi_enabled(&d->pci);
d61a4ce8
GH		 263 int level;
264
265 intel_hda_update_int_sts(d);
266 if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) {
267 level = 1;
268 } else {
269 level = 0;
270 }
17786d52
GH		 271 dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__,
272 level, msi ? "msi" : "intx");
273 if (msi) {
274 if (level) {
275 msi_notify(&d->pci, 0);
276 }
277 } else {
278 qemu_set_irq(d->pci.irq[0], level);
279 }
d61a4ce8
GH		 280}
281
282static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
283{
284 uint32_t cad, nid, data;
285 HDACodecDevice *codec;
286
287 cad = (verb >> 28) & 0x0f;
288 if (verb & (1 << 27)) {
289 /* indirect node addressing, not specified in HDA 1.0 */
290 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__);
291 return -1;
292 }
293 nid = (verb >> 20) & 0x7f;
294 data = verb & 0xfffff;
295
296 codec = hda_codec_find(&d->codecs, cad);
297 if (codec == NULL) {
298 dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__);
299 return -1;
300 }
301 codec->info->command(codec, nid, data);
302 return 0;
303}
304
305static void intel_hda_corb_run(IntelHDAState *d)
306{
307 target_phys_addr_t addr;
308 uint32_t rp, verb;
309
310 if (d->ics & ICH6_IRS_BUSY) {
311 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw);
312 intel_hda_send_command(d, d->icw);
313 return;
314 }
315
316 for (;;) {
317 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
318 dprint(d, 2, "%s: !run\n", __FUNCTION__);
319 return;
320 }
321 if ((d->corb_rp & 0xff) == d->corb_wp) {
322 dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__);
323 return;
324 }
325 if (d->rirb_count == d->rirb_cnt) {
326 dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__);
327 return;
328 }
329
330 rp = (d->corb_rp + 1) & 0xff;
331 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
fa0ce55c 332 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp);
d61a4ce8
GH		 333 d->corb_rp = rp;
334
335 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb);
336 intel_hda_send_command(d, verb);
337 }
338}
339
340static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
341{
342 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
343 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
344 target_phys_addr_t addr;
345 uint32_t wp, ex;
346
347 if (d->ics & ICH6_IRS_BUSY) {
348 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
349 __FUNCTION__, response, dev->cad);
350 d->irr = response;
351 d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
352 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
353 return;
354 }
355
356 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
357 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__);
358 return;
359 }
360
361 ex = (solicited ? 0 : (1 << 4)) | dev->cad;
362 wp = (d->rirb_wp + 1) & 0xff;
363 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
fa0ce55c
DG		 364 stl_le_pci_dma(&d->pci, addr + 8*wp, response);
365 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex);
d61a4ce8
GH		 366 d->rirb_wp = wp;
367
368 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
369 __FUNCTION__, wp, response, ex);
370
371 d->rirb_count++;
372 if (d->rirb_count == d->rirb_cnt) {
373 dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count);
374 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
375 d->rirb_sts |= ICH6_RBSTS_IRQ;
376 intel_hda_update_irq(d);
377 }
378 } else if ((d->corb_rp & 0xff) == d->corb_wp) {
379 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__,
380 d->rirb_count, d->rirb_cnt);
381 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
382 d->rirb_sts |= ICH6_RBSTS_IRQ;
383 intel_hda_update_irq(d);
384 }
385 }
386}
387
388static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
389 uint8_t *buf, uint32_t len)
390{
391 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
392 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
d61a4ce8
GH		 393 target_phys_addr_t addr;
394 uint32_t s, copy, left;
36ac4ad3 395 IntelHDAStream *st;
d61a4ce8
GH		 396 bool irq = false;
397
36ac4ad3
MAL		 398 st = output ? d->st + 4 : d->st;
399 for (s = 0; s < 4; s++) {
400 if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
401 st = st + s;
d61a4ce8
GH		 402 break;
403 }
404 }
18ebcc86 405 if (s == 4) {
d61a4ce8
GH		 406 return false;
407 }
408 if (st->bpl == NULL) {
409 return false;
410 }
411 if (st->ctl & (1 << 26)) {
412 /*
413 * Wait with the next DMA xfer until the guest
414 * has acked the buffer completion interrupt
415 */
416 return false;
417 }
418
419 left = len;
420 while (left > 0) {
421 copy = left;
422 if (copy > st->bsize - st->lpib)
423 copy = st->bsize - st->lpib;
424 if (copy > st->bpl[st->be].len - st->bp)
425 copy = st->bpl[st->be].len - st->bp;
426
427 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
428 st->be, st->bp, st->bpl[st->be].len, copy);
429
fa0ce55c 430 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output);
d61a4ce8
GH		 431 st->lpib += copy;
432 st->bp += copy;
433 buf += copy;
434 left -= copy;
435
436 if (st->bpl[st->be].len == st->bp) {
437 /* bpl entry filled */
438 if (st->bpl[st->be].flags & 0x01) {
439 irq = true;
440 }
441 st->bp = 0;
442 st->be++;
443 if (st->be == st->bentries) {
444 /* bpl wrap around */
445 st->be = 0;
446 st->lpib = 0;
447 }
448 }
449 }
450 if (d->dp_lbase & 0x01) {
451 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
fa0ce55c 452 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib);
d61a4ce8
GH		 453 }
454 dprint(d, 3, "dma: --\n");
455
456 if (irq) {
457 st->ctl |= (1 << 26); /* buffer completion interrupt */
458 intel_hda_update_irq(d);
459 }
460 return true;
461}
462
463static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
464{
465 target_phys_addr_t addr;
466 uint8_t buf[16];
467 uint32_t i;
468
469 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
470 st->bentries = st->lvi +1;
7267c094
AL		 471 g_free(st->bpl);
472 st->bpl = g_malloc(sizeof(bpl) * st->bentries);
d61a4ce8 473 for (i = 0; i < st->bentries; i++, addr += 16) {
fa0ce55c 474 pci_dma_read(&d->pci, addr, buf, 16);
d61a4ce8
GH		 475 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
476 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
477 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
478 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
479 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
480 }
481
482 st->bsize = st->cbl;
483 st->lpib = 0;
484 st->be = 0;
485 st->bp = 0;
486}
487
ba43d289 488static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
d61a4ce8
GH		 489{
490 DeviceState *qdev;
491 HDACodecDevice *cdev;
492
d8bb00d6 493 QTAILQ_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
d61a4ce8
GH		 494 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
495 if (cdev->info->stream) {
ba43d289 496 cdev->info->stream(cdev, stream, running, output);
d61a4ce8
GH		 497 }
498 }
499}
500
501/* --------------------------------------------------------------------- */
502
503static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
504{
505 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
506 intel_hda_reset(&d->pci.qdev);
507 }
508}
509
6a0d02f5
GH		 510static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
511{
512 intel_hda_update_irq(d);
513}
514
d61a4ce8
GH		 515static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
516{
517 intel_hda_update_irq(d);
518}
519
520static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
521{
522 intel_hda_update_irq(d);
523}
524
525static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
526{
527 int64_t ns;
528
529 ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns;
530 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
531}
532
533static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
534{
535 intel_hda_corb_run(d);
536}
537
538static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
539{
540 intel_hda_corb_run(d);
541}
542
543static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
544{
545 if (d->rirb_wp & ICH6_RIRBWP_RST) {
546 d->rirb_wp = 0;
547 }
548}
549
550static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
551{
552 intel_hda_update_irq(d);
553
554 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
555 /* cleared ICH6_RBSTS_IRQ */
556 d->rirb_count = 0;
557 intel_hda_corb_run(d);
558 }
559}
560
561static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
562{
563 if (d->ics & ICH6_IRS_BUSY) {
564 intel_hda_corb_run(d);
565 }
566}
567
568static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
569{
ba43d289 570 bool output = reg->stream >= 4;
d61a4ce8
GH		 571 IntelHDAStream *st = d->st + reg->stream;
572
573 if (st->ctl & 0x01) {
574 /* reset */
575 dprint(d, 1, "st #%d: reset\n", reg->stream);
576 st->ctl = 0;
577 }
578 if ((st->ctl & 0x02) != (old & 0x02)) {
579 uint32_t stnr = (st->ctl >> 20) & 0x0f;
580 /* run bit flipped */
581 if (st->ctl & 0x02) {
582 /* start */
583 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
584 reg->stream, stnr, st->cbl);
585 intel_hda_parse_bdl(d, st);
ba43d289 586 intel_hda_notify_codecs(d, stnr, true, output);
d61a4ce8
GH		 587 } else {
588 /* stop */
589 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
ba43d289 590 intel_hda_notify_codecs(d, stnr, false, output);
d61a4ce8
GH		 591 }
592 }
593 intel_hda_update_irq(d);
594}
595
596/* --------------------------------------------------------------------- */
597
598#define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
599
600static const struct IntelHDAReg regtab[] = {
601 /* global */
602 [ ICH6_REG_GCAP ] = {
603 .name = "GCAP",
604 .size = 2,
605 .reset = 0x4401,
606 },
607 [ ICH6_REG_VMIN ] = {
608 .name = "VMIN",
609 .size = 1,
610 },
611 [ ICH6_REG_VMAJ ] = {
612 .name = "VMAJ",
613 .size = 1,
614 .reset = 1,
615 },
616 [ ICH6_REG_OUTPAY ] = {
617 .name = "OUTPAY",
618 .size = 2,
619 .reset = 0x3c,
620 },
621 [ ICH6_REG_INPAY ] = {
622 .name = "INPAY",
623 .size = 2,
624 .reset = 0x1d,
625 },
626 [ ICH6_REG_GCTL ] = {
627 .name = "GCTL",
628 .size = 4,
629 .wmask = 0x0103,
630 .offset = offsetof(IntelHDAState, g_ctl),
631 .whandler = intel_hda_set_g_ctl,
632 },
633 [ ICH6_REG_WAKEEN ] = {
634 .name = "WAKEEN",
635 .size = 2,
df0db221 636 .wmask = 0x7fff,
d61a4ce8 637 .offset = offsetof(IntelHDAState, wake_en),
6a0d02f5 638 .whandler = intel_hda_set_wake_en,
d61a4ce8
GH		 639 },
640 [ ICH6_REG_STATESTS ] = {
641 .name = "STATESTS",
642 .size = 2,
df0db221
GH		 643 .wmask = 0x7fff,
644 .wclear = 0x7fff,
d61a4ce8
GH		 645 .offset = offsetof(IntelHDAState, state_sts),
646 .whandler = intel_hda_set_state_sts,
647 },
648
649 /* interrupts */
650 [ ICH6_REG_INTCTL ] = {
651 .name = "INTCTL",
652 .size = 4,
653 .wmask = 0xc00000ff,
654 .offset = offsetof(IntelHDAState, int_ctl),
655 .whandler = intel_hda_set_int_ctl,
656 },
657 [ ICH6_REG_INTSTS ] = {
658 .name = "INTSTS",
659 .size = 4,
660 .wmask = 0xc00000ff,
661 .wclear = 0xc00000ff,
662 .offset = offsetof(IntelHDAState, int_sts),
663 },
664
665 /* misc */
666 [ ICH6_REG_WALLCLK ] = {
667 .name = "WALLCLK",
668 .size = 4,
669 .offset = offsetof(IntelHDAState, wall_clk),
670 .rhandler = intel_hda_get_wall_clk,
671 },
672 [ ICH6_REG_WALLCLK + 0x2000 ] = {
673 .name = "WALLCLK(alias)",
674 .size = 4,
675 .offset = offsetof(IntelHDAState, wall_clk),
676 .rhandler = intel_hda_get_wall_clk,
677 },
678
679 /* dma engine */
680 [ ICH6_REG_CORBLBASE ] = {
681 .name = "CORBLBASE",
682 .size = 4,
683 .wmask = 0xffffff80,
684 .offset = offsetof(IntelHDAState, corb_lbase),
685 },
686 [ ICH6_REG_CORBUBASE ] = {
687 .name = "CORBUBASE",
688 .size = 4,
689 .wmask = 0xffffffff,
690 .offset = offsetof(IntelHDAState, corb_ubase),
691 },
692 [ ICH6_REG_CORBWP ] = {
693 .name = "CORBWP",
694 .size = 2,
695 .wmask = 0xff,
696 .offset = offsetof(IntelHDAState, corb_wp),
697 .whandler = intel_hda_set_corb_wp,
698 },
699 [ ICH6_REG_CORBRP ] = {
700 .name = "CORBRP",
701 .size = 2,
702 .wmask = 0x80ff,
703 .offset = offsetof(IntelHDAState, corb_rp),
704 },
705 [ ICH6_REG_CORBCTL ] = {
706 .name = "CORBCTL",
707 .size = 1,
708 .wmask = 0x03,
709 .offset = offsetof(IntelHDAState, corb_ctl),
710 .whandler = intel_hda_set_corb_ctl,
711 },
712 [ ICH6_REG_CORBSTS ] = {
713 .name = "CORBSTS",
714 .size = 1,
715 .wmask = 0x01,
716 .wclear = 0x01,
717 .offset = offsetof(IntelHDAState, corb_sts),
718 },
719 [ ICH6_REG_CORBSIZE ] = {
720 .name = "CORBSIZE",
721 .size = 1,
722 .reset = 0x42,
723 .offset = offsetof(IntelHDAState, corb_size),
724 },
725 [ ICH6_REG_RIRBLBASE ] = {
726 .name = "RIRBLBASE",
727 .size = 4,
728 .wmask = 0xffffff80,
729 .offset = offsetof(IntelHDAState, rirb_lbase),
730 },
731 [ ICH6_REG_RIRBUBASE ] = {
732 .name = "RIRBUBASE",
733 .size = 4,
734 .wmask = 0xffffffff,
735 .offset = offsetof(IntelHDAState, rirb_ubase),
736 },
737 [ ICH6_REG_RIRBWP ] = {
738 .name = "RIRBWP",
739 .size = 2,
740 .wmask = 0x8000,
741 .offset = offsetof(IntelHDAState, rirb_wp),
742 .whandler = intel_hda_set_rirb_wp,
743 },
744 [ ICH6_REG_RINTCNT ] = {
745 .name = "RINTCNT",
746 .size = 2,
747 .wmask = 0xff,
748 .offset = offsetof(IntelHDAState, rirb_cnt),
749 },
750 [ ICH6_REG_RIRBCTL ] = {
751 .name = "RIRBCTL",
752 .size = 1,
753 .wmask = 0x07,
754 .offset = offsetof(IntelHDAState, rirb_ctl),
755 },
756 [ ICH6_REG_RIRBSTS ] = {
757 .name = "RIRBSTS",
758 .size = 1,
759 .wmask = 0x05,
760 .wclear = 0x05,
761 .offset = offsetof(IntelHDAState, rirb_sts),
762 .whandler = intel_hda_set_rirb_sts,
763 },
764 [ ICH6_REG_RIRBSIZE ] = {
765 .name = "RIRBSIZE",
766 .size = 1,
767 .reset = 0x42,
768 .offset = offsetof(IntelHDAState, rirb_size),
769 },
770
771 [ ICH6_REG_DPLBASE ] = {
772 .name = "DPLBASE",
773 .size = 4,
774 .wmask = 0xffffff81,
775 .offset = offsetof(IntelHDAState, dp_lbase),
776 },
777 [ ICH6_REG_DPUBASE ] = {
778 .name = "DPUBASE",
779 .size = 4,
780 .wmask = 0xffffffff,
781 .offset = offsetof(IntelHDAState, dp_ubase),
782 },
783
784 [ ICH6_REG_IC ] = {
785 .name = "ICW",
786 .size = 4,
787 .wmask = 0xffffffff,
788 .offset = offsetof(IntelHDAState, icw),
789 },
790 [ ICH6_REG_IR ] = {
791 .name = "IRR",
792 .size = 4,
793 .offset = offsetof(IntelHDAState, irr),
794 },
795 [ ICH6_REG_IRS ] = {
796 .name = "ICS",
797 .size = 2,
798 .wmask = 0x0003,
799 .wclear = 0x0002,
800 .offset = offsetof(IntelHDAState, ics),
801 .whandler = intel_hda_set_ics,
802 },
803
804#define HDA_STREAM(_t, _i) \
805 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
806 .stream = _i, \
807 .name = _t stringify(_i) " CTL", \
808 .size = 4, \
809 .wmask = 0x1cff001f, \
810 .offset = offsetof(IntelHDAState, st[_i].ctl), \
811 .whandler = intel_hda_set_st_ctl, \
812 }, \
813 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
814 .stream = _i, \
815 .name = _t stringify(_i) " CTL(stnr)", \
816 .size = 1, \
817 .shift = 16, \
818 .wmask = 0x00ff0000, \
819 .offset = offsetof(IntelHDAState, st[_i].ctl), \
820 .whandler = intel_hda_set_st_ctl, \
821 }, \
822 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
823 .stream = _i, \
824 .name = _t stringify(_i) " CTL(sts)", \
825 .size = 1, \
826 .shift = 24, \
827 .wmask = 0x1c000000, \
828 .wclear = 0x1c000000, \
829 .offset = offsetof(IntelHDAState, st[_i].ctl), \
830 .whandler = intel_hda_set_st_ctl, \
831 }, \
832 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
833 .stream = _i, \
834 .name = _t stringify(_i) " LPIB", \
835 .size = 4, \
836 .offset = offsetof(IntelHDAState, st[_i].lpib), \
837 }, \
838 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
839 .stream = _i, \
840 .name = _t stringify(_i) " LPIB(alias)", \
841 .size = 4, \
842 .offset = offsetof(IntelHDAState, st[_i].lpib), \
843 }, \
844 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
845 .stream = _i, \
846 .name = _t stringify(_i) " CBL", \
847 .size = 4, \
848 .wmask = 0xffffffff, \
849 .offset = offsetof(IntelHDAState, st[_i].cbl), \
850 }, \
851 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
852 .stream = _i, \
853 .name = _t stringify(_i) " LVI", \
854 .size = 2, \
855 .wmask = 0x00ff, \
856 .offset = offsetof(IntelHDAState, st[_i].lvi), \
857 }, \
858 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
859 .stream = _i, \
860 .name = _t stringify(_i) " FIFOS", \
861 .size = 2, \
862 .reset = HDA_BUFFER_SIZE, \
863 }, \
864 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
865 .stream = _i, \
866 .name = _t stringify(_i) " FMT", \
867 .size = 2, \
868 .wmask = 0x7f7f, \
869 .offset = offsetof(IntelHDAState, st[_i].fmt), \
870 }, \
871 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
872 .stream = _i, \
873 .name = _t stringify(_i) " BDLPL", \
874 .size = 4, \
875 .wmask = 0xffffff80, \
876 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
877 }, \
878 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
879 .stream = _i, \
880 .name = _t stringify(_i) " BDLPU", \
881 .size = 4, \
882 .wmask = 0xffffffff, \
883 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
884 }, \
885
886 HDA_STREAM("IN", 0)
887 HDA_STREAM("IN", 1)
888 HDA_STREAM("IN", 2)
889 HDA_STREAM("IN", 3)
890
891 HDA_STREAM("OUT", 4)
892 HDA_STREAM("OUT", 5)
893 HDA_STREAM("OUT", 6)
894 HDA_STREAM("OUT", 7)
895
896};
897
898static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr)
899{
900 const IntelHDAReg *reg;
901
902 if (addr >= sizeof(regtab)/sizeof(regtab[0])) {
903 goto noreg;
904 }
905 reg = regtab+addr;
906 if (reg->name == NULL) {
907 goto noreg;
908 }
909 return reg;
910
911noreg:
912 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
913 return NULL;
914}
915
916static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
917{
918 uint8_t *addr = (void*)d;
919
920 addr += reg->offset;
921 return (uint32_t*)addr;
922}
923
924static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
925 uint32_t wmask)
926{
927 uint32_t *addr;
928 uint32_t old;
929
930 if (!reg) {
931 return;
932 }
933
934 if (d->debug) {
935 time_t now = time(NULL);
936 if (d->last_write && d->last_reg == reg && d->last_val == val) {
937 d->repeat_count++;
938 if (d->last_sec != now) {
939 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
940 d->last_sec = now;
941 d->repeat_count = 0;
942 }
943 } else {
944 if (d->repeat_count) {
945 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
946 }
947 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
948 d->last_write = 1;
949 d->last_reg = reg;
950 d->last_val = val;
951 d->last_sec = now;
952 d->repeat_count = 0;
953 }
954 }
955 assert(reg->offset != 0);
956
957 addr = intel_hda_reg_addr(d, reg);
958 old = *addr;
959
960 if (reg->shift) {
961 val <<= reg->shift;
962 wmask <<= reg->shift;
963 }
964 wmask &= reg->wmask;
965 *addr &= ~wmask;
966 *addr |= wmask & val;
967 *addr &= ~(val & reg->wclear);
968
969 if (reg->whandler) {
970 reg->whandler(d, reg, old);
971 }
972}
973
974static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
975 uint32_t rmask)
976{
977 uint32_t *addr, ret;
978
979 if (!reg) {
980 return 0;
981 }
982
983 if (reg->rhandler) {
984 reg->rhandler(d, reg);
985 }
986
987 if (reg->offset == 0) {
988 /* constant read-only register */
989 ret = reg->reset;
990 } else {
991 addr = intel_hda_reg_addr(d, reg);
992 ret = *addr;
993 if (reg->shift) {
994 ret >>= reg->shift;
995 }
996 ret &= rmask;
997 }
998 if (d->debug) {
999 time_t now = time(NULL);
1000 if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1001 d->repeat_count++;
1002 if (d->last_sec != now) {
1003 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1004 d->last_sec = now;
1005 d->repeat_count = 0;
1006 }
1007 } else {
1008 if (d->repeat_count) {
1009 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1010 }
1011 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1012 d->last_write = 0;
1013 d->last_reg = reg;
1014 d->last_val = ret;
1015 d->last_sec = now;
1016 d->repeat_count = 0;
1017 }
1018 }
1019 return ret;
1020}
1021
1022static void intel_hda_regs_reset(IntelHDAState *d)
1023{
1024 uint32_t *addr;
1025 int i;
1026
1027 for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) {
1028 if (regtab[i].name == NULL) {
1029 continue;
1030 }
1031 if (regtab[i].offset == 0) {
1032 continue;
1033 }
1034 addr = intel_hda_reg_addr(d, regtab + i);
1035 *addr = regtab[i].reset;
1036 }
1037}
1038
1039/* --------------------------------------------------------------------- */
1040
1041static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1042{
1043 IntelHDAState *d = opaque;
1044 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1045
1046 intel_hda_reg_write(d, reg, val, 0xff);
1047}
1048
1049static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1050{
1051 IntelHDAState *d = opaque;
1052 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1053
1054 intel_hda_reg_write(d, reg, val, 0xffff);
1055}
1056
1057static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1058{
1059 IntelHDAState *d = opaque;
1060 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1061
1062 intel_hda_reg_write(d, reg, val, 0xffffffff);
1063}
1064
1065static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr)
1066{
1067 IntelHDAState *d = opaque;
1068 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1069
1070 return intel_hda_reg_read(d, reg, 0xff);
1071}
1072
1073static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr)
1074{
1075 IntelHDAState *d = opaque;
1076 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1077
1078 return intel_hda_reg_read(d, reg, 0xffff);
1079}
1080
1081static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr)
1082{
1083 IntelHDAState *d = opaque;
1084 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1085
1086 return intel_hda_reg_read(d, reg, 0xffffffff);
1087}
1088
234bbdf1
AK		 1089static const MemoryRegionOps intel_hda_mmio_ops = {
1090 .old_mmio = {
1091 .read = {
1092 intel_hda_mmio_readb,
1093 intel_hda_mmio_readw,
1094 intel_hda_mmio_readl,
1095 },
1096 .write = {
1097 intel_hda_mmio_writeb,
1098 intel_hda_mmio_writew,
1099 intel_hda_mmio_writel,
1100 },
1101 },
1102 .endianness = DEVICE_NATIVE_ENDIAN,
d61a4ce8
GH		 1103};
1104
d61a4ce8
GH		 1105/* --------------------------------------------------------------------- */
1106
1107static void intel_hda_reset(DeviceState *dev)
1108{
1109 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev);
1110 DeviceState *qdev;
1111 HDACodecDevice *cdev;
1112
1113 intel_hda_regs_reset(d);
74475455 1114 d->wall_base_ns = qemu_get_clock_ns(vm_clock);
d61a4ce8
GH		 1115
1116 /* reset codecs */
d8bb00d6 1117 QTAILQ_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
d61a4ce8
GH		 1118 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
1119 if (qdev->info->reset) {
1120 qdev->info->reset(qdev);
1121 }
1122 d->state_sts |= (1 << cdev->cad);
1123 }
1124 intel_hda_update_irq(d);
1125}
1126
1127static int intel_hda_init(PCIDevice *pci)
1128{
1129 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1130 uint8_t *conf = d->pci.config;
1131
1132 d->name = d->pci.qdev.info->name;
1133
d61a4ce8
GH		 1134 pci_config_set_interrupt_pin(conf, 1);
1135
1136 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1137 conf[0x40] = 0x01;
1138
234bbdf1
AK		 1139 memory_region_init_io(&d->mmio, &intel_hda_mmio_ops, d,
1140 "intel-hda", 0x4000);
e824b2cc 1141 pci_register_bar(&d->pci, 0, 0, &d->mmio);
17786d52
GH		 1142 if (d->msi) {
1143 msi_init(&d->pci, 0x50, 1, true, false);
1144 }
d61a4ce8
GH		 1145
1146 hda_codec_bus_init(&d->pci.qdev, &d->codecs,
1147 intel_hda_response, intel_hda_xfer);
1148
1149 return 0;
1150}
1151
dc4b9240
GH		 1152static int intel_hda_exit(PCIDevice *pci)
1153{
1154 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1155
45fe15c2 1156 msi_uninit(&d->pci);
234bbdf1 1157 memory_region_destroy(&d->mmio);
dc4b9240
GH		 1158 return 0;
1159}
1160
17786d52
GH		 1161static void intel_hda_write_config(PCIDevice *pci, uint32_t addr,
1162 uint32_t val, int len)
1163{
1164 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1165
1166 pci_default_write_config(pci, addr, val, len);
1167 if (d->msi) {
1168 msi_write_config(pci, addr, val, len);
1169 }
1170}
1171
d61a4ce8
GH		 1172static int intel_hda_post_load(void *opaque, int version)
1173{
1174 IntelHDAState* d = opaque;
1175 int i;
1176
1177 dprint(d, 1, "%s\n", __FUNCTION__);
1178 for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1179 if (d->st[i].ctl & 0x02) {
1180 intel_hda_parse_bdl(d, &d->st[i]);
1181 }
1182 }
1183 intel_hda_update_irq(d);
1184 return 0;
1185}
1186
1187static const VMStateDescription vmstate_intel_hda_stream = {
1188 .name = "intel-hda-stream",
1189 .version_id = 1,
1190 .fields = (VMStateField []) {
1191 VMSTATE_UINT32(ctl, IntelHDAStream),
1192 VMSTATE_UINT32(lpib, IntelHDAStream),
1193 VMSTATE_UINT32(cbl, IntelHDAStream),
1194 VMSTATE_UINT32(lvi, IntelHDAStream),
1195 VMSTATE_UINT32(fmt, IntelHDAStream),
1196 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1197 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1198 VMSTATE_END_OF_LIST()
1199 }
1200};
1201
1202static const VMStateDescription vmstate_intel_hda = {
1203 .name = "intel-hda",
1204 .version_id = 1,
1205 .post_load = intel_hda_post_load,
1206 .fields = (VMStateField []) {
1207 VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1208
1209 /* registers */
1210 VMSTATE_UINT32(g_ctl, IntelHDAState),
1211 VMSTATE_UINT32(wake_en, IntelHDAState),
1212 VMSTATE_UINT32(state_sts, IntelHDAState),
1213 VMSTATE_UINT32(int_ctl, IntelHDAState),
1214 VMSTATE_UINT32(int_sts, IntelHDAState),
1215 VMSTATE_UINT32(wall_clk, IntelHDAState),
1216 VMSTATE_UINT32(corb_lbase, IntelHDAState),
1217 VMSTATE_UINT32(corb_ubase, IntelHDAState),
1218 VMSTATE_UINT32(corb_rp, IntelHDAState),
1219 VMSTATE_UINT32(corb_wp, IntelHDAState),
1220 VMSTATE_UINT32(corb_ctl, IntelHDAState),
1221 VMSTATE_UINT32(corb_sts, IntelHDAState),
1222 VMSTATE_UINT32(corb_size, IntelHDAState),
1223 VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1224 VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1225 VMSTATE_UINT32(rirb_wp, IntelHDAState),
1226 VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1227 VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1228 VMSTATE_UINT32(rirb_sts, IntelHDAState),
1229 VMSTATE_UINT32(rirb_size, IntelHDAState),
1230 VMSTATE_UINT32(dp_lbase, IntelHDAState),
1231 VMSTATE_UINT32(dp_ubase, IntelHDAState),
1232 VMSTATE_UINT32(icw, IntelHDAState),
1233 VMSTATE_UINT32(irr, IntelHDAState),
1234 VMSTATE_UINT32(ics, IntelHDAState),
1235 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1236 vmstate_intel_hda_stream,
1237 IntelHDAStream),
1238
1239 /* additional state info */
1240 VMSTATE_UINT32(rirb_count, IntelHDAState),
1241 VMSTATE_INT64(wall_base_ns, IntelHDAState),
1242
1243 VMSTATE_END_OF_LIST()
1244 }
1245};
1246
1247static PCIDeviceInfo intel_hda_info = {
1248 .qdev.name = "intel-hda",
1249 .qdev.desc = "Intel HD Audio Controller",
1250 .qdev.size = sizeof(IntelHDAState),
1251 .qdev.vmsd = &vmstate_intel_hda,
1252 .qdev.reset = intel_hda_reset,
1253 .init = intel_hda_init,
dc4b9240 1254 .exit = intel_hda_exit,
17786d52 1255 .config_write = intel_hda_write_config,
d15fda63
IY		 1256 .vendor_id = PCI_VENDOR_ID_INTEL,
1257 .device_id = 0x2668,
1258 .revision = 1,
1259 .class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO,
d61a4ce8
GH		 1260 .qdev.props = (Property[]) {
1261 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
17786d52 1262 DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1),
d61a4ce8
GH		 1263 DEFINE_PROP_END_OF_LIST(),
1264 }
1265};
1266
1267static void intel_hda_register(void)
1268{
1269 pci_qdev_register(&intel_hda_info);
1270}
1271device_init(intel_hda_register);
1272
1273/*
1274 * create intel hda controller with codec attached to it,
1275 * so '-soundhw hda' works.
1276 */
1277int intel_hda_and_codec_init(PCIBus *bus)
1278{
1279 PCIDevice *controller;
1280 BusState *hdabus;
1281 DeviceState *codec;
1282
1283 controller = pci_create_simple(bus, -1, "intel-hda");
1284 hdabus = QLIST_FIRST(&controller->qdev.child_bus);
1285 codec = qdev_create(hdabus, "hda-duplex");
1286 qdev_init_nofail(codec);
1287 return 0;
1288}
1289
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