[qemu.git] / hw / timer / imx_epit.c

/*
 * IMX EPIT Timer
 *
 * Copyright (c) 2008 OK Labs
 * Copyright (c) 2011 NICTA Pty Ltd
 * Originally written by Hans Jiang
 * Updated by Peter Chubb
 * Updated by Jean-Christophe Dubois <[email protected]>
 *
 * This code is licensed under GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 *
 */

#include "hw/timer/imx_epit.h"
#include "hw/misc/imx_ccm.h"
#include "qemu/main-loop.h"

#define DEBUG_TIMER 0
#if DEBUG_TIMER

static char const *imx_epit_reg_name(uint32_t reg)
{
    switch (reg) {
    case 0:
        return "CR";
    case 1:
        return "SR";
    case 2:
        return "LR";
    case 3:
        return "CMP";
    case 4:
        return "CNT";
    default:
        return "[?]";
    }
}

#  define DPRINTF(fmt, args...) \
    do { fprintf(stderr, "%s: " fmt , __func__, ##args); } while (0)
#else
#  define DPRINTF(fmt, args...) do {} while (0)
#endif

/*
 * Define to 1 for messages about attempts to
 * access unimplemented registers or similar.
 */
#define DEBUG_IMPLEMENTATION 1
#if DEBUG_IMPLEMENTATION
#  define IPRINTF(fmt, args...) \
          do { fprintf(stderr, "%s: " fmt, __func__, ##args); } while (0)
#else
#  define IPRINTF(fmt, args...) do {} while (0)
#endif

/*
 * Exact clock frequencies vary from board to board.
 * These are typical.
 */
static const IMXClk imx_epit_clocks[] =  {
    0,        /* 00 disabled */
    IPG,      /* 01 ipg_clk, ~532MHz */
    IPG,      /* 10 ipg_clk_highfreq */
    CLK_32k,  /* 11 ipg_clk_32k -- ~32kHz */
};

/*
 * Update interrupt status
 */
static void imx_epit_update_int(IMXEPITState *s)
{
    if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
        qemu_irq_raise(s->irq);
    } else {
        qemu_irq_lower(s->irq);
    }
}

static void imx_epit_set_freq(IMXEPITState *s)
{
    uint32_t clksrc;
    uint32_t prescaler;
    uint32_t freq;

    clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, 2);
    prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, 12);

    freq = imx_clock_frequency(s->ccm, imx_epit_clocks[clksrc]) / prescaler;

    s->freq = freq;

    DPRINTF("Setting ptimer frequency to %u\n", freq);

    if (freq) {
        ptimer_set_freq(s->timer_reload, freq);
        ptimer_set_freq(s->timer_cmp, freq);
    }
}

static void imx_epit_reset(DeviceState *dev)
{
    IMXEPITState *s = IMX_EPIT(dev);

    /*
     * Soft reset doesn't touch some bits; hard reset clears them
     */
    s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
    s->sr = 0;
    s->lr = EPIT_TIMER_MAX;
    s->cmp = 0;
    s->cnt = 0;
    /* stop both timers */
    ptimer_stop(s->timer_cmp);
    ptimer_stop(s->timer_reload);
    /* compute new frequency */
    imx_epit_set_freq(s);
    /* init both timers to EPIT_TIMER_MAX */
    ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
    ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
    if (s->freq && (s->cr & CR_EN)) {
        /* if the timer is still enabled, restart it */
        ptimer_run(s->timer_reload, 0);
    }
}

static uint32_t imx_epit_update_count(IMXEPITState *s)
{
    s->cnt = ptimer_get_count(s->timer_reload);

    return s->cnt;
}

static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
{
    IMXEPITState *s = IMX_EPIT(opaque);
    uint32_t reg_value = 0;
    uint32_t reg = offset >> 2;

    switch (reg) {
    case 0: /* Control Register */
        reg_value = s->cr;
        break;

    case 1: /* Status Register */
        reg_value = s->sr;
        break;

    case 2: /* LR - ticks*/
        reg_value = s->lr;
        break;

    case 3: /* CMP */
        reg_value = s->cmp;
        break;

    case 4: /* CNT */
        imx_epit_update_count(s);
        reg_value = s->cnt;
        break;

    default:
        IPRINTF("Bad offset %x\n", reg);
        break;
    }

    DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(reg), reg_value);

    return reg_value;
}

static void imx_epit_reload_compare_timer(IMXEPITState *s)
{
    if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN))  {
        /* if the compare feature is on and timers are running */
        uint32_t tmp = imx_epit_update_count(s);
        uint64_t next;
        if (tmp > s->cmp) {
            /* It'll fire in this round of the timer */
            next = tmp - s->cmp;
        } else { /* catch it next time around */
            next = tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s->lr);
        }
        ptimer_set_count(s->timer_cmp, next);
    }
}

static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
                           unsigned size)
{
    IMXEPITState *s = IMX_EPIT(opaque);
    uint32_t reg = offset >> 2;
    uint64_t oldcr;

    DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(reg), (uint32_t)value);

    switch (reg) {
    case 0: /* CR */

        oldcr = s->cr;
        s->cr = value & 0x03ffffff;
        if (s->cr & CR_SWR) {
            /* handle the reset */
            imx_epit_reset(DEVICE(s));
        } else {
            imx_epit_set_freq(s);
        }

        if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
            if (s->cr & CR_ENMOD) {
                if (s->cr & CR_RLD) {
                    ptimer_set_limit(s->timer_reload, s->lr, 1);
                    ptimer_set_limit(s->timer_cmp, s->lr, 1);
                } else {
                    ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
                    ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
                }
            }

            imx_epit_reload_compare_timer(s);
            ptimer_run(s->timer_reload, 0);
            if (s->cr & CR_OCIEN) {
                ptimer_run(s->timer_cmp, 0);
            } else {
                ptimer_stop(s->timer_cmp);
            }
        } else if (!(s->cr & CR_EN)) {
            /* stop both timers */
            ptimer_stop(s->timer_reload);
            ptimer_stop(s->timer_cmp);
        } else  if (s->cr & CR_OCIEN) {
            if (!(oldcr & CR_OCIEN)) {
                imx_epit_reload_compare_timer(s);
                ptimer_run(s->timer_cmp, 0);
            }
        } else {
            ptimer_stop(s->timer_cmp);
        }
        break;

    case 1: /* SR - ACK*/
        /* writing 1 to OCIF clear the OCIF bit */
        if (value & 0x01) {
            s->sr = 0;
            imx_epit_update_int(s);
        }
        break;

    case 2: /* LR - set ticks */
        s->lr = value;

        if (s->cr & CR_RLD) {
            /* Also set the limit if the LRD bit is set */
            /* If IOVW bit is set then set the timer value */
            ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
            ptimer_set_limit(s->timer_cmp, s->lr, 0);
        } else if (s->cr & CR_IOVW) {
            /* If IOVW bit is set then set the timer value */
            ptimer_set_count(s->timer_reload, s->lr);
        }

        imx_epit_reload_compare_timer(s);
        break;

    case 3: /* CMP */
        s->cmp = value;

        imx_epit_reload_compare_timer(s);

        break;

    default:
        IPRINTF("Bad offset %x\n", reg);

        break;
    }
}
static void imx_epit_cmp(void *opaque)
{
    IMXEPITState *s = IMX_EPIT(opaque);

    DPRINTF("sr was %d\n", s->sr);

    s->sr = 1;
    imx_epit_update_int(s);
}

static const MemoryRegionOps imx_epit_ops = {
    .read = imx_epit_read,
    .write = imx_epit_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static const VMStateDescription vmstate_imx_timer_epit = {
    .name = TYPE_IMX_EPIT,
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(cr, IMXEPITState),
        VMSTATE_UINT32(sr, IMXEPITState),
        VMSTATE_UINT32(lr, IMXEPITState),
        VMSTATE_UINT32(cmp, IMXEPITState),
        VMSTATE_UINT32(cnt, IMXEPITState),
        VMSTATE_UINT32(freq, IMXEPITState),
        VMSTATE_PTIMER(timer_reload, IMXEPITState),
        VMSTATE_PTIMER(timer_cmp, IMXEPITState),
        VMSTATE_END_OF_LIST()
    }
};

static void imx_epit_realize(DeviceState *dev, Error **errp)
{
    IMXEPITState *s = IMX_EPIT(dev);
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    QEMUBH *bh;

    DPRINTF("\n");

    sysbus_init_irq(sbd, &s->irq);
    memory_region_init_io(&s->iomem, OBJECT(s), &imx_epit_ops, s, TYPE_IMX_EPIT,
                          0x00001000);
    sysbus_init_mmio(sbd, &s->iomem);

    s->timer_reload = ptimer_init(NULL);

    bh = qemu_bh_new(imx_epit_cmp, s);
    s->timer_cmp = ptimer_init(bh);
}

static void imx_epit_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc  = DEVICE_CLASS(klass);

    dc->realize = imx_epit_realize;
    dc->reset = imx_epit_reset;
    dc->vmsd = &vmstate_imx_timer_epit;
    dc->desc = "i.MX periodic timer";
}

static const TypeInfo imx_epit_info = {
    .name = TYPE_IMX_EPIT,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(IMXEPITState),
    .class_init = imx_epit_class_init,
};

static void imx_epit_register_types(void)
{
    type_register_static(&imx_epit_info);
}

type_init(imx_epit_register_types)
Commit	Line	Data
a50c0d6f JCD	1	/*
	2	* IMX EPIT Timer
	3	*
	4	* Copyright (c) 2008 OK Labs
	5	* Copyright (c) 2011 NICTA Pty Ltd
	6	* Originally written by Hans Jiang
	7	* Updated by Peter Chubb
951cd00e	8	* Updated by Jean-Christophe Dubois <[email protected]>
a50c0d6f JCD	9	*
	10	* This code is licensed under GPL version 2 or later. See
	11	* the COPYING file in the top-level directory.
	12	*
	13	*/
	14
951cd00e JCD	15	#include "hw/timer/imx_epit.h"
951cd00e JCD	16	#include "hw/misc/imx_ccm.h"
6a1751b7	17	#include "qemu/main-loop.h"
a50c0d6f	18
95669e69 JCD	19	#define DEBUG_TIMER 0
	20	#if DEBUG_TIMER
	21
	22	static char const *imx_epit_reg_name(uint32_t reg)
	23	{
	24	switch (reg) {
	25	case 0:
	26	return "CR";
	27	case 1:
	28	return "SR";
	29	case 2:
	30	return "LR";
	31	case 3:
	32	return "CMP";
	33	case 4:
	34	return "CNT";
	35	default:
	36	return "[?]";
	37	}
	38	}
	39
a50c0d6f	40	# define DPRINTF(fmt, args...) \
23005810	41	do { fprintf(stderr, "%s: " fmt , __func__, ##args); } while (0)
a50c0d6f JCD	42	#else
	43	# define DPRINTF(fmt, args...) do {} while (0)
	44	#endif
	45
	46	/*
	47	* Define to 1 for messages about attempts to
	48	* access unimplemented registers or similar.
	49	*/
	50	#define DEBUG_IMPLEMENTATION 1
	51	#if DEBUG_IMPLEMENTATION
95669e69 JCD	52	# define IPRINTF(fmt, args...) \
95669e69 JCD	53	do { fprintf(stderr, "%s: " fmt, __func__, ##args); } while (0)
a50c0d6f JCD	54	#else
	55	# define IPRINTF(fmt, args...) do {} while (0)
	56	#endif
	57
a50c0d6f JCD	58	/*
	59	* Exact clock frequencies vary from board to board.
	60	* These are typical.
	61	*/
95669e69	62	static const IMXClk imx_epit_clocks[] = {
a50c0d6f JCD	63	0, /* 00 disabled */
	64	IPG, /* 01 ipg_clk, ~532MHz */
	65	IPG, /* 10 ipg_clk_highfreq */
	66	CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */
	67	};
	68
a50c0d6f JCD	69	/*
	70	* Update interrupt status
	71	*/
95669e69	72	static void imx_epit_update_int(IMXEPITState *s)
a50c0d6f	73	{
95669e69	74	if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
a50c0d6f JCD	75	qemu_irq_raise(s->irq);
	76	} else {
	77	qemu_irq_lower(s->irq);
	78	}
	79	}
	80
95669e69	81	static void imx_epit_set_freq(IMXEPITState *s)
a50c0d6f	82	{
95669e69 JCD	83	uint32_t clksrc;
95669e69 JCD	84	uint32_t prescaler;
a50c0d6f JCD	85	uint32_t freq;
	86
	87	clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, 2);
	88	prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, 12);
	89
95669e69	90	freq = imx_clock_frequency(s->ccm, imx_epit_clocks[clksrc]) / prescaler;
a50c0d6f JCD	91
a50c0d6f JCD	92	s->freq = freq;
95669e69	93
a50c0d6f JCD	94	DPRINTF("Setting ptimer frequency to %u\n", freq);
	95
	96	if (freq) {
	97	ptimer_set_freq(s->timer_reload, freq);
	98	ptimer_set_freq(s->timer_cmp, freq);
	99	}
	100	}
	101
95669e69	102	static void imx_epit_reset(DeviceState *dev)
a50c0d6f	103	{
95669e69	104	IMXEPITState *s = IMX_EPIT(dev);
a50c0d6f JCD	105
	106	/*
	107	* Soft reset doesn't touch some bits; hard reset clears them
	108	*/
23005810	109	s->cr &= (CR_EN\|CR_ENMOD\|CR_STOPEN\|CR_DOZEN\|CR_WAITEN\|CR_DBGEN);
a50c0d6f	110	s->sr = 0;
203d65a4	111	s->lr = EPIT_TIMER_MAX;
a50c0d6f JCD	112	s->cmp = 0;
	113	s->cnt = 0;
	114	/* stop both timers */
	115	ptimer_stop(s->timer_cmp);
	116	ptimer_stop(s->timer_reload);
	117	/* compute new frequency */
95669e69	118	imx_epit_set_freq(s);
203d65a4 MT	119	/* init both timers to EPIT_TIMER_MAX */
	120	ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
	121	ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
a50c0d6f JCD	122	if (s->freq && (s->cr & CR_EN)) {
a50c0d6f JCD	123	/* if the timer is still enabled, restart it */
23005810	124	ptimer_run(s->timer_reload, 0);
a50c0d6f JCD	125	}
	126	}
	127
95669e69	128	static uint32_t imx_epit_update_count(IMXEPITState *s)
a50c0d6f	129	{
565328fc	130	s->cnt = ptimer_get_count(s->timer_reload);
a50c0d6f	131
565328fc	132	return s->cnt;
a50c0d6f JCD	133	}
a50c0d6f JCD	134
95669e69	135	static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
a50c0d6f	136	{
95669e69 JCD	137	IMXEPITState *s = IMX_EPIT(opaque);
	138	uint32_t reg_value = 0;
	139	uint32_t reg = offset >> 2;
a50c0d6f	140
95669e69	141	switch (reg) {
a50c0d6f	142	case 0: /* Control Register */
95669e69 JCD	143	reg_value = s->cr;
95669e69 JCD	144	break;
a50c0d6f JCD	145
a50c0d6f JCD	146	case 1: /* Status Register */
95669e69 JCD	147	reg_value = s->sr;
95669e69 JCD	148	break;
a50c0d6f JCD	149
a50c0d6f JCD	150	case 2: /* LR - ticks*/
95669e69 JCD	151	reg_value = s->lr;
95669e69 JCD	152	break;
a50c0d6f JCD	153
a50c0d6f JCD	154	case 3: /* CMP */
95669e69 JCD	155	reg_value = s->cmp;
95669e69 JCD	156	break;
a50c0d6f JCD	157
a50c0d6f JCD	158	case 4: /* CNT */
95669e69 JCD	159	imx_epit_update_count(s);
	160	reg_value = s->cnt;
	161	break;
	162
	163	default:
	164	IPRINTF("Bad offset %x\n", reg);
	165	break;
a50c0d6f JCD	166	}
a50c0d6f JCD	167
95669e69 JCD	168	DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(reg), reg_value);
	169
	170	return reg_value;
a50c0d6f JCD	171	}
a50c0d6f JCD	172
95669e69	173	static void imx_epit_reload_compare_timer(IMXEPITState *s)
a50c0d6f	174	{
23005810 PC	175	if ((s->cr & (CR_EN \| CR_OCIEN)) == (CR_EN \| CR_OCIEN)) {
23005810 PC	176	/* if the compare feature is on and timers are running */
95669e69	177	uint32_t tmp = imx_epit_update_count(s);
23005810	178	uint64_t next;
a50c0d6f	179	if (tmp > s->cmp) {
23005810 PC	180	/* It'll fire in this round of the timer */
	181	next = tmp - s->cmp;
	182	} else { /* catch it next time around */
203d65a4	183	next = tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s->lr);
a50c0d6f	184	}
23005810	185	ptimer_set_count(s->timer_cmp, next);
a50c0d6f JCD	186	}
	187	}
	188
95669e69 JCD	189	static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
95669e69 JCD	190	unsigned size)
a50c0d6f	191	{
95669e69 JCD	192	IMXEPITState *s = IMX_EPIT(opaque);
95669e69 JCD	193	uint32_t reg = offset >> 2;
23005810	194	uint64_t oldcr;
95669e69 JCD	195
95669e69 JCD	196	DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(reg), (uint32_t)value);
a50c0d6f	197
95669e69	198	switch (reg) {
a50c0d6f	199	case 0: /* CR */
23005810 PC	200
23005810 PC	201	oldcr = s->cr;
a50c0d6f JCD	202	s->cr = value & 0x03ffffff;
	203	if (s->cr & CR_SWR) {
	204	/* handle the reset */
95669e69	205	imx_epit_reset(DEVICE(s));
a50c0d6f	206	} else {
95669e69	207	imx_epit_set_freq(s);
a50c0d6f JCD	208	}
a50c0d6f JCD	209
23005810	210	if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
a50c0d6f JCD	211	if (s->cr & CR_ENMOD) {
	212	if (s->cr & CR_RLD) {
	213	ptimer_set_limit(s->timer_reload, s->lr, 1);
23005810	214	ptimer_set_limit(s->timer_cmp, s->lr, 1);
a50c0d6f	215	} else {
203d65a4 MT	216	ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
203d65a4 MT	217	ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
a50c0d6f JCD	218	}
	219	}
	220
95669e69	221	imx_epit_reload_compare_timer(s);
23005810 PC	222	ptimer_run(s->timer_reload, 0);
	223	if (s->cr & CR_OCIEN) {
	224	ptimer_run(s->timer_cmp, 0);
	225	} else {
	226	ptimer_stop(s->timer_cmp);
	227	}
	228	} else if (!(s->cr & CR_EN)) {
a50c0d6f JCD	229	/* stop both timers */
	230	ptimer_stop(s->timer_reload);
	231	ptimer_stop(s->timer_cmp);
23005810 PC	232	} else if (s->cr & CR_OCIEN) {
	233	if (!(oldcr & CR_OCIEN)) {
	234	imx_epit_reload_compare_timer(s);
	235	ptimer_run(s->timer_cmp, 0);
	236	}
	237	} else {
	238	ptimer_stop(s->timer_cmp);
a50c0d6f JCD	239	}
	240	break;
	241
	242	case 1: /* SR - ACK*/
	243	/* writing 1 to OCIF clear the OCIF bit */
	244	if (value & 0x01) {
	245	s->sr = 0;
95669e69	246	imx_epit_update_int(s);
a50c0d6f JCD	247	}
	248	break;
	249
	250	case 2: /* LR - set ticks */
	251	s->lr = value;
	252
	253	if (s->cr & CR_RLD) {
	254	/* Also set the limit if the LRD bit is set */
	255	/* If IOVW bit is set then set the timer value */
	256	ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
23005810	257	ptimer_set_limit(s->timer_cmp, s->lr, 0);
a50c0d6f JCD	258	} else if (s->cr & CR_IOVW) {
	259	/* If IOVW bit is set then set the timer value */
	260	ptimer_set_count(s->timer_reload, s->lr);
	261	}
	262
95669e69	263	imx_epit_reload_compare_timer(s);
a50c0d6f JCD	264	break;
	265
	266	case 3: /* CMP */
	267	s->cmp = value;
	268
95669e69	269	imx_epit_reload_compare_timer(s);
a50c0d6f JCD	270
	271	break;
	272
	273	default:
95669e69 JCD	274	IPRINTF("Bad offset %x\n", reg);
	275
	276	break;
a50c0d6f JCD	277	}
a50c0d6f JCD	278	}
95669e69	279	static void imx_epit_cmp(void *opaque)
a50c0d6f	280	{
95669e69	281	IMXEPITState *s = IMX_EPIT(opaque);
a50c0d6f	282
23005810	283	DPRINTF("sr was %d\n", s->sr);
a50c0d6f	284
23005810 PC	285	s->sr = 1;
23005810 PC	286	imx_epit_update_int(s);
a50c0d6f JCD	287	}
a50c0d6f JCD	288
95669e69	289	static const MemoryRegionOps imx_epit_ops = {
565328fc JCD	290	.read = imx_epit_read,
	291	.write = imx_epit_write,
	292	.endianness = DEVICE_NATIVE_ENDIAN,
a50c0d6f JCD	293	};
a50c0d6f JCD	294
95669e69	295	static const VMStateDescription vmstate_imx_timer_epit = {
565328fc	296	.name = TYPE_IMX_EPIT,
a50c0d6f JCD	297	.version_id = 2,
a50c0d6f JCD	298	.minimum_version_id = 2,
8f1e884b	299	.fields = (VMStateField[]) {
95669e69 JCD	300	VMSTATE_UINT32(cr, IMXEPITState),
	301	VMSTATE_UINT32(sr, IMXEPITState),
	302	VMSTATE_UINT32(lr, IMXEPITState),
	303	VMSTATE_UINT32(cmp, IMXEPITState),
	304	VMSTATE_UINT32(cnt, IMXEPITState),
	305	VMSTATE_UINT32(freq, IMXEPITState),
	306	VMSTATE_PTIMER(timer_reload, IMXEPITState),
	307	VMSTATE_PTIMER(timer_cmp, IMXEPITState),
a50c0d6f JCD	308	VMSTATE_END_OF_LIST()
	309	}
	310	};
	311
95669e69	312	static void imx_epit_realize(DeviceState dev, Error *errp)
a50c0d6f	313	{
95669e69 JCD	314	IMXEPITState *s = IMX_EPIT(dev);
95669e69 JCD	315	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
a50c0d6f JCD	316	QEMUBH *bh;
a50c0d6f JCD	317
95669e69 JCD	318	DPRINTF("\n");
	319
	320	sysbus_init_irq(sbd, &s->irq);
853dca12	321	memory_region_init_io(&s->iomem, OBJECT(s), &imx_epit_ops, s, TYPE_IMX_EPIT,
a50c0d6f	322	0x00001000);
95669e69	323	sysbus_init_mmio(sbd, &s->iomem);
a50c0d6f	324
23005810	325	s->timer_reload = ptimer_init(NULL);
a50c0d6f	326
95669e69	327	bh = qemu_bh_new(imx_epit_cmp, s);
a50c0d6f	328	s->timer_cmp = ptimer_init(bh);
a50c0d6f JCD	329	}
a50c0d6f JCD	330
95669e69	331	static void imx_epit_class_init(ObjectClass klass, void data)
a50c0d6f JCD	332	{
a50c0d6f JCD	333	DeviceClass *dc = DEVICE_CLASS(klass);
95669e69 JCD	334
	335	dc->realize = imx_epit_realize;
	336	dc->reset = imx_epit_reset;
	337	dc->vmsd = &vmstate_imx_timer_epit;
a50c0d6f JCD	338	dc->desc = "i.MX periodic timer";
	339	}
	340
95669e69 JCD	341	static const TypeInfo imx_epit_info = {
95669e69 JCD	342	.name = TYPE_IMX_EPIT,
a50c0d6f	343	.parent = TYPE_SYS_BUS_DEVICE,
95669e69 JCD	344	.instance_size = sizeof(IMXEPITState),
95669e69 JCD	345	.class_init = imx_epit_class_init,
a50c0d6f JCD	346	};
a50c0d6f JCD	347
95669e69	348	static void imx_epit_register_types(void)
a50c0d6f	349	{
95669e69	350	type_register_static(&imx_epit_info);
a50c0d6f JCD	351	}
a50c0d6f JCD	352
95669e69	353	type_init(imx_epit_register_types)