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8250: Customized base baudrate
[qemu.git] / hw / musicpal.c
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24859b68
AZ		 1/*
2 * Marvell MV88W8618 / Freecom MusicPal emulation.
3 *
4 * Copyright (c) 2008 Jan Kiszka
5 *
6 * This code is licenced under the GNU GPL v2.
7 */
8
9#include "hw.h"
10#include "arm-misc.h"
11#include "devices.h"
12#include "net.h"
13#include "sysemu.h"
14#include "boards.h"
15#include "pc.h"
16#include "qemu-timer.h"
17#include "block.h"
18#include "flash.h"
19#include "console.h"
20#include "audio/audio.h"
21#include "i2c.h"
22
23#define MP_ETH_BASE 0x80008000
24#define MP_ETH_SIZE 0x00001000
25
26#define MP_UART1_BASE 0x8000C840
27#define MP_UART2_BASE 0x8000C940
28
29#define MP_FLASHCFG_BASE 0x90006000
30#define MP_FLASHCFG_SIZE 0x00001000
31
32#define MP_AUDIO_BASE 0x90007000
33#define MP_AUDIO_SIZE 0x00001000
34
35#define MP_PIC_BASE 0x90008000
36#define MP_PIC_SIZE 0x00001000
37
38#define MP_PIT_BASE 0x90009000
39#define MP_PIT_SIZE 0x00001000
40
41#define MP_LCD_BASE 0x9000c000
42#define MP_LCD_SIZE 0x00001000
43
44#define MP_SRAM_BASE 0xC0000000
45#define MP_SRAM_SIZE 0x00020000
46
47#define MP_RAM_DEFAULT_SIZE 32*1024*1024
48#define MP_FLASH_SIZE_MAX 32*1024*1024
49
50#define MP_TIMER1_IRQ 4
51/* ... */
52#define MP_TIMER4_IRQ 7
53#define MP_EHCI_IRQ 8
54#define MP_ETH_IRQ 9
55#define MP_UART1_IRQ 11
56#define MP_UART2_IRQ 11
57#define MP_GPIO_IRQ 12
58#define MP_RTC_IRQ 28
59#define MP_AUDIO_IRQ 30
60
61static uint32_t gpio_in_state = 0xffffffff;
62static uint32_t gpio_out_state;
63static ram_addr_t sram_off;
64
65/* Address conversion helpers */
66static void *target2host_addr(uint32_t addr)
67{
68 if (addr < MP_SRAM_BASE) {
69 if (addr >= MP_RAM_DEFAULT_SIZE)
70 return NULL;
71 return (void *)(phys_ram_base + addr);
72 } else {
73 if (addr >= MP_SRAM_BASE + MP_SRAM_SIZE)
74 return NULL;
75 return (void *)(phys_ram_base + sram_off + addr - MP_SRAM_BASE);
76 }
77}
78
79static uint32_t host2target_addr(void *addr)
80{
81 if (addr < ((void *)phys_ram_base) + sram_off)
82 return (unsigned long)addr - (unsigned long)phys_ram_base;
83 else
84 return (unsigned long)addr - (unsigned long)phys_ram_base -
85 sram_off + MP_SRAM_BASE;
86}
87
88
89typedef enum i2c_state {
90 STOPPED = 0,
91 INITIALIZING,
92 SENDING_BIT7,
93 SENDING_BIT6,
94 SENDING_BIT5,
95 SENDING_BIT4,
96 SENDING_BIT3,
97 SENDING_BIT2,
98 SENDING_BIT1,
99 SENDING_BIT0,
100 WAITING_FOR_ACK,
101 RECEIVING_BIT7,
102 RECEIVING_BIT6,
103 RECEIVING_BIT5,
104 RECEIVING_BIT4,
105 RECEIVING_BIT3,
106 RECEIVING_BIT2,
107 RECEIVING_BIT1,
108 RECEIVING_BIT0,
109 SENDING_ACK
110} i2c_state;
111
112typedef struct i2c_interface {
113 i2c_bus *bus;
114 i2c_state state;
115 int last_data;
116 int last_clock;
117 uint8_t buffer;
118 int current_addr;
119} i2c_interface;
120
121static void i2c_enter_stop(i2c_interface *i2c)
122{
123 if (i2c->current_addr >= 0)
124 i2c_end_transfer(i2c->bus);
125 i2c->current_addr = -1;
126 i2c->state = STOPPED;
127}
128
129static void i2c_state_update(i2c_interface *i2c, int data, int clock)
130{
131 if (!i2c)
132 return;
133
134 switch (i2c->state) {
135 case STOPPED:
136 if (data == 0 && i2c->last_data == 1 && clock == 1)
137 i2c->state = INITIALIZING;
138 break;
139
140 case INITIALIZING:
141 if (clock == 0 && i2c->last_clock == 1 && data == 0)
142 i2c->state = SENDING_BIT7;
143 else
144 i2c_enter_stop(i2c);
145 break;
146
147 case SENDING_BIT7 ... SENDING_BIT0:
148 if (clock == 0 && i2c->last_clock == 1) {
149 i2c->buffer = (i2c->buffer << 1) | data;
150 i2c->state++; /* will end up in WAITING_FOR_ACK */
151 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
152 i2c_enter_stop(i2c);
153 break;
154
155 case WAITING_FOR_ACK:
156 if (clock == 0 && i2c->last_clock == 1) {
157 if (i2c->current_addr < 0) {
158 i2c->current_addr = i2c->buffer;
159 i2c_start_transfer(i2c->bus, i2c->current_addr & 0xfe,
160 i2c->buffer & 1);
161 } else
162 i2c_send(i2c->bus, i2c->buffer);
163 if (i2c->current_addr & 1) {
164 i2c->state = RECEIVING_BIT7;
165 i2c->buffer = i2c_recv(i2c->bus);
166 } else
167 i2c->state = SENDING_BIT7;
168 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
169 i2c_enter_stop(i2c);
170 break;
171
172 case RECEIVING_BIT7 ... RECEIVING_BIT0:
173 if (clock == 0 && i2c->last_clock == 1) {
174 i2c->state++; /* will end up in SENDING_ACK */
175 i2c->buffer <<= 1;
176 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
177 i2c_enter_stop(i2c);
178 break;
179
180 case SENDING_ACK:
181 if (clock == 0 && i2c->last_clock == 1) {
182 i2c->state = RECEIVING_BIT7;
183 if (data == 0)
184 i2c->buffer = i2c_recv(i2c->bus);
185 else
186 i2c_nack(i2c->bus);
187 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
188 i2c_enter_stop(i2c);
189 break;
190 }
191
192 i2c->last_data = data;
193 i2c->last_clock = clock;
194}
195
196static int i2c_get_data(i2c_interface *i2c)
197{
198 if (!i2c)
199 return 0;
200
201 switch (i2c->state) {
202 case RECEIVING_BIT7 ... RECEIVING_BIT0:
203 return (i2c->buffer >> 7);
204
205 case WAITING_FOR_ACK:
206 default:
207 return 0;
208 }
209}
210
211static i2c_interface *mixer_i2c;
212
213#ifdef HAS_AUDIO
214
215/* Audio register offsets */
216#define MP_AUDIO_PLAYBACK_MODE 0x00
217#define MP_AUDIO_CLOCK_DIV 0x18
218#define MP_AUDIO_IRQ_STATUS 0x20
219#define MP_AUDIO_IRQ_ENABLE 0x24
220#define MP_AUDIO_TX_START_LO 0x28
221#define MP_AUDIO_TX_THRESHOLD 0x2C
222#define MP_AUDIO_TX_STATUS 0x38
223#define MP_AUDIO_TX_START_HI 0x40
224
225/* Status register and IRQ enable bits */
226#define MP_AUDIO_TX_HALF (1 << 6)
227#define MP_AUDIO_TX_FULL (1 << 7)
228
229/* Playback mode bits */
230#define MP_AUDIO_16BIT_SAMPLE (1 << 0)
231#define MP_AUDIO_PLAYBACK_EN (1 << 7)
232#define MP_AUDIO_CLOCK_24MHZ (1 << 9)
4001a81e 233#define MP_AUDIO_MONO (1 << 14)
24859b68
AZ		 234
235/* Wolfson 8750 I2C address */
236#define MP_WM_ADDR 0x34
237
238const char audio_name[] = "mv88w8618";
239
240typedef struct musicpal_audio_state {
241 uint32_t base;
242 qemu_irq irq;
243 uint32_t playback_mode;
244 uint32_t status;
245 uint32_t irq_enable;
246 unsigned long phys_buf;
247 void *target_buffer;
248 unsigned int threshold;
249 unsigned int play_pos;
250 unsigned int last_free;
251 uint32_t clock_div;
252 i2c_slave *wm;
253} musicpal_audio_state;
254
255static void audio_callback(void *opaque, int free_out, int free_in)
256{
257 musicpal_audio_state *s = opaque;
4001a81e 258 int16_t *codec_buffer, *mem_buffer;
24859b68
AZ		 259 int pos, block_size;
260
261 if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN))
262 return;
263
264 if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
4001a81e
AZ		 265 free_out <<= 1;
266
267 if (!(s->playback_mode & MP_AUDIO_MONO))
24859b68
AZ		 268 free_out <<= 1;
269
270 block_size = s->threshold/2;
271 if (free_out - s->last_free < block_size)
272 return;
273
4001a81e
AZ		 274 mem_buffer = s->target_buffer + s->play_pos;
275 if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) {
276 if (s->playback_mode & MP_AUDIO_MONO) {
277 codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
278 for (pos = 0; pos < block_size; pos += 2) {
279 *codec_buffer++ = *mem_buffer;
280 *codec_buffer++ = *mem_buffer++;
281 }
282 } else
283 memcpy(wm8750_dac_buffer(s->wm, block_size >> 2),
284 (uint32_t *)mem_buffer, block_size);
285 } else {
286 if (s->playback_mode & MP_AUDIO_MONO) {
287 codec_buffer = wm8750_dac_buffer(s->wm, block_size);
288 for (pos = 0; pos < block_size; pos++) {
289 *codec_buffer++ = cpu_to_le16(256 * *((int8_t *)mem_buffer));
290 *codec_buffer++ = cpu_to_le16(256 * *((int8_t *)mem_buffer)++);
291 }
292 } else {
293 codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
294 for (pos = 0; pos < block_size; pos += 2) {
295 *codec_buffer++ = cpu_to_le16(256 * *((int8_t *)mem_buffer)++);
296 *codec_buffer++ = cpu_to_le16(256 * *((int8_t *)mem_buffer)++);
297 }
24859b68 298 }
662caa6f
AZ		 299 }
300 wm8750_dac_commit(s->wm);
24859b68
AZ		 301
302 s->last_free = free_out - block_size;
303
304 if (s->play_pos == 0) {
305 s->status |= MP_AUDIO_TX_HALF;
306 s->play_pos = block_size;
307 } else {
308 s->status |= MP_AUDIO_TX_FULL;
309 s->play_pos = 0;
310 }
311
312 if (s->status & s->irq_enable)
313 qemu_irq_raise(s->irq);
314}
315
af83e09e
AZ		 316static void musicpal_audio_clock_update(musicpal_audio_state *s)
317{
318 int rate;
319
320 if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ)
321 rate = 24576000 / 64; /* 24.576MHz */
322 else
323 rate = 11289600 / 64; /* 11.2896MHz */
324
325 rate /= ((s->clock_div >> 8) & 0xff) + 1;
326
91834991 327 wm8750_set_bclk_in(s->wm, rate);
af83e09e
AZ		 328}
329
24859b68
AZ		 330static uint32_t musicpal_audio_read(void *opaque, target_phys_addr_t offset)
331{
332 musicpal_audio_state *s = opaque;
333
334 offset -= s->base;
335 switch (offset) {
336 case MP_AUDIO_PLAYBACK_MODE:
337 return s->playback_mode;
338
339 case MP_AUDIO_CLOCK_DIV:
340 return s->clock_div;
341
342 case MP_AUDIO_IRQ_STATUS:
343 return s->status;
344
345 case MP_AUDIO_IRQ_ENABLE:
346 return s->irq_enable;
347
348 case MP_AUDIO_TX_STATUS:
349 return s->play_pos >> 2;
350
351 default:
352 return 0;
353 }
354}
355
356static void musicpal_audio_write(void *opaque, target_phys_addr_t offset,
357 uint32_t value)
358{
359 musicpal_audio_state *s = opaque;
360
361 offset -= s->base;
362 switch (offset) {
363 case MP_AUDIO_PLAYBACK_MODE:
364 if (value & MP_AUDIO_PLAYBACK_EN &&
365 !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) {
366 s->status = 0;
367 s->last_free = 0;
368 s->play_pos = 0;
369 }
370 s->playback_mode = value;
af83e09e 371 musicpal_audio_clock_update(s);
24859b68
AZ		 372 break;
373
374 case MP_AUDIO_CLOCK_DIV:
375 s->clock_div = value;
376 s->last_free = 0;
377 s->play_pos = 0;
af83e09e 378 musicpal_audio_clock_update(s);
24859b68
AZ		 379 break;
380
381 case MP_AUDIO_IRQ_STATUS:
382 s->status &= ~value;
383 break;
384
385 case MP_AUDIO_IRQ_ENABLE:
386 s->irq_enable = value;
387 if (s->status & s->irq_enable)
388 qemu_irq_raise(s->irq);
389 break;
390
391 case MP_AUDIO_TX_START_LO:
392 s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF);
393 s->target_buffer = target2host_addr(s->phys_buf);
394 s->play_pos = 0;
395 s->last_free = 0;
396 break;
397
398 case MP_AUDIO_TX_THRESHOLD:
399 s->threshold = (value + 1) * 4;
400 break;
401
402 case MP_AUDIO_TX_START_HI:
403 s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16);
404 s->target_buffer = target2host_addr(s->phys_buf);
405 s->play_pos = 0;
406 s->last_free = 0;
407 break;
408 }
409}
410
411static void musicpal_audio_reset(void *opaque)
412{
413 musicpal_audio_state *s = opaque;
414
415 s->playback_mode = 0;
416 s->status = 0;
417 s->irq_enable = 0;
418}
419
420static CPUReadMemoryFunc *musicpal_audio_readfn[] = {
421 musicpal_audio_read,
422 musicpal_audio_read,
423 musicpal_audio_read
424};
425
426static CPUWriteMemoryFunc *musicpal_audio_writefn[] = {
427 musicpal_audio_write,
428 musicpal_audio_write,
429 musicpal_audio_write
430};
431
432static i2c_interface *musicpal_audio_init(uint32_t base, qemu_irq irq)
433{
434 AudioState *audio;
435 musicpal_audio_state *s;
436 i2c_interface *i2c;
437 int iomemtype;
438
439 audio = AUD_init();
440 if (!audio) {
441 AUD_log(audio_name, "No audio state\n");
442 return NULL;
443 }
444
445 s = qemu_mallocz(sizeof(musicpal_audio_state));
446 if (!s)
447 return NULL;
448 s->base = base;
449 s->irq = irq;
450
451 i2c = qemu_mallocz(sizeof(i2c_interface));
452 if (!i2c)
453 return NULL;
454 i2c->bus = i2c_init_bus();
455 i2c->current_addr = -1;
456
457 s->wm = wm8750_init(i2c->bus, audio);
458 if (!s->wm)
459 return NULL;
460 i2c_set_slave_address(s->wm, MP_WM_ADDR);
461 wm8750_data_req_set(s->wm, audio_callback, s);
462
463 iomemtype = cpu_register_io_memory(0, musicpal_audio_readfn,
464 musicpal_audio_writefn, s);
465 cpu_register_physical_memory(base, MP_AUDIO_SIZE, iomemtype);
466
467 qemu_register_reset(musicpal_audio_reset, s);
468
469 return i2c;
470}
471#else /* !HAS_AUDIO */
472static i2c_interface *musicpal_audio_init(uint32_t base, qemu_irq irq)
473{
474 return NULL;
475}
476#endif /* !HAS_AUDIO */
477
478/* Ethernet register offsets */
479#define MP_ETH_SMIR 0x010
480#define MP_ETH_PCXR 0x408
481#define MP_ETH_SDCMR 0x448
482#define MP_ETH_ICR 0x450
483#define MP_ETH_IMR 0x458
484#define MP_ETH_FRDP0 0x480
485#define MP_ETH_FRDP1 0x484
486#define MP_ETH_FRDP2 0x488
487#define MP_ETH_FRDP3 0x48C
488#define MP_ETH_CRDP0 0x4A0
489#define MP_ETH_CRDP1 0x4A4
490#define MP_ETH_CRDP2 0x4A8
491#define MP_ETH_CRDP3 0x4AC
492#define MP_ETH_CTDP0 0x4E0
493#define MP_ETH_CTDP1 0x4E4
494#define MP_ETH_CTDP2 0x4E8
495#define MP_ETH_CTDP3 0x4EC
496
497/* MII PHY access */
498#define MP_ETH_SMIR_DATA 0x0000FFFF
499#define MP_ETH_SMIR_ADDR 0x03FF0000
500#define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */
501#define MP_ETH_SMIR_RDVALID (1 << 27)
502
503/* PHY registers */
504#define MP_ETH_PHY1_BMSR 0x00210000
505#define MP_ETH_PHY1_PHYSID1 0x00410000
506#define MP_ETH_PHY1_PHYSID2 0x00610000
507
508#define MP_PHY_BMSR_LINK 0x0004
509#define MP_PHY_BMSR_AUTONEG 0x0008
510
511#define MP_PHY_88E3015 0x01410E20
512
513/* TX descriptor status */
514#define MP_ETH_TX_OWN (1 << 31)
515
516/* RX descriptor status */
517#define MP_ETH_RX_OWN (1 << 31)
518
519/* Interrupt cause/mask bits */
520#define MP_ETH_IRQ_RX_BIT 0
521#define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT)
522#define MP_ETH_IRQ_TXHI_BIT 2
523#define MP_ETH_IRQ_TXLO_BIT 3
524
525/* Port config bits */
526#define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */
527
528/* SDMA command bits */
529#define MP_ETH_CMD_TXHI (1 << 23)
530#define MP_ETH_CMD_TXLO (1 << 22)
531
532typedef struct mv88w8618_tx_desc {
533 uint32_t cmdstat;
534 uint16_t res;
535 uint16_t bytes;
536 uint32_t buffer;
537 uint32_t next;
538} mv88w8618_tx_desc;
539
540typedef struct mv88w8618_rx_desc {
541 uint32_t cmdstat;
542 uint16_t bytes;
543 uint16_t buffer_size;
544 uint32_t buffer;
545 uint32_t next;
546} mv88w8618_rx_desc;
547
548typedef struct mv88w8618_eth_state {
549 uint32_t base;
550 qemu_irq irq;
551 uint32_t smir;
552 uint32_t icr;
553 uint32_t imr;
554 int vlan_header;
555 mv88w8618_tx_desc *tx_queue[2];
556 mv88w8618_rx_desc *rx_queue[4];
557 mv88w8618_rx_desc *frx_queue[4];
558 mv88w8618_rx_desc *cur_rx[4];
559 VLANClientState *vc;
560} mv88w8618_eth_state;
561
562static int eth_can_receive(void *opaque)
563{
564 return 1;
565}
566
567static void eth_receive(void *opaque, const uint8_t *buf, int size)
568{
569 mv88w8618_eth_state *s = opaque;
570 mv88w8618_rx_desc *desc;
571 int i;
572
573 for (i = 0; i < 4; i++) {
574 desc = s->cur_rx[i];
575 if (!desc)
576 continue;
577 do {
578 if (le32_to_cpu(desc->cmdstat) & MP_ETH_RX_OWN &&
579 le16_to_cpu(desc->buffer_size) >= size) {
580 memcpy(target2host_addr(le32_to_cpu(desc->buffer) +
581 s->vlan_header),
582 buf, size);
583 desc->bytes = cpu_to_le16(size + s->vlan_header);
584 desc->cmdstat &= cpu_to_le32(~MP_ETH_RX_OWN);
585 s->cur_rx[i] = target2host_addr(le32_to_cpu(desc->next));
586
587 s->icr |= MP_ETH_IRQ_RX;
588 if (s->icr & s->imr)
589 qemu_irq_raise(s->irq);
590 return;
591 }
592 desc = target2host_addr(le32_to_cpu(desc->next));
593 } while (desc != s->rx_queue[i]);
594 }
595}
596
597static void eth_send(mv88w8618_eth_state *s, int queue_index)
598{
599 mv88w8618_tx_desc *desc = s->tx_queue[queue_index];
600
601 do {
602 if (le32_to_cpu(desc->cmdstat) & MP_ETH_TX_OWN) {
603 qemu_send_packet(s->vc,
604 target2host_addr(le32_to_cpu(desc->buffer)),
605 le16_to_cpu(desc->bytes));
606 desc->cmdstat &= cpu_to_le32(~MP_ETH_TX_OWN);
607 s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
608 }
609 desc = target2host_addr(le32_to_cpu(desc->next));
610 } while (desc != s->tx_queue[queue_index]);
611}
612
613static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
614{
615 mv88w8618_eth_state *s = opaque;
616
617 offset -= s->base;
618 switch (offset) {
619 case MP_ETH_SMIR:
620 if (s->smir & MP_ETH_SMIR_OPCODE) {
621 switch (s->smir & MP_ETH_SMIR_ADDR) {
622 case MP_ETH_PHY1_BMSR:
623 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
624 MP_ETH_SMIR_RDVALID;
625 case MP_ETH_PHY1_PHYSID1:
626 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
627 case MP_ETH_PHY1_PHYSID2:
628 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
629 default:
630 return MP_ETH_SMIR_RDVALID;
631 }
632 }
633 return 0;
634
635 case MP_ETH_ICR:
636 return s->icr;
637
638 case MP_ETH_IMR:
639 return s->imr;
640
641 case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
642 return host2target_addr(s->frx_queue[(offset - MP_ETH_FRDP0)/4]);
643
644 case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
645 return host2target_addr(s->rx_queue[(offset - MP_ETH_CRDP0)/4]);
646
647 case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
648 return host2target_addr(s->tx_queue[(offset - MP_ETH_CTDP0)/4]);
649
650 default:
651 return 0;
652 }
653}
654
655static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
656 uint32_t value)
657{
658 mv88w8618_eth_state *s = opaque;
659
660 offset -= s->base;
661 switch (offset) {
662 case MP_ETH_SMIR:
663 s->smir = value;
664 break;
665
666 case MP_ETH_PCXR:
667 s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
668 break;
669
670 case MP_ETH_SDCMR:
671 if (value & MP_ETH_CMD_TXHI)
672 eth_send(s, 1);
673 if (value & MP_ETH_CMD_TXLO)
674 eth_send(s, 0);
675 if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
676 qemu_irq_raise(s->irq);
677 break;
678
679 case MP_ETH_ICR:
680 s->icr &= value;
681 break;
682
683 case MP_ETH_IMR:
684 s->imr = value;
685 if (s->icr & s->imr)
686 qemu_irq_raise(s->irq);
687 break;
688
689 case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
690 s->frx_queue[(offset - MP_ETH_FRDP0)/4] = target2host_addr(value);
691 break;
692
693 case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
694 s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
695 s->cur_rx[(offset - MP_ETH_CRDP0)/4] = target2host_addr(value);
696 break;
697
698 case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
699 s->tx_queue[(offset - MP_ETH_CTDP0)/4] = target2host_addr(value);
700 break;
701 }
702}
703
704static CPUReadMemoryFunc *mv88w8618_eth_readfn[] = {
705 mv88w8618_eth_read,
706 mv88w8618_eth_read,
707 mv88w8618_eth_read
708};
709
710static CPUWriteMemoryFunc *mv88w8618_eth_writefn[] = {
711 mv88w8618_eth_write,
712 mv88w8618_eth_write,
713 mv88w8618_eth_write
714};
715
716static void mv88w8618_eth_init(NICInfo *nd, uint32_t base, qemu_irq irq)
717{
718 mv88w8618_eth_state *s;
719 int iomemtype;
720
721 s = qemu_mallocz(sizeof(mv88w8618_eth_state));
722 if (!s)
723 return;
724 s->base = base;
725 s->irq = irq;
726 s->vc = qemu_new_vlan_client(nd->vlan, eth_receive, eth_can_receive, s);
727 iomemtype = cpu_register_io_memory(0, mv88w8618_eth_readfn,
728 mv88w8618_eth_writefn, s);
729 cpu_register_physical_memory(base, MP_ETH_SIZE, iomemtype);
730}
731
732/* LCD register offsets */
733#define MP_LCD_IRQCTRL 0x180
734#define MP_LCD_IRQSTAT 0x184
735#define MP_LCD_SPICTRL 0x1ac
736#define MP_LCD_INST 0x1bc
737#define MP_LCD_DATA 0x1c0
738
739/* Mode magics */
740#define MP_LCD_SPI_DATA 0x00100011
741#define MP_LCD_SPI_CMD 0x00104011
742#define MP_LCD_SPI_INVALID 0x00000000
743
744/* Commmands */
745#define MP_LCD_INST_SETPAGE0 0xB0
746/* ... */
747#define MP_LCD_INST_SETPAGE7 0xB7
748
749#define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
750
751typedef struct musicpal_lcd_state {
752 uint32_t base;
753 uint32_t mode;
754 uint32_t irqctrl;
755 int page;
756 int page_off;
757 DisplayState *ds;
758 uint8_t video_ram[128*64/8];
759} musicpal_lcd_state;
760
761static uint32_t lcd_brightness;
762
763static uint8_t scale_lcd_color(uint8_t col)
764{
765 int tmp = col;
766
767 switch (lcd_brightness) {
768 case 0x00000007: /* 0 */
769 return 0;
770
771 case 0x00020000: /* 1 */
772 return (tmp * 1) / 7;
773
774 case 0x00020001: /* 2 */
775 return (tmp * 2) / 7;
776
777 case 0x00040000: /* 3 */
778 return (tmp * 3) / 7;
779
780 case 0x00010006: /* 4 */
781 return (tmp * 4) / 7;
782
783 case 0x00020005: /* 5 */
784 return (tmp * 5) / 7;
785
786 case 0x00040003: /* 6 */
787 return (tmp * 6) / 7;
788
789 case 0x00030004: /* 7 */
790 default:
791 return col;
792 }
793}
794
0266f2c7
AZ		 795#define SET_LCD_PIXEL(depth, type) \
796static inline void glue(set_lcd_pixel, depth) \
797 (musicpal_lcd_state *s, int x, int y, type col) \
798{ \
799 int dx, dy; \
800 type *pixel = &((type *) s->ds->data)[(y * 128 * 3 + x) * 3]; \
801\
802 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
803 for (dx = 0; dx < 3; dx++, pixel++) \
804 *pixel = col; \
24859b68 805}
0266f2c7
AZ		 806SET_LCD_PIXEL(8, uint8_t)
807SET_LCD_PIXEL(16, uint16_t)
808SET_LCD_PIXEL(32, uint32_t)
809
810#include "pixel_ops.h"
24859b68
AZ		 811
812static void lcd_refresh(void *opaque)
813{
814 musicpal_lcd_state *s = opaque;
0266f2c7 815 int x, y, col;
24859b68 816
0266f2c7
AZ		 817 switch (s->ds->depth) {
818 case 0:
819 return;
820#define LCD_REFRESH(depth, func) \
821 case depth: \
822 col = func(scale_lcd_color((MP_LCD_TEXTCOLOR >> 16) & 0xff), \
823 scale_lcd_color((MP_LCD_TEXTCOLOR >> 8) & 0xff), \
824 scale_lcd_color(MP_LCD_TEXTCOLOR & 0xff)); \
825 for (x = 0; x < 128; x++) \
826 for (y = 0; y < 64; y++) \
827 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \
828 glue(set_lcd_pixel, depth)(s, x, y, col); \
829 else \
830 glue(set_lcd_pixel, depth)(s, x, y, 0); \
831 break;
832 LCD_REFRESH(8, rgb_to_pixel8)
833 LCD_REFRESH(16, rgb_to_pixel16)
834 LCD_REFRESH(32, (s->ds->bgr ? rgb_to_pixel32bgr : rgb_to_pixel32))
835 default:
836 cpu_abort(cpu_single_env, "unsupported colour depth %i\n",
837 s->ds->depth);
838 }
24859b68
AZ		 839
840 dpy_update(s->ds, 0, 0, 128*3, 64*3);
841}
842
843static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
844{
845 musicpal_lcd_state *s = opaque;
846
847 offset -= s->base;
848 switch (offset) {
849 case MP_LCD_IRQCTRL:
850 return s->irqctrl;
851
852 default:
853 return 0;
854 }
855}
856
857static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
858 uint32_t value)
859{
860 musicpal_lcd_state *s = opaque;
861
862 offset -= s->base;
863 switch (offset) {
864 case MP_LCD_IRQCTRL:
865 s->irqctrl = value;
866 break;
867
868 case MP_LCD_SPICTRL:
869 if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
870 s->mode = value;
871 else
872 s->mode = MP_LCD_SPI_INVALID;
873 break;
874
875 case MP_LCD_INST:
876 if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
877 s->page = value - MP_LCD_INST_SETPAGE0;
878 s->page_off = 0;
879 }
880 break;
881
882 case MP_LCD_DATA:
883 if (s->mode == MP_LCD_SPI_CMD) {
884 if (value >= MP_LCD_INST_SETPAGE0 &&
885 value <= MP_LCD_INST_SETPAGE7) {
886 s->page = value - MP_LCD_INST_SETPAGE0;
887 s->page_off = 0;
888 }
889 } else if (s->mode == MP_LCD_SPI_DATA) {
890 s->video_ram[s->page*128 + s->page_off] = value;
891 s->page_off = (s->page_off + 1) & 127;
892 }
893 break;
894 }
895}
896
897static CPUReadMemoryFunc *musicpal_lcd_readfn[] = {
898 musicpal_lcd_read,
899 musicpal_lcd_read,
900 musicpal_lcd_read
901};
902
903static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = {
904 musicpal_lcd_write,
905 musicpal_lcd_write,
906 musicpal_lcd_write
907};
908
909static void musicpal_lcd_init(DisplayState *ds, uint32_t base)
910{
911 musicpal_lcd_state *s;
912 int iomemtype;
913
914 s = qemu_mallocz(sizeof(musicpal_lcd_state));
915 if (!s)
916 return;
917 s->base = base;
918 s->ds = ds;
919 iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
920 musicpal_lcd_writefn, s);
921 cpu_register_physical_memory(base, MP_LCD_SIZE, iomemtype);
922
923 graphic_console_init(ds, lcd_refresh, NULL, NULL, NULL, s);
924 dpy_resize(ds, 128*3, 64*3);
925}
926
927/* PIC register offsets */
928#define MP_PIC_STATUS 0x00
929#define MP_PIC_ENABLE_SET 0x08
930#define MP_PIC_ENABLE_CLR 0x0C
931
932typedef struct mv88w8618_pic_state
933{
934 uint32_t base;
935 uint32_t level;
936 uint32_t enabled;
937 qemu_irq parent_irq;
938} mv88w8618_pic_state;
939
940static void mv88w8618_pic_update(mv88w8618_pic_state *s)
941{
942 qemu_set_irq(s->parent_irq, (s->level & s->enabled));
943}
944
945static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
946{
947 mv88w8618_pic_state *s = opaque;
948
949 if (level)
950 s->level |= 1 << irq;
951 else
952 s->level &= ~(1 << irq);
953 mv88w8618_pic_update(s);
954}
955
956static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
957{
958 mv88w8618_pic_state *s = opaque;
959
960 offset -= s->base;
961 switch (offset) {
962 case MP_PIC_STATUS:
963 return s->level & s->enabled;
964
965 default:
966 return 0;
967 }
968}
969
970static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
971 uint32_t value)
972{
973 mv88w8618_pic_state *s = opaque;
974
975 offset -= s->base;
976 switch (offset) {
977 case MP_PIC_ENABLE_SET:
978 s->enabled |= value;
979 break;
980
981 case MP_PIC_ENABLE_CLR:
982 s->enabled &= ~value;
983 s->level &= ~value;
984 break;
985 }
986 mv88w8618_pic_update(s);
987}
988
989static void mv88w8618_pic_reset(void *opaque)
990{
991 mv88w8618_pic_state *s = opaque;
992
993 s->level = 0;
994 s->enabled = 0;
995}
996
997static CPUReadMemoryFunc *mv88w8618_pic_readfn[] = {
998 mv88w8618_pic_read,
999 mv88w8618_pic_read,
1000 mv88w8618_pic_read
1001};
1002
1003static CPUWriteMemoryFunc *mv88w8618_pic_writefn[] = {
1004 mv88w8618_pic_write,
1005 mv88w8618_pic_write,
1006 mv88w8618_pic_write
1007};
1008
1009static qemu_irq *mv88w8618_pic_init(uint32_t base, qemu_irq parent_irq)
1010{
1011 mv88w8618_pic_state *s;
1012 int iomemtype;
1013 qemu_irq *qi;
1014
1015 s = qemu_mallocz(sizeof(mv88w8618_pic_state));
1016 if (!s)
1017 return NULL;
1018 qi = qemu_allocate_irqs(mv88w8618_pic_set_irq, s, 32);
1019 s->base = base;
1020 s->parent_irq = parent_irq;
1021 iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
1022 mv88w8618_pic_writefn, s);
1023 cpu_register_physical_memory(base, MP_PIC_SIZE, iomemtype);
1024
1025 qemu_register_reset(mv88w8618_pic_reset, s);
1026
1027 return qi;
1028}
1029
1030/* PIT register offsets */
1031#define MP_PIT_TIMER1_LENGTH 0x00
1032/* ... */
1033#define MP_PIT_TIMER4_LENGTH 0x0C
1034#define MP_PIT_CONTROL 0x10
1035#define MP_PIT_TIMER1_VALUE 0x14
1036/* ... */
1037#define MP_PIT_TIMER4_VALUE 0x20
1038#define MP_BOARD_RESET 0x34
1039
1040/* Magic board reset value (probably some watchdog behind it) */
1041#define MP_BOARD_RESET_MAGIC 0x10000
1042
1043typedef struct mv88w8618_timer_state {
1044 ptimer_state *timer;
1045 uint32_t limit;
1046 int freq;
1047 qemu_irq irq;
1048} mv88w8618_timer_state;
1049
1050typedef struct mv88w8618_pit_state {
1051 void *timer[4];
1052 uint32_t control;
1053 uint32_t base;
1054} mv88w8618_pit_state;
1055
1056static void mv88w8618_timer_tick(void *opaque)
1057{
1058 mv88w8618_timer_state *s = opaque;
1059
1060 qemu_irq_raise(s->irq);
1061}
1062
1063static void *mv88w8618_timer_init(uint32_t freq, qemu_irq irq)
1064{
1065 mv88w8618_timer_state *s;
1066 QEMUBH *bh;
1067
1068 s = qemu_mallocz(sizeof(mv88w8618_timer_state));
1069 s->irq = irq;
1070 s->freq = freq;
1071
1072 bh = qemu_bh_new(mv88w8618_timer_tick, s);
1073 s->timer = ptimer_init(bh);
1074
1075 return s;
1076}
1077
1078static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
1079{
1080 mv88w8618_pit_state *s = opaque;
1081 mv88w8618_timer_state *t;
1082
1083 offset -= s->base;
1084 switch (offset) {
1085 case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
1086 t = s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
1087 return ptimer_get_count(t->timer);
1088
1089 default:
1090 return 0;
1091 }
1092}
1093
1094static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
1095 uint32_t value)
1096{
1097 mv88w8618_pit_state *s = opaque;
1098 mv88w8618_timer_state *t;
1099 int i;
1100
1101 offset -= s->base;
1102 switch (offset) {
1103 case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
1104 t = s->timer[offset >> 2];
1105 t->limit = value;
1106 ptimer_set_limit(t->timer, t->limit, 1);
1107 break;
1108
1109 case MP_PIT_CONTROL:
1110 for (i = 0; i < 4; i++) {
1111 if (value & 0xf) {
1112 t = s->timer[i];
1113 ptimer_set_limit(t->timer, t->limit, 0);
1114 ptimer_set_freq(t->timer, t->freq);
1115 ptimer_run(t->timer, 0);
1116 }
1117 value >>= 4;
1118 }
1119 break;
1120
1121 case MP_BOARD_RESET:
1122 if (value == MP_BOARD_RESET_MAGIC)
1123 qemu_system_reset_request();
1124 break;
1125 }
1126}
1127
1128static CPUReadMemoryFunc *mv88w8618_pit_readfn[] = {
1129 mv88w8618_pit_read,
1130 mv88w8618_pit_read,
1131 mv88w8618_pit_read
1132};
1133
1134static CPUWriteMemoryFunc *mv88w8618_pit_writefn[] = {
1135 mv88w8618_pit_write,
1136 mv88w8618_pit_write,
1137 mv88w8618_pit_write
1138};
1139
1140static void mv88w8618_pit_init(uint32_t base, qemu_irq *pic, int irq)
1141{
1142 int iomemtype;
1143 mv88w8618_pit_state *s;
1144
1145 s = qemu_mallocz(sizeof(mv88w8618_pit_state));
1146 if (!s)
1147 return;
1148
1149 s->base = base;
1150 /* Letting them all run at 1 MHz is likely just a pragmatic
1151 * simplification. */
1152 s->timer[0] = mv88w8618_timer_init(1000000, pic[irq]);
1153 s->timer[1] = mv88w8618_timer_init(1000000, pic[irq + 1]);
1154 s->timer[2] = mv88w8618_timer_init(1000000, pic[irq + 2]);
1155 s->timer[3] = mv88w8618_timer_init(1000000, pic[irq + 3]);
1156
1157 iomemtype = cpu_register_io_memory(0, mv88w8618_pit_readfn,
1158 mv88w8618_pit_writefn, s);
1159 cpu_register_physical_memory(base, MP_PIT_SIZE, iomemtype);
1160}
1161
1162/* Flash config register offsets */
1163#define MP_FLASHCFG_CFGR0 0x04
1164
1165typedef struct mv88w8618_flashcfg_state {
1166 uint32_t base;
1167 uint32_t cfgr0;
1168} mv88w8618_flashcfg_state;
1169
1170static uint32_t mv88w8618_flashcfg_read(void *opaque,
1171 target_phys_addr_t offset)
1172{
1173 mv88w8618_flashcfg_state *s = opaque;
1174
1175 offset -= s->base;
1176 switch (offset) {
1177 case MP_FLASHCFG_CFGR0:
1178 return s->cfgr0;
1179
1180 default:
1181 return 0;
1182 }
1183}
1184
1185static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
1186 uint32_t value)
1187{
1188 mv88w8618_flashcfg_state *s = opaque;
1189
1190 offset -= s->base;
1191 switch (offset) {
1192 case MP_FLASHCFG_CFGR0:
1193 s->cfgr0 = value;
1194 break;
1195 }
1196}
1197
1198static CPUReadMemoryFunc *mv88w8618_flashcfg_readfn[] = {
1199 mv88w8618_flashcfg_read,
1200 mv88w8618_flashcfg_read,
1201 mv88w8618_flashcfg_read
1202};
1203
1204static CPUWriteMemoryFunc *mv88w8618_flashcfg_writefn[] = {
1205 mv88w8618_flashcfg_write,
1206 mv88w8618_flashcfg_write,
1207 mv88w8618_flashcfg_write
1208};
1209
1210static void mv88w8618_flashcfg_init(uint32_t base)
1211{
1212 int iomemtype;
1213 mv88w8618_flashcfg_state *s;
1214
1215 s = qemu_mallocz(sizeof(mv88w8618_flashcfg_state));
1216 if (!s)
1217 return;
1218
1219 s->base = base;
1220 s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1221 iomemtype = cpu_register_io_memory(0, mv88w8618_flashcfg_readfn,
1222 mv88w8618_flashcfg_writefn, s);
1223 cpu_register_physical_memory(base, MP_FLASHCFG_SIZE, iomemtype);
1224}
1225
1226/* Various registers in the 0x80000000 domain */
1227#define MP_BOARD_REVISION 0x2018
1228
1229#define MP_WLAN_MAGIC1 0xc11c
1230#define MP_WLAN_MAGIC2 0xc124
1231
1232#define MP_GPIO_OE_LO 0xd008
1233#define MP_GPIO_OUT_LO 0xd00c
1234#define MP_GPIO_IN_LO 0xd010
1235#define MP_GPIO_ISR_LO 0xd020
1236#define MP_GPIO_OE_HI 0xd508
1237#define MP_GPIO_OUT_HI 0xd50c
1238#define MP_GPIO_IN_HI 0xd510
1239#define MP_GPIO_ISR_HI 0xd520
1240
1241/* GPIO bits & masks */
1242#define MP_GPIO_WHEEL_VOL (1 << 8)
1243#define MP_GPIO_WHEEL_VOL_INV (1 << 9)
1244#define MP_GPIO_WHEEL_NAV (1 << 10)
1245#define MP_GPIO_WHEEL_NAV_INV (1 << 11)
1246#define MP_GPIO_LCD_BRIGHTNESS 0x00070000
1247#define MP_GPIO_BTN_FAVORITS (1 << 19)
1248#define MP_GPIO_BTN_MENU (1 << 20)
1249#define MP_GPIO_BTN_VOLUME (1 << 21)
1250#define MP_GPIO_BTN_NAVIGATION (1 << 22)
1251#define MP_GPIO_I2C_DATA_BIT 29
1252#define MP_GPIO_I2C_DATA (1 << MP_GPIO_I2C_DATA_BIT)
1253#define MP_GPIO_I2C_CLOCK_BIT 30
1254
1255/* LCD brightness bits in GPIO_OE_HI */
1256#define MP_OE_LCD_BRIGHTNESS 0x0007
1257
1258static uint32_t musicpal_read(void *opaque, target_phys_addr_t offset)
1259{
1260 offset -= 0x80000000;
1261 switch (offset) {
1262 case MP_BOARD_REVISION:
1263 return 0x0031;
1264
1265 case MP_GPIO_OE_HI: /* used for LCD brightness control */
1266 return lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1267
1268 case MP_GPIO_OUT_LO:
1269 return gpio_out_state & 0xFFFF;
1270 case MP_GPIO_OUT_HI:
1271 return gpio_out_state >> 16;
1272
1273 case MP_GPIO_IN_LO:
1274 return gpio_in_state & 0xFFFF;
1275 case MP_GPIO_IN_HI:
1276 /* Update received I2C data */
1277 gpio_in_state = (gpio_in_state & ~MP_GPIO_I2C_DATA) |
1278 (i2c_get_data(mixer_i2c) << MP_GPIO_I2C_DATA_BIT);
1279 return gpio_in_state >> 16;
1280
1281 /* This is a simplification of reality */
1282 case MP_GPIO_ISR_LO:
1283 return ~gpio_in_state & 0xFFFF;
1284 case MP_GPIO_ISR_HI:
1285 return ~gpio_in_state >> 16;
1286
1287 /* Workaround to allow loading the binary-only wlandrv.ko crap
1288 * from the original Freecom firmware. */
1289 case MP_WLAN_MAGIC1:
1290 return ~3;
1291 case MP_WLAN_MAGIC2:
1292 return -1;
1293
1294 default:
1295 return 0;
1296 }
1297}
1298
1299static void musicpal_write(void *opaque, target_phys_addr_t offset,
1300 uint32_t value)
1301{
1302 offset -= 0x80000000;
1303 switch (offset) {
1304 case MP_GPIO_OE_HI: /* used for LCD brightness control */
1305 lcd_brightness = (lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1306 (value & MP_OE_LCD_BRIGHTNESS);
1307 break;
1308
1309 case MP_GPIO_OUT_LO:
1310 gpio_out_state = (gpio_out_state & 0xFFFF0000) | (value & 0xFFFF);
1311 break;
1312 case MP_GPIO_OUT_HI:
1313 gpio_out_state = (gpio_out_state & 0xFFFF) | (value << 16);
1314 lcd_brightness = (lcd_brightness & 0xFFFF) |
1315 (gpio_out_state & MP_GPIO_LCD_BRIGHTNESS);
1316 i2c_state_update(mixer_i2c,
1317 (gpio_out_state >> MP_GPIO_I2C_DATA_BIT) & 1,
1318 (gpio_out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1319 break;
1320
1321 }
1322}
1323
1324/* Keyboard codes & masks */
1325#define KEY_PRESSED 0x80
1326#define KEY_CODE 0x7f
1327
1328#define KEYCODE_TAB 0x0f
1329#define KEYCODE_ENTER 0x1c
1330#define KEYCODE_F 0x21
1331#define KEYCODE_M 0x32
1332
1333#define KEYCODE_EXTENDED 0xe0
1334#define KEYCODE_UP 0x48
1335#define KEYCODE_DOWN 0x50
1336#define KEYCODE_LEFT 0x4b
1337#define KEYCODE_RIGHT 0x4d
1338
1339static void musicpal_key_event(void *opaque, int keycode)
1340{
1341 qemu_irq irq = opaque;
1342 uint32_t event = 0;
1343 static int kbd_extended;
1344
1345 if (keycode == KEYCODE_EXTENDED) {
1346 kbd_extended = 1;
1347 return;
1348 }
1349
1350 if (kbd_extended)
1351 switch (keycode & KEY_CODE) {
1352 case KEYCODE_UP:
1353 event = MP_GPIO_WHEEL_NAV | MP_GPIO_WHEEL_NAV_INV;
1354 break;
1355
1356 case KEYCODE_DOWN:
1357 event = MP_GPIO_WHEEL_NAV;
1358 break;
1359
1360 case KEYCODE_LEFT:
1361 event = MP_GPIO_WHEEL_VOL | MP_GPIO_WHEEL_VOL_INV;
1362 break;
1363
1364 case KEYCODE_RIGHT:
1365 event = MP_GPIO_WHEEL_VOL;
1366 break;
1367 }
1368 else
1369 switch (keycode & KEY_CODE) {
1370 case KEYCODE_F:
1371 event = MP_GPIO_BTN_FAVORITS;
1372 break;
1373
1374 case KEYCODE_TAB:
1375 event = MP_GPIO_BTN_VOLUME;
1376 break;
1377
1378 case KEYCODE_ENTER:
1379 event = MP_GPIO_BTN_NAVIGATION;
1380 break;
1381
1382 case KEYCODE_M:
1383 event = MP_GPIO_BTN_MENU;
1384 break;
1385 }
1386
1387 if (keycode & KEY_PRESSED)
1388 gpio_in_state |= event;
1389 else if (gpio_in_state & event) {
1390 gpio_in_state &= ~event;
1391 qemu_irq_raise(irq);
1392 }
1393
1394 kbd_extended = 0;
1395}
1396
1397static CPUReadMemoryFunc *musicpal_readfn[] = {
1398 musicpal_read,
1399 musicpal_read,
1400 musicpal_read,
1401};
1402
1403static CPUWriteMemoryFunc *musicpal_writefn[] = {
1404 musicpal_write,
1405 musicpal_write,
1406 musicpal_write,
1407};
1408
1409static struct arm_boot_info musicpal_binfo = {
1410 .loader_start = 0x0,
1411 .board_id = 0x20e,
1412};
1413
b0f6edb1 1414static void musicpal_init(ram_addr_t ram_size, int vga_ram_size,
24859b68
AZ		 1415 const char *boot_device, DisplayState *ds,
1416 const char *kernel_filename, const char *kernel_cmdline,
1417 const char *initrd_filename, const char *cpu_model)
1418{
1419 CPUState *env;
1420 qemu_irq *pic;
1421 int index;
1422 int iomemtype;
1423 unsigned long flash_size;
1424
1425 if (!cpu_model)
1426 cpu_model = "arm926";
1427
1428 env = cpu_init(cpu_model);
1429 if (!env) {
1430 fprintf(stderr, "Unable to find CPU definition\n");
1431 exit(1);
1432 }
1433 pic = arm_pic_init_cpu(env);
1434
1435 /* For now we use a fixed - the original - RAM size */
1436 cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1437 qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1438
1439 sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1440 cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1441
1442 /* Catch various stuff not handled by separate subsystems */
1443 iomemtype = cpu_register_io_memory(0, musicpal_readfn,
b0f6edb1 1444 musicpal_writefn, env);
24859b68
AZ		 1445 cpu_register_physical_memory(0x80000000, 0x10000, iomemtype);
1446
1447 pic = mv88w8618_pic_init(MP_PIC_BASE, pic[ARM_PIC_CPU_IRQ]);
1448 mv88w8618_pit_init(MP_PIT_BASE, pic, MP_TIMER1_IRQ);
1449
1450 if (serial_hds[0])
b6cd0ea1 1451 serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
24859b68
AZ		 1452 serial_hds[0], 1);
1453 if (serial_hds[1])
b6cd0ea1 1454 serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
24859b68
AZ		 1455 serial_hds[1], 1);
1456
1457 /* Register flash */
1458 index = drive_get_index(IF_PFLASH, 0, 0);
1459 if (index != -1) {
1460 flash_size = bdrv_getlength(drives_table[index].bdrv);
1461 if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1462 flash_size != 32*1024*1024) {
1463 fprintf(stderr, "Invalid flash image size\n");
1464 exit(1);
1465 }
1466
1467 /*
1468 * The original U-Boot accesses the flash at 0xFE000000 instead of
1469 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1470 * image is smaller than 32 MB.
1471 */
1472 pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1473 drives_table[index].bdrv, 0x10000,
1474 (flash_size + 0xffff) >> 16,
1475 MP_FLASH_SIZE_MAX / flash_size,
1476 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1477 0x5555, 0x2AAA);
1478 }
1479 mv88w8618_flashcfg_init(MP_FLASHCFG_BASE);
1480
1481 musicpal_lcd_init(ds, MP_LCD_BASE);
1482
1483 qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]);
1484
1485 /*
1486 * Wait a bit to catch menu button during U-Boot start-up
1487 * (to trigger emergency update).
1488 */
1489 sleep(1);
1490
1491 mv88w8618_eth_init(&nd_table[0], MP_ETH_BASE, pic[MP_ETH_IRQ]);
1492
1493 mixer_i2c = musicpal_audio_init(MP_AUDIO_BASE, pic[MP_AUDIO_IRQ]);
1494
1495 musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1496 musicpal_binfo.kernel_filename = kernel_filename;
1497 musicpal_binfo.kernel_cmdline = kernel_cmdline;
1498 musicpal_binfo.initrd_filename = initrd_filename;
b0f6edb1 1499 arm_load_kernel(env, &musicpal_binfo);
24859b68
AZ		 1500}
1501
1502QEMUMachine musicpal_machine = {
1503 "musicpal",
1504 "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1505 musicpal_init,
1506 MP_RAM_DEFAULT_SIZE + MP_SRAM_SIZE + MP_FLASH_SIZE_MAX + RAMSIZE_FIXED
1507};
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