]> Git Repo - qemu.git/blame - hw/char/debugcon.c
x86: Clean up includes
[qemu.git] / hw / char / debugcon.c
CommitLineData
c9f398e5
PA
1/*
2 * QEMU Bochs-style debug console ("port E9") emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2008 Citrix Systems, Inc.
6 * Copyright (c) Intel Corporation; author: H. Peter Anvin
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
b6a0aa05 27#include "qemu/osdep.h"
83c9f4ca 28#include "hw/hw.h"
dccfcd0e 29#include "sysemu/char.h"
0d09e41a
PB
30#include "hw/isa/isa.h"
31#include "hw/i386/pc.h"
c9f398e5 32
e8ba1ce9
GH
33#define TYPE_ISA_DEBUGCON_DEVICE "isa-debugcon"
34#define ISA_DEBUGCON_DEVICE(obj) \
35 OBJECT_CHECK(ISADebugconState, (obj), TYPE_ISA_DEBUGCON_DEVICE)
36
c9f398e5
PA
37//#define DEBUG_DEBUGCON
38
39typedef struct DebugconState {
e8ba1ce9 40 MemoryRegion io;
c9f398e5
PA
41 CharDriverState *chr;
42 uint32_t readback;
43} DebugconState;
44
45typedef struct ISADebugconState {
e8ba1ce9
GH
46 ISADevice parent_obj;
47
c9f398e5
PA
48 uint32_t iobase;
49 DebugconState state;
50} ISADebugconState;
51
e8ba1ce9
GH
52static void debugcon_ioport_write(void *opaque, hwaddr addr, uint64_t val,
53 unsigned width)
c9f398e5
PA
54{
55 DebugconState *s = opaque;
56 unsigned char ch = val;
57
58#ifdef DEBUG_DEBUGCON
668fca91 59 printf(" [debugcon: write addr=0x%04" HWADDR_PRIx " val=0x%02" PRIx64 "]\n", addr, val);
c9f398e5
PA
60#endif
61
2cc6e0a1 62 qemu_chr_fe_write(s->chr, &ch, 1);
c9f398e5
PA
63}
64
65
e8ba1ce9 66static uint64_t debugcon_ioport_read(void *opaque, hwaddr addr, unsigned width)
c9f398e5
PA
67{
68 DebugconState *s = opaque;
69
70#ifdef DEBUG_DEBUGCON
668fca91 71 printf("debugcon: read addr=0x%04" HWADDR_PRIx "\n", addr);
c9f398e5
PA
72#endif
73
74 return s->readback;
75}
76
e8ba1ce9
GH
77static const MemoryRegionOps debugcon_ops = {
78 .read = debugcon_ioport_read,
79 .write = debugcon_ioport_write,
80 .valid.min_access_size = 1,
81 .valid.max_access_size = 1,
82 .endianness = DEVICE_LITTLE_ENDIAN,
83};
84
db895a1e 85static void debugcon_realize_core(DebugconState *s, Error **errp)
c9f398e5
PA
86{
87 if (!s->chr) {
db895a1e
AF
88 error_setg(errp, "Can't create debugcon device, empty char device");
89 return;
c9f398e5
PA
90 }
91
92 qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, s);
93}
94
db895a1e 95static void debugcon_isa_realizefn(DeviceState *dev, Error **errp)
c9f398e5 96{
db895a1e 97 ISADevice *d = ISA_DEVICE(dev);
e8ba1ce9 98 ISADebugconState *isa = ISA_DEBUGCON_DEVICE(dev);
c9f398e5 99 DebugconState *s = &isa->state;
db895a1e 100 Error *err = NULL;
c9f398e5 101
db895a1e
AF
102 debugcon_realize_core(s, &err);
103 if (err != NULL) {
104 error_propagate(errp, err);
105 return;
106 }
300b1fc6 107 memory_region_init_io(&s->io, OBJECT(dev), &debugcon_ops, s,
e8ba1ce9 108 TYPE_ISA_DEBUGCON_DEVICE, 1);
db895a1e 109 memory_region_add_subregion(isa_address_space_io(d),
e8ba1ce9 110 isa->iobase, &s->io);
c9f398e5
PA
111}
112
39bffca2 113static Property debugcon_isa_properties[] = {
c7bcc85d 114 DEFINE_PROP_UINT32("iobase", ISADebugconState, iobase, 0xe9),
39bffca2 115 DEFINE_PROP_CHR("chardev", ISADebugconState, state.chr),
c7bcc85d 116 DEFINE_PROP_UINT32("readback", ISADebugconState, state.readback, 0xe9),
39bffca2
AL
117 DEFINE_PROP_END_OF_LIST(),
118};
119
8f04ee08
AL
120static void debugcon_isa_class_initfn(ObjectClass *klass, void *data)
121{
39bffca2 122 DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e
AF
123
124 dc->realize = debugcon_isa_realizefn;
39bffca2 125 dc->props = debugcon_isa_properties;
125ee0ed 126 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
8f04ee08
AL
127}
128
8c43a6f0 129static const TypeInfo debugcon_isa_info = {
e8ba1ce9 130 .name = TYPE_ISA_DEBUGCON_DEVICE,
39bffca2
AL
131 .parent = TYPE_ISA_DEVICE,
132 .instance_size = sizeof(ISADebugconState),
133 .class_init = debugcon_isa_class_initfn,
c9f398e5
PA
134};
135
83f7d43a 136static void debugcon_register_types(void)
c9f398e5 137{
39bffca2 138 type_register_static(&debugcon_isa_info);
c9f398e5
PA
139}
140
83f7d43a 141type_init(debugcon_register_types)
This page took 0.486548 seconds and 4 git commands to generate.