[qemu.git] / hw / display / vga-pci.c

/*
 * QEMU PCI VGA Emulator.
 *
 * see docs/specs/standard-vga.txt for virtual hardware specs.
 *
 * Copyright (c) 2003 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw/hw.h"
#include "ui/console.h"
#include "hw/pci/pci.h"
#include "vga_int.h"
#include "ui/pixel_ops.h"
#include "qemu/timer.h"
#include "hw/loader.h"

#define PCI_VGA_IOPORT_OFFSET 0x400
#define PCI_VGA_IOPORT_SIZE   (0x3e0 - 0x3c0)
#define PCI_VGA_BOCHS_OFFSET  0x500
#define PCI_VGA_BOCHS_SIZE    (0x0b * 2)
#define PCI_VGA_QEXT_OFFSET   0x600
#define PCI_VGA_QEXT_SIZE     (2 * 4)
#define PCI_VGA_MMIO_SIZE     0x1000

#define PCI_VGA_QEXT_REG_SIZE         (0 * 4)
#define PCI_VGA_QEXT_REG_BYTEORDER    (1 * 4)
#define  PCI_VGA_QEXT_LITTLE_ENDIAN   0x1e1e1e1e
#define  PCI_VGA_QEXT_BIG_ENDIAN      0xbebebebe

enum vga_pci_flags {
    PCI_VGA_FLAG_ENABLE_MMIO = 1,
    PCI_VGA_FLAG_ENABLE_QEXT = 2,
};

typedef struct PCIVGAState {
    PCIDevice dev;
    VGACommonState vga;
    uint32_t flags;
    MemoryRegion mmio;
    MemoryRegion ioport;
    MemoryRegion bochs;
    MemoryRegion qext;
} PCIVGAState;

static const VMStateDescription vmstate_vga_pci = {
    .name = "vga",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, PCIVGAState),
        VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
        VMSTATE_END_OF_LIST()
    }
};

static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
                                    unsigned size)
{
    PCIVGAState *d = ptr;
    uint64_t ret = 0;

    switch (size) {
    case 1:
        ret = vga_ioport_read(&d->vga, addr);
        break;
    case 2:
        ret  = vga_ioport_read(&d->vga, addr);
        ret |= vga_ioport_read(&d->vga, addr+1) << 8;
        break;
    }
    return ret;
}

static void pci_vga_ioport_write(void *ptr, hwaddr addr,
                                 uint64_t val, unsigned size)
{
    PCIVGAState *d = ptr;

    switch (size) {
    case 1:
        vga_ioport_write(&d->vga, addr + 0x3c0, val);
        break;
    case 2:
        /*
         * Update bytes in little endian order.  Allows to update
         * indexed registers with a single word write because the
         * index byte is updated first.
         */
        vga_ioport_write(&d->vga, addr + 0x3c0, val & 0xff);
        vga_ioport_write(&d->vga, addr + 0x3c1, (val >> 8) & 0xff);
        break;
    }
}

static const MemoryRegionOps pci_vga_ioport_ops = {
    .read = pci_vga_ioport_read,
    .write = pci_vga_ioport_write,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .impl.min_access_size = 1,
    .impl.max_access_size = 2,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
                                   unsigned size)
{
    PCIVGAState *d = ptr;
    int index = addr >> 1;

    vbe_ioport_write_index(&d->vga, 0, index);
    return vbe_ioport_read_data(&d->vga, 0);
}

static void pci_vga_bochs_write(void *ptr, hwaddr addr,
                                uint64_t val, unsigned size)
{
    PCIVGAState *d = ptr;
    int index = addr >> 1;

    vbe_ioport_write_index(&d->vga, 0, index);
    vbe_ioport_write_data(&d->vga, 0, val);
}

static const MemoryRegionOps pci_vga_bochs_ops = {
    .read = pci_vga_bochs_read,
    .write = pci_vga_bochs_write,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .impl.min_access_size = 2,
    .impl.max_access_size = 2,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
{
    PCIVGAState *d = ptr;

    switch (addr) {
    case PCI_VGA_QEXT_REG_SIZE:
        return PCI_VGA_QEXT_SIZE;
    case PCI_VGA_QEXT_REG_BYTEORDER:
        return d->vga.big_endian_fb ?
            PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
    default:
        return 0;
    }
}

static void pci_vga_qext_write(void *ptr, hwaddr addr,
                               uint64_t val, unsigned size)
{
    PCIVGAState *d = ptr;

    switch (addr) {
    case PCI_VGA_QEXT_REG_BYTEORDER:
        if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
            d->vga.big_endian_fb = true;
        }
        if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
            d->vga.big_endian_fb = false;
        }
        break;
    }
}

static const MemoryRegionOps pci_vga_qext_ops = {
    .read = pci_vga_qext_read,
    .write = pci_vga_qext_write,
    .valid.min_access_size = 4,
    .valid.max_access_size = 4,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static int pci_std_vga_initfn(PCIDevice *dev)
{
    PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
    VGACommonState *s = &d->vga;

    /* vga + console init */
    vga_common_init(s, OBJECT(dev), true);
    vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
             true);

    s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);

    /* XXX: VGA_RAM_SIZE must be a power of two */
    pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);

    /* mmio bar for vga register access */
    if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
        memory_region_init(&d->mmio, NULL, "vga.mmio", 4096);
        memory_region_init_io(&d->ioport, NULL, &pci_vga_ioport_ops, d,
                              "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
        memory_region_init_io(&d->bochs, NULL, &pci_vga_bochs_ops, d,
                              "bochs dispi interface", PCI_VGA_BOCHS_SIZE);

        memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,
                                    &d->ioport);
        memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,
                                    &d->bochs);

        if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
            memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d,
                                  "qemu extended regs", PCI_VGA_QEXT_SIZE);
            memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET,
                                        &d->qext);
            pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
        }

        pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
    }

    if (!dev->rom_bar) {
        /* compatibility with pc-0.13 and older */
        vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
    }

    return 0;
}

static int pci_secondary_vga_initfn(PCIDevice *dev)
{
    PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
    VGACommonState *s = &d->vga;

    /* vga + console init */
    vga_common_init(s, OBJECT(dev), false);
    s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);

    /* mmio bar */
    memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", 4096);
    memory_region_init_io(&d->ioport, OBJECT(dev), &pci_vga_ioport_ops, d,
                          "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
    memory_region_init_io(&d->bochs, OBJECT(dev), &pci_vga_bochs_ops, d,
                          "bochs dispi interface", PCI_VGA_BOCHS_SIZE);

    memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,
                                &d->ioport);
    memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,
                                &d->bochs);

    if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
        memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d,
                              "qemu extended regs", PCI_VGA_QEXT_SIZE);
        memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET,
                                    &d->qext);
        pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
    }

    pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
    pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);

    return 0;
}

static void pci_secondary_vga_reset(DeviceState *dev)
{
    PCIVGAState *d = DO_UPCAST(PCIVGAState, dev.qdev, dev);

    vga_common_reset(&d->vga);
}

static Property vga_pci_properties[] = {
    DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
    DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
    DEFINE_PROP_BIT("qemu-extended-regs",
                    PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
    DEFINE_PROP_END_OF_LIST(),
};

static Property secondary_pci_properties[] = {
    DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
    DEFINE_PROP_BIT("qemu-extended-regs",
                    PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
    DEFINE_PROP_END_OF_LIST(),
};

static void vga_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = pci_std_vga_initfn;
    k->romfile = "vgabios-stdvga.bin";
    k->vendor_id = PCI_VENDOR_ID_QEMU;
    k->device_id = PCI_DEVICE_ID_QEMU_VGA;
    k->class_id = PCI_CLASS_DISPLAY_VGA;
    dc->vmsd = &vmstate_vga_pci;
    dc->props = vga_pci_properties;
    dc->hotpluggable = false;
    set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
}

static void secondary_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = pci_secondary_vga_initfn;
    k->vendor_id = PCI_VENDOR_ID_QEMU;
    k->device_id = PCI_DEVICE_ID_QEMU_VGA;
    k->class_id = PCI_CLASS_DISPLAY_OTHER;
    dc->vmsd = &vmstate_vga_pci;
    dc->props = secondary_pci_properties;
    dc->reset = pci_secondary_vga_reset;
}

static const TypeInfo vga_info = {
    .name          = "VGA",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIVGAState),
    .class_init    = vga_class_init,
};

static const TypeInfo secondary_info = {
    .name          = "secondary-vga",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIVGAState),
    .class_init    = secondary_class_init,
};

static void vga_register_types(void)
{
    type_register_static(&vga_info);
    type_register_static(&secondary_info);
}

type_init(vga_register_types)
Commit	Line	Data
47d37dd9 JQ	1	/*
	2	* QEMU PCI VGA Emulator.
	3	*
cc228248 GH	4	* see docs/specs/standard-vga.txt for virtual hardware specs.
cc228248 GH	5	*
47d37dd9 JQ	6	* Copyright (c) 2003 Fabrice Bellard
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*/
83c9f4ca	26	#include "hw/hw.h"
28ecbaee	27	#include "ui/console.h"
83c9f4ca	28	#include "hw/pci/pci.h"
47b43a1f	29	#include "vga_int.h"
28ecbaee	30	#include "ui/pixel_ops.h"
1de7afc9	31	#include "qemu/timer.h"
83c9f4ca	32	#include "hw/loader.h"
47d37dd9	33
803ff052 GH	34	#define PCI_VGA_IOPORT_OFFSET 0x400
	35	#define PCI_VGA_IOPORT_SIZE (0x3e0 - 0x3c0)
	36	#define PCI_VGA_BOCHS_OFFSET 0x500
	37	#define PCI_VGA_BOCHS_SIZE (0x0b * 2)
b5682aa4 GH	38	#define PCI_VGA_QEXT_OFFSET 0x600
b5682aa4 GH	39	#define PCI_VGA_QEXT_SIZE (2 * 4)
803ff052 GH	40	#define PCI_VGA_MMIO_SIZE 0x1000
803ff052 GH	41
b5682aa4 GH	42	#define PCI_VGA_QEXT_REG_SIZE (0 * 4)
	43	#define PCI_VGA_QEXT_REG_BYTEORDER (1 * 4)
	44	#define PCI_VGA_QEXT_LITTLE_ENDIAN 0x1e1e1e1e
	45	#define PCI_VGA_QEXT_BIG_ENDIAN 0xbebebebe
	46
803ff052 GH	47	enum vga_pci_flags {
803ff052 GH	48	PCI_VGA_FLAG_ENABLE_MMIO = 1,
b5682aa4	49	PCI_VGA_FLAG_ENABLE_QEXT = 2,
803ff052 GH	50	};
803ff052 GH	51
47d37dd9 JQ	52	typedef struct PCIVGAState {
	53	PCIDevice dev;
	54	VGACommonState vga;
803ff052 GH	55	uint32_t flags;
	56	MemoryRegion mmio;
	57	MemoryRegion ioport;
	58	MemoryRegion bochs;
b5682aa4	59	MemoryRegion qext;
47d37dd9 JQ	60	} PCIVGAState;
47d37dd9 JQ	61
a4f9631c JQ	62	static const VMStateDescription vmstate_vga_pci = {
	63	.name = "vga",
	64	.version_id = 2,
	65	.minimum_version_id = 2,
d49805ae	66	.fields = (VMStateField[]) {
a4f9631c JQ	67	VMSTATE_PCI_DEVICE(dev, PCIVGAState),
	68	VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
	69	VMSTATE_END_OF_LIST()
47d37dd9	70	}
a4f9631c	71	};
47d37dd9	72
a8170e5e	73	static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
803ff052 GH	74	unsigned size)
	75	{
	76	PCIVGAState *d = ptr;
	77	uint64_t ret = 0;
	78
	79	switch (size) {
	80	case 1:
	81	ret = vga_ioport_read(&d->vga, addr);
	82	break;
	83	case 2:
	84	ret = vga_ioport_read(&d->vga, addr);
	85	ret \|= vga_ioport_read(&d->vga, addr+1) << 8;
	86	break;
	87	}
	88	return ret;
	89	}
	90
a8170e5e	91	static void pci_vga_ioport_write(void *ptr, hwaddr addr,
803ff052 GH	92	uint64_t val, unsigned size)
	93	{
	94	PCIVGAState *d = ptr;
c96c53b5	95
803ff052 GH	96	switch (size) {
803ff052 GH	97	case 1:
c96c53b5	98	vga_ioport_write(&d->vga, addr + 0x3c0, val);
803ff052 GH	99	break;
	100	case 2:
	101	/*
	102	* Update bytes in little endian order. Allows to update
	103	* indexed registers with a single word write because the
	104	* index byte is updated first.
	105	*/
c96c53b5 GH	106	vga_ioport_write(&d->vga, addr + 0x3c0, val & 0xff);
c96c53b5 GH	107	vga_ioport_write(&d->vga, addr + 0x3c1, (val >> 8) & 0xff);
803ff052 GH	108	break;
	109	}
	110	}
	111
	112	static const MemoryRegionOps pci_vga_ioport_ops = {
	113	.read = pci_vga_ioport_read,
	114	.write = pci_vga_ioport_write,
	115	.valid.min_access_size = 1,
	116	.valid.max_access_size = 4,
	117	.impl.min_access_size = 1,
	118	.impl.max_access_size = 2,
	119	.endianness = DEVICE_LITTLE_ENDIAN,
	120	};
	121
a8170e5e	122	static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
803ff052 GH	123	unsigned size)
	124	{
	125	PCIVGAState *d = ptr;
	126	int index = addr >> 1;
	127
	128	vbe_ioport_write_index(&d->vga, 0, index);
	129	return vbe_ioport_read_data(&d->vga, 0);
	130	}
	131
a8170e5e	132	static void pci_vga_bochs_write(void *ptr, hwaddr addr,
803ff052 GH	133	uint64_t val, unsigned size)
	134	{
	135	PCIVGAState *d = ptr;
	136	int index = addr >> 1;
	137
	138	vbe_ioport_write_index(&d->vga, 0, index);
	139	vbe_ioport_write_data(&d->vga, 0, val);
	140	}
	141
	142	static const MemoryRegionOps pci_vga_bochs_ops = {
	143	.read = pci_vga_bochs_read,
	144	.write = pci_vga_bochs_write,
	145	.valid.min_access_size = 1,
	146	.valid.max_access_size = 4,
	147	.impl.min_access_size = 2,
	148	.impl.max_access_size = 2,
	149	.endianness = DEVICE_LITTLE_ENDIAN,
	150	};
	151
b5682aa4 GH	152	static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
	153	{
	154	PCIVGAState *d = ptr;
	155
	156	switch (addr) {
	157	case PCI_VGA_QEXT_REG_SIZE:
	158	return PCI_VGA_QEXT_SIZE;
	159	case PCI_VGA_QEXT_REG_BYTEORDER:
	160	return d->vga.big_endian_fb ?
	161	PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
	162	default:
	163	return 0;
	164	}
	165	}
	166
	167	static void pci_vga_qext_write(void *ptr, hwaddr addr,
	168	uint64_t val, unsigned size)
	169	{
	170	PCIVGAState *d = ptr;
	171
	172	switch (addr) {
	173	case PCI_VGA_QEXT_REG_BYTEORDER:
	174	if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
	175	d->vga.big_endian_fb = true;
	176	}
	177	if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
	178	d->vga.big_endian_fb = false;
	179	}
	180	break;
	181	}
	182	}
	183
	184	static const MemoryRegionOps pci_vga_qext_ops = {
	185	.read = pci_vga_qext_read,
	186	.write = pci_vga_qext_write,
	187	.valid.min_access_size = 4,
	188	.valid.max_access_size = 4,
	189	.endianness = DEVICE_LITTLE_ENDIAN,
	190	};
	191
a1e47211	192	static int pci_std_vga_initfn(PCIDevice *dev)
47d37dd9	193	{
0d0302e2 GH	194	PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
0d0302e2 GH	195	VGACommonState *s = &d->vga;
47d37dd9	196
0d0302e2	197	/* vga + console init */
e2bbfc8e	198	vga_common_init(s, OBJECT(dev), true);
712f0cc7 PB	199	vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
712f0cc7 PB	200	true);
47d37dd9	201
5643706a	202	s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
47d37dd9	203
0d0302e2 GH	204	/* XXX: VGA_RAM_SIZE must be a power of two */
0d0302e2 GH	205	pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
47d37dd9	206
803ff052 GH	207	/* mmio bar for vga register access */
803ff052 GH	208	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
2c9b15ca PB	209	memory_region_init(&d->mmio, NULL, "vga.mmio", 4096);
2c9b15ca PB	210	memory_region_init_io(&d->ioport, NULL, &pci_vga_ioport_ops, d,
803ff052	211	"vga ioports remapped", PCI_VGA_IOPORT_SIZE);
2c9b15ca	212	memory_region_init_io(&d->bochs, NULL, &pci_vga_bochs_ops, d,
803ff052 GH	213	"bochs dispi interface", PCI_VGA_BOCHS_SIZE);
	214
	215	memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,
	216	&d->ioport);
	217	memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,
	218	&d->bochs);
b5682aa4 GH	219
	220	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
	221	memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d,
	222	"qemu extended regs", PCI_VGA_QEXT_SIZE);
	223	memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET,
	224	&d->qext);
	225	pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
	226	}
	227
803ff052 GH	228	pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
	229	}
	230
0d0302e2 GH	231	if (!dev->rom_bar) {
0d0302e2 GH	232	/* compatibility with pc-0.13 and older */
83118327	233	vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
0d0302e2	234	}
281a26b1	235
0d0302e2	236	return 0;
47d37dd9 JQ	237	}
47d37dd9 JQ	238
63e3e24d GH	239	static int pci_secondary_vga_initfn(PCIDevice *dev)
	240	{
	241	PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
	242	VGACommonState *s = &d->vga;
	243
	244	/* vga + console init */
	245	vga_common_init(s, OBJECT(dev), false);
	246	s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
	247
	248	/* mmio bar */
	249	memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", 4096);
	250	memory_region_init_io(&d->ioport, OBJECT(dev), &pci_vga_ioport_ops, d,
	251	"vga ioports remapped", PCI_VGA_IOPORT_SIZE);
	252	memory_region_init_io(&d->bochs, OBJECT(dev), &pci_vga_bochs_ops, d,
	253	"bochs dispi interface", PCI_VGA_BOCHS_SIZE);
	254
	255	memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,
	256	&d->ioport);
	257	memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,
	258	&d->bochs);
	259
b5682aa4 GH	260	if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
	261	memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d,
	262	"qemu extended regs", PCI_VGA_QEXT_SIZE);
	263	memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET,
	264	&d->qext);
	265	pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
	266	}
	267
63e3e24d GH	268	pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
	269	pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
	270
	271	return 0;
	272	}
	273
	274	static void pci_secondary_vga_reset(DeviceState *dev)
	275	{
	276	PCIVGAState *d = DO_UPCAST(PCIVGAState, dev.qdev, dev);
	277
	278	vga_common_reset(&d->vga);
	279	}
	280
4a1e244e	281	static Property vga_pci_properties[] = {
9e56edcf	282	DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
803ff052	283	DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
b5682aa4 GH	284	DEFINE_PROP_BIT("qemu-extended-regs",
b5682aa4 GH	285	PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
4a1e244e GH	286	DEFINE_PROP_END_OF_LIST(),
	287	};
	288
63e3e24d GH	289	static Property secondary_pci_properties[] = {
63e3e24d GH	290	DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
b5682aa4 GH	291	DEFINE_PROP_BIT("qemu-extended-regs",
b5682aa4 GH	292	PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
63e3e24d GH	293	DEFINE_PROP_END_OF_LIST(),
	294	};
	295
40021f08 AL	296	static void vga_class_init(ObjectClass klass, void data)
40021f08 AL	297	{
39bffca2	298	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	299	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
40021f08 AL	300
a1e47211	301	k->init = pci_std_vga_initfn;
40021f08 AL	302	k->romfile = "vgabios-stdvga.bin";
	303	k->vendor_id = PCI_VENDOR_ID_QEMU;
	304	k->device_id = PCI_DEVICE_ID_QEMU_VGA;
	305	k->class_id = PCI_CLASS_DISPLAY_VGA;
39bffca2	306	dc->vmsd = &vmstate_vga_pci;
4a1e244e	307	dc->props = vga_pci_properties;
2897ae02	308	dc->hotpluggable = false;
125ee0ed	309	set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
40021f08	310	}
32902772	311
63e3e24d GH	312	static void secondary_class_init(ObjectClass klass, void data)
	313	{
	314	DeviceClass *dc = DEVICE_CLASS(klass);
	315	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	316
	317	k->init = pci_secondary_vga_initfn;
	318	k->vendor_id = PCI_VENDOR_ID_QEMU;
	319	k->device_id = PCI_DEVICE_ID_QEMU_VGA;
	320	k->class_id = PCI_CLASS_DISPLAY_OTHER;
	321	dc->vmsd = &vmstate_vga_pci;
	322	dc->props = secondary_pci_properties;
	323	dc->reset = pci_secondary_vga_reset;
	324	}
	325
8c43a6f0	326	static const TypeInfo vga_info = {
39bffca2 AL	327	.name = "VGA",
	328	.parent = TYPE_PCI_DEVICE,
	329	.instance_size = sizeof(PCIVGAState),
	330	.class_init = vga_class_init,
47d37dd9 JQ	331	};
47d37dd9 JQ	332
63e3e24d GH	333	static const TypeInfo secondary_info = {
	334	.name = "secondary-vga",
	335	.parent = TYPE_PCI_DEVICE,
	336	.instance_size = sizeof(PCIVGAState),
	337	.class_init = secondary_class_init,
	338	};
	339
83f7d43a	340	static void vga_register_types(void)
47d37dd9	341	{
39bffca2	342	type_register_static(&vga_info);
63e3e24d	343	type_register_static(&secondary_info);
47d37dd9	344	}
83f7d43a AF	345
83f7d43a AF	346	type_init(vga_register_types)