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ab7ab3d7 AF |
1 | /* |
2 | * QEMU SPARC CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see | |
18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
19 | */ | |
20 | #ifndef QEMU_SPARC_CPU_QOM_H | |
21 | #define QEMU_SPARC_CPU_QOM_H | |
22 | ||
14cccb61 | 23 | #include "qom/cpu.h" |
ab7ab3d7 AF |
24 | #include "cpu.h" |
25 | ||
26 | #ifdef TARGET_SPARC64 | |
27 | #define TYPE_SPARC_CPU "sparc64-cpu" | |
28 | #else | |
29 | #define TYPE_SPARC_CPU "sparc-cpu" | |
30 | #endif | |
31 | ||
32 | #define SPARC_CPU_CLASS(klass) \ | |
33 | OBJECT_CLASS_CHECK(SPARCCPUClass, (klass), TYPE_SPARC_CPU) | |
34 | #define SPARC_CPU(obj) \ | |
35 | OBJECT_CHECK(SPARCCPU, (obj), TYPE_SPARC_CPU) | |
36 | #define SPARC_CPU_GET_CLASS(obj) \ | |
37 | OBJECT_GET_CLASS(SPARCCPUClass, (obj), TYPE_SPARC_CPU) | |
38 | ||
39 | /** | |
40 | * SPARCCPUClass: | |
b6e91ebf | 41 | * @parent_realize: The parent class' realize handler. |
ab7ab3d7 AF |
42 | * @parent_reset: The parent class' reset handler. |
43 | * | |
44 | * A SPARC CPU model. | |
45 | */ | |
46 | typedef struct SPARCCPUClass { | |
47 | /*< private >*/ | |
48 | CPUClass parent_class; | |
49 | /*< public >*/ | |
50 | ||
b6e91ebf | 51 | DeviceRealize parent_realize; |
ab7ab3d7 AF |
52 | void (*parent_reset)(CPUState *cpu); |
53 | } SPARCCPUClass; | |
54 | ||
55 | /** | |
56 | * SPARCCPU: | |
57 | * @env: #CPUSPARCState | |
58 | * | |
59 | * A SPARC CPU. | |
60 | */ | |
61 | typedef struct SPARCCPU { | |
62 | /*< private >*/ | |
63 | CPUState parent_obj; | |
64 | /*< public >*/ | |
65 | ||
66 | CPUSPARCState env; | |
67 | } SPARCCPU; | |
68 | ||
69 | static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env) | |
70 | { | |
6e42be7c | 71 | return container_of(env, SPARCCPU, env); |
ab7ab3d7 AF |
72 | } |
73 | ||
74 | #define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e)) | |
75 | ||
fadf9825 | 76 | #define ENV_OFFSET offsetof(SPARCCPU, env) |
ab7ab3d7 | 77 | |
97a8ea5a | 78 | void sparc_cpu_do_interrupt(CPUState *cpu); |
878096ee AF |
79 | void sparc_cpu_dump_state(CPUState *cpu, FILE *f, |
80 | fprintf_function cpu_fprintf, int flags); | |
00b941e5 | 81 | hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
5b50e790 AF |
82 | int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); |
83 | int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
93e22326 PB |
84 | void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, |
85 | vaddr addr, int is_write, | |
86 | int is_user, uintptr_t retaddr); | |
97a8ea5a | 87 | |
ab7ab3d7 | 88 | #endif |