[qemu.git] / include / hw / i386 / ich9.h

#ifndef HW_ICH9_H
#define HW_ICH9_H

#include "hw/hw.h"
#include "hw/isa/isa.h"
#include "hw/sysbus.h"
#include "hw/i386/pc.h"
#include "hw/isa/apm.h"
#include "hw/i386/ioapic.h"
#include "hw/pci/pci.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci/pci_bridge.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/ich9.h"
#include "hw/pci/pci_bus.h"

void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);

void ich9_generate_smi(void);

#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */

#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
#define ICH9_LPC_DEVICE(obj) \
     OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)

typedef struct ICH9LPCState {
    /* ICH9 LPC PCI to ISA bridge */
    PCIDevice d;

    /* (pci device, intx) -> pirq
     * In real chipset case, the unused slots are never used
     * as ICH9 supports only D25-D31 irq routing.
     * On the other hand in qemu case, any slot/function can be populated
     * via command line option.
     * So fallback interrupt routing for any devices in any slots is necessary.
    */
    uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];

    APMState apm;
    ICH9LPCPMRegs pm;
    uint32_t sci_level; /* track sci level */
    uint8_t sci_gsi;

    /* 2.24 Pin Straps */
    struct {
        bool spkr_hi;
    } pin_strap;

    /* 10.1 Chipset Configuration registers(Memory Space)
     which is pointed by RCBA */
    uint8_t chip_config[ICH9_CC_SIZE];

    /*
     * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
     *
     * register contents and IO memory region
     */
    uint8_t rst_cnt;
    MemoryRegion rst_cnt_mem;

    /* SMI feature negotiation via fw_cfg */
    uint64_t smi_host_features;       /* guest-invisible, host endian */
    uint8_t smi_host_features_le[8];  /* guest-visible, read-only, little
                                       * endian uint64_t */
    uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little
                                       * endian uint64_t */
    uint8_t smi_features_ok;          /* guest-visible, read-only; selecting it
                                       * triggers feature lockdown */
    uint64_t smi_negotiated_features; /* guest-invisible, host endian */

    /* isa bus */
    ISABus *isa_bus;
    MemoryRegion rcrb_mem; /* root complex register block */
    Notifier machine_ready;

    qemu_irq gsi[GSI_NUM_PINS];
} ICH9LPCState;

Object *ich9_lpc_find(void);

#define Q35_MASK(bit, ms_bit, ls_bit) \
((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))

/* ICH9: Chipset Configuration Registers */
#define ICH9_CC_ADDR_MASK                       (ICH9_CC_SIZE - 1)

#define ICH9_CC
#define ICH9_CC_D28IP                           0x310C
#define ICH9_CC_D28IP_SHIFT                     4
#define ICH9_CC_D28IP_MASK                      0xf
#define ICH9_CC_D28IP_DEFAULT                   0x00214321
#define ICH9_CC_D31IR                           0x3140
#define ICH9_CC_D30IR                           0x3142
#define ICH9_CC_D29IR                           0x3144
#define ICH9_CC_D28IR                           0x3146
#define ICH9_CC_D27IR                           0x3148
#define ICH9_CC_D26IR                           0x314C
#define ICH9_CC_D25IR                           0x3150
#define ICH9_CC_DIR_DEFAULT                     0x3210
#define ICH9_CC_D30IR_DEFAULT                   0x0
#define ICH9_CC_DIR_SHIFT                       4
#define ICH9_CC_DIR_MASK                        0x7
#define ICH9_CC_OIC                             0x31FF
#define ICH9_CC_OIC_AEN                         0x1
#define ICH9_CC_GCS                             0x3410
#define ICH9_CC_GCS_DEFAULT                     0x00000020
#define ICH9_CC_GCS_NO_REBOOT                   (1 << 5)

/* D28:F[0-5] */
#define ICH9_PCIE_DEV                           28
#define ICH9_PCIE_FUNC_MAX                      6


/* D29:F0 USB UHCI Controller #1 */
#define ICH9_USB_UHCI1_DEV                      29
#define ICH9_USB_UHCI1_FUNC                     0

/* D30:F0 DMI-to-PCI bridge */
#define ICH9_D2P_BRIDGE                         "ICH9 D2P BRIDGE"
#define ICH9_D2P_BRIDGE_SAVEVM_VERSION          0

#define ICH9_D2P_BRIDGE_DEV                     30
#define ICH9_D2P_BRIDGE_FUNC                    0

#define ICH9_D2P_SECONDARY_DEFAULT              (256 - 8)

#define ICH9_D2P_A2_REVISION                    0x92

/* D31:F0 LPC Processor Interface */
#define ICH9_RST_CNT_IOPORT                     0xCF9

/* D31:F1 LPC controller */
#define ICH9_A2_LPC                             "ICH9 A2 LPC"
#define ICH9_A2_LPC_SAVEVM_VERSION              0

#define ICH9_LPC_DEV                            31
#define ICH9_LPC_FUNC                           0

#define ICH9_A2_LPC_REVISION                    0x2
#define ICH9_LPC_NB_PIRQS                       8       /* PCI A-H */

#define ICH9_LPC_PMBASE                         0x40
#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK       Q35_MASK(32, 15, 7)
#define ICH9_LPC_PMBASE_RTE                     0x1
#define ICH9_LPC_PMBASE_DEFAULT                 0x1
#define ICH9_LPC_ACPI_CTRL                      0x44
#define ICH9_LPC_ACPI_CTRL_ACPI_EN              0x80
#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK     Q35_MASK(8, 2, 0)
#define ICH9_LPC_ACPI_CTRL_9                    0x0
#define ICH9_LPC_ACPI_CTRL_10                   0x1
#define ICH9_LPC_ACPI_CTRL_11                   0x2
#define ICH9_LPC_ACPI_CTRL_20                   0x4
#define ICH9_LPC_ACPI_CTRL_21                   0x5
#define ICH9_LPC_ACPI_CTRL_DEFAULT              0x0

#define ICH9_LPC_PIRQA_ROUT                     0x60
#define ICH9_LPC_PIRQB_ROUT                     0x61
#define ICH9_LPC_PIRQC_ROUT                     0x62
#define ICH9_LPC_PIRQD_ROUT                     0x63

#define ICH9_LPC_PIRQE_ROUT                     0x68
#define ICH9_LPC_PIRQF_ROUT                     0x69
#define ICH9_LPC_PIRQG_ROUT                     0x6a
#define ICH9_LPC_PIRQH_ROUT                     0x6b

#define ICH9_LPC_PIRQ_ROUT_IRQEN                0x80
#define ICH9_LPC_PIRQ_ROUT_MASK                 Q35_MASK(8, 3, 0)
#define ICH9_LPC_PIRQ_ROUT_DEFAULT              0x80

#define ICH9_LPC_GEN_PMCON_1                    0xa0
#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK           (1 << 4)
#define ICH9_LPC_GEN_PMCON_2                    0xa2
#define ICH9_LPC_GEN_PMCON_3                    0xa4
#define ICH9_LPC_GEN_PMCON_LOCK                 0xa6

#define ICH9_LPC_RCBA                           0xf0
#define ICH9_LPC_RCBA_BA_MASK                   Q35_MASK(32, 31, 14)
#define ICH9_LPC_RCBA_EN                        0x1
#define ICH9_LPC_RCBA_DEFAULT                   0x0

#define ICH9_LPC_PIC_NUM_PINS                   16
#define ICH9_LPC_IOAPIC_NUM_PINS                24

#define ICH9_GPIO_GSI "gsi"

/* D31:F2 SATA Controller #1 */
#define ICH9_SATA1_DEV                          31
#define ICH9_SATA1_FUNC                         2

/* D31:F0 power management I/O registers
   offset from the address ICH9_LPC_PMBASE */

/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
#define ICH9_PMIO_SIZE                          128
#define ICH9_PMIO_MASK                          (ICH9_PMIO_SIZE - 1)

#define ICH9_PMIO_PM1_STS                       0x00
#define ICH9_PMIO_PM1_EN                        0x02
#define ICH9_PMIO_PM1_CNT                       0x04
#define ICH9_PMIO_PM1_TMR                       0x08
#define ICH9_PMIO_GPE0_STS                      0x20
#define ICH9_PMIO_GPE0_EN                       0x28
#define ICH9_PMIO_GPE0_LEN                      16
#define ICH9_PMIO_SMI_EN                        0x30
#define ICH9_PMIO_SMI_EN_APMC_EN                (1 << 5)
#define ICH9_PMIO_SMI_EN_TCO_EN                 (1 << 13)
#define ICH9_PMIO_SMI_STS                       0x34
#define ICH9_PMIO_TCO_RLD                       0x60
#define ICH9_PMIO_TCO_LEN                       32

/* FADT ACPI_ENABLE/ACPI_DISABLE */
#define ICH9_APM_ACPI_ENABLE                    0x2
#define ICH9_APM_ACPI_DISABLE                   0x3


/* D31:F3 SMBus controller */
#define TYPE_ICH9_SMB_DEVICE "ICH9 SMB"

#define ICH9_A2_SMB_REVISION                    0x02
#define ICH9_SMB_PI                             0x00

#define ICH9_SMB_SMBMBAR0                       0x10
#define ICH9_SMB_SMBMBAR1                       0x14
#define ICH9_SMB_SMBM_BAR                       0
#define ICH9_SMB_SMBM_SIZE                      (1 << 8)
#define ICH9_SMB_SMB_BASE                       0x20
#define ICH9_SMB_SMB_BASE_BAR                   4
#define ICH9_SMB_SMB_BASE_SIZE                  (1 << 5)
#define ICH9_SMB_HOSTC                          0x40
#define ICH9_SMB_HOSTC_SSRESET                  ((uint8_t)(1 << 3))
#define ICH9_SMB_HOSTC_I2C_EN                   ((uint8_t)(1 << 2))
#define ICH9_SMB_HOSTC_SMB_SMI_EN               ((uint8_t)(1 << 1))
#define ICH9_SMB_HOSTC_HST_EN                   ((uint8_t)(1 << 0))

/* D31:F3 SMBus I/O and memory mapped I/O registers */
#define ICH9_SMB_DEV                            31
#define ICH9_SMB_FUNC                           3

#define ICH9_SMB_HST_STS                        0x00
#define ICH9_SMB_HST_CNT                        0x02
#define ICH9_SMB_HST_CMD                        0x03
#define ICH9_SMB_XMIT_SLVA                      0x04
#define ICH9_SMB_HST_D0                         0x05
#define ICH9_SMB_HST_D1                         0x06
#define ICH9_SMB_HOST_BLOCK_DB                  0x07

/* bit positions used in fw_cfg SMI feature negotiation */
#define ICH9_LPC_SMI_F_BROADCAST_BIT            0

#endif /* HW_ICH9_H */
Commit	Line	Data
e516572f JB	1	#ifndef HW_ICH9_H
	2	#define HW_ICH9_H
	3
83c9f4ca	4	#include "hw/hw.h"
0d09e41a	5	#include "hw/isa/isa.h"
83c9f4ca	6	#include "hw/sysbus.h"
0d09e41a PB	7	#include "hw/i386/pc.h"
	8	#include "hw/isa/apm.h"
	9	#include "hw/i386/ioapic.h"
83c9f4ca PB	10	#include "hw/pci/pci.h"
	11	#include "hw/pci/pcie_host.h"
	12	#include "hw/pci/pci_bridge.h"
0d09e41a PB	13	#include "hw/acpi/acpi.h"
0d09e41a PB	14	#include "hw/acpi/ich9.h"
83c9f4ca	15	#include "hw/pci/pci_bus.h"
e516572f JB	16
	17	void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
	18	int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
91c3f2f0	19	PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
18d6abae	20	void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
a5c82852	21	I2CBus ich9_smb_init(PCIBus bus, int devfn, uint32_t smb_io_base);
e516572f	22
92055797	23	void ich9_generate_smi(void);
92055797	24
7335a95a	25	#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */
e516572f	26
292b1634	27	#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
e516572f JB	28	#define ICH9_LPC_DEVICE(obj) \
	29	OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)
	30
	31	typedef struct ICH9LPCState {
	32	/* ICH9 LPC PCI to ISA bridge */
	33	PCIDevice d;
	34
	35	/* (pci device, intx) -> pirq
	36	* In real chipset case, the unused slots are never used
0668a06b	37	* as ICH9 supports only D25-D31 irq routing.
e516572f JB	38	* On the other hand in qemu case, any slot/function can be populated
	39	* via command line option.
	40	* So fallback interrupt routing for any devices in any slots is necessary.
	41	*/
	42	uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
	43
	44	APMState apm;
	45	ICH9LPCPMRegs pm;
	46	uint32_t sci_level; /* track sci level */
8f242cb7	47	uint8_t sci_gsi;
e516572f	48
5add35be PA	49	/* 2.24 Pin Straps */
	50	struct {
	51	bool spkr_hi;
	52	} pin_strap;
	53
e516572f JB	54	/* 10.1 Chipset Configuration registers(Memory Space)
	55	which is pointed by RCBA */
	56	uint8_t chip_config[ICH9_CC_SIZE];
0e98b436 LE	57
	58	/*
	59	* 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
	60	*
	61	* register contents and IO memory region
	62	*/
	63	uint8_t rst_cnt;
	64	MemoryRegion rst_cnt_mem;
	65
50de920b LE	66	/* SMI feature negotiation via fw_cfg */
	67	uint64_t smi_host_features; /* guest-invisible, host endian */
	68	uint8_t smi_host_features_le[8]; /* guest-visible, read-only, little
	69	* endian uint64_t */
	70	uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little
	71	* endian uint64_t */
	72	uint8_t smi_features_ok; /* guest-visible, read-only; selecting it
	73	* triggers feature lockdown */
	74	uint64_t smi_negotiated_features; /* guest-invisible, host endian */
	75
e516572f JB	76	/* isa bus */
e516572f JB	77	ISABus *isa_bus;
7335a95a	78	MemoryRegion rcrb_mem; /* root complex register block */
3f5bc9e8	79	Notifier machine_ready;
e516572f	80
f999c0de	81	qemu_irq gsi[GSI_NUM_PINS];
e516572f JB	82	} ICH9LPCState;
e516572f JB	83
6f1426ab MT	84	Object *ich9_lpc_find(void);
6f1426ab MT	85
e516572f JB	86	#define Q35_MASK(bit, ms_bit, ls_bit) \
	87	((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
	88
	89	/* ICH9: Chipset Configuration Registers */
	90	#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
	91
	92	#define ICH9_CC
	93	#define ICH9_CC_D28IP 0x310C
	94	#define ICH9_CC_D28IP_SHIFT 4
	95	#define ICH9_CC_D28IP_MASK 0xf
	96	#define ICH9_CC_D28IP_DEFAULT 0x00214321
	97	#define ICH9_CC_D31IR 0x3140
	98	#define ICH9_CC_D30IR 0x3142
	99	#define ICH9_CC_D29IR 0x3144
	100	#define ICH9_CC_D28IR 0x3146
	101	#define ICH9_CC_D27IR 0x3148
	102	#define ICH9_CC_D26IR 0x314C
	103	#define ICH9_CC_D25IR 0x3150
	104	#define ICH9_CC_DIR_DEFAULT 0x3210
	105	#define ICH9_CC_D30IR_DEFAULT 0x0
	106	#define ICH9_CC_DIR_SHIFT 4
	107	#define ICH9_CC_DIR_MASK 0x7
	108	#define ICH9_CC_OIC 0x31FF
	109	#define ICH9_CC_OIC_AEN 0x1
92055797 PA	110	#define ICH9_CC_GCS 0x3410
	111	#define ICH9_CC_GCS_DEFAULT 0x00000020
	112	#define ICH9_CC_GCS_NO_REBOOT (1 << 5)
e516572f JB	113
	114	/* D28:F[0-5] */
	115	#define ICH9_PCIE_DEV 28
	116	#define ICH9_PCIE_FUNC_MAX 6
	117
	118
	119	/* D29:F0 USB UHCI Controller #1 */
	120	#define ICH9_USB_UHCI1_DEV 29
	121	#define ICH9_USB_UHCI1_FUNC 0
	122
263cf436	123	/* D30:F0 DMI-to-PCI bridge */
e516572f JB	124	#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
	125	#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
	126
	127	#define ICH9_D2P_BRIDGE_DEV 30
	128	#define ICH9_D2P_BRIDGE_FUNC 0
	129
	130	#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8)
	131
	132	#define ICH9_D2P_A2_REVISION 0x92
	133
0e98b436 LE	134	/* D31:F0 LPC Processor Interface */
0e98b436 LE	135	#define ICH9_RST_CNT_IOPORT 0xCF9
e516572f JB	136
	137	/* D31:F1 LPC controller */
	138	#define ICH9_A2_LPC "ICH9 A2 LPC"
	139	#define ICH9_A2_LPC_SAVEVM_VERSION 0
	140
	141	#define ICH9_LPC_DEV 31
	142	#define ICH9_LPC_FUNC 0
	143
	144	#define ICH9_A2_LPC_REVISION 0x2
	145	#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
	146
	147	#define ICH9_LPC_PMBASE 0x40
	148	#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
	149	#define ICH9_LPC_PMBASE_RTE 0x1
	150	#define ICH9_LPC_PMBASE_DEFAULT 0x1
	151	#define ICH9_LPC_ACPI_CTRL 0x44
	152	#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
	153	#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
	154	#define ICH9_LPC_ACPI_CTRL_9 0x0
	155	#define ICH9_LPC_ACPI_CTRL_10 0x1
	156	#define ICH9_LPC_ACPI_CTRL_11 0x2
	157	#define ICH9_LPC_ACPI_CTRL_20 0x4
	158	#define ICH9_LPC_ACPI_CTRL_21 0x5
	159	#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
	160
	161	#define ICH9_LPC_PIRQA_ROUT 0x60
	162	#define ICH9_LPC_PIRQB_ROUT 0x61
	163	#define ICH9_LPC_PIRQC_ROUT 0x62
	164	#define ICH9_LPC_PIRQD_ROUT 0x63
	165
	166	#define ICH9_LPC_PIRQE_ROUT 0x68
	167	#define ICH9_LPC_PIRQF_ROUT 0x69
	168	#define ICH9_LPC_PIRQG_ROUT 0x6a
	169	#define ICH9_LPC_PIRQH_ROUT 0x6b
	170
	171	#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
	172	#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
	173	#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
	174
11e66a15 GH	175	#define ICH9_LPC_GEN_PMCON_1 0xa0
	176	#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4)
	177	#define ICH9_LPC_GEN_PMCON_2 0xa2
	178	#define ICH9_LPC_GEN_PMCON_3 0xa4
	179	#define ICH9_LPC_GEN_PMCON_LOCK 0xa6
	180
e516572f JB	181	#define ICH9_LPC_RCBA 0xf0
	182	#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
	183	#define ICH9_LPC_RCBA_EN 0x1
	184	#define ICH9_LPC_RCBA_DEFAULT 0x0
	185
	186	#define ICH9_LPC_PIC_NUM_PINS 16
	187	#define ICH9_LPC_IOAPIC_NUM_PINS 24
	188
f999c0de EV	189	#define ICH9_GPIO_GSI "gsi"
f999c0de EV	190
e516572f JB	191	/* D31:F2 SATA Controller #1 */
	192	#define ICH9_SATA1_DEV 31
	193	#define ICH9_SATA1_FUNC 2
	194
0668a06b	195	/* D31:F0 power management I/O registers
e516572f JB	196	offset from the address ICH9_LPC_PMBASE */
	197
	198	/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
	199	#define ICH9_PMIO_SIZE 128
	200	#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
	201
	202	#define ICH9_PMIO_PM1_STS 0x00
	203	#define ICH9_PMIO_PM1_EN 0x02
	204	#define ICH9_PMIO_PM1_CNT 0x04
	205	#define ICH9_PMIO_PM1_TMR 0x08
	206	#define ICH9_PMIO_GPE0_STS 0x20
	207	#define ICH9_PMIO_GPE0_EN 0x28
	208	#define ICH9_PMIO_GPE0_LEN 16
	209	#define ICH9_PMIO_SMI_EN 0x30
	210	#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
92055797	211	#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13)
e516572f	212	#define ICH9_PMIO_SMI_STS 0x34
92055797 PA	213	#define ICH9_PMIO_TCO_RLD 0x60
92055797 PA	214	#define ICH9_PMIO_TCO_LEN 32
e516572f JB	215
	216	/* FADT ACPI_ENABLE/ACPI_DISABLE */
	217	#define ICH9_APM_ACPI_ENABLE 0x2
	218	#define ICH9_APM_ACPI_DISABLE 0x3
	219
	220
	221	/* D31:F3 SMBus controller */
f2dd8ebd EV	222	#define TYPE_ICH9_SMB_DEVICE "ICH9 SMB"
f2dd8ebd EV	223
e516572f JB	224	#define ICH9_A2_SMB_REVISION 0x02
	225	#define ICH9_SMB_PI 0x00
	226
	227	#define ICH9_SMB_SMBMBAR0 0x10
	228	#define ICH9_SMB_SMBMBAR1 0x14
	229	#define ICH9_SMB_SMBM_BAR 0
	230	#define ICH9_SMB_SMBM_SIZE (1 << 8)
	231	#define ICH9_SMB_SMB_BASE 0x20
	232	#define ICH9_SMB_SMB_BASE_BAR 4
	233	#define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
	234	#define ICH9_SMB_HOSTC 0x40
	235	#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
	236	#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
	237	#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
	238	#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
	239
	240	/* D31:F3 SMBus I/O and memory mapped I/O registers */
	241	#define ICH9_SMB_DEV 31
	242	#define ICH9_SMB_FUNC 3
	243
	244	#define ICH9_SMB_HST_STS 0x00
	245	#define ICH9_SMB_HST_CNT 0x02
	246	#define ICH9_SMB_HST_CMD 0x03
	247	#define ICH9_SMB_XMIT_SLVA 0x04
	248	#define ICH9_SMB_HST_D0 0x05
	249	#define ICH9_SMB_HST_D1 0x06
	250	#define ICH9_SMB_HOST_BLOCK_DB 0x07
	251
5ce45c7a LE	252	/* bit positions used in fw_cfg SMI feature negotiation */
	253	#define ICH9_LPC_SMI_F_BROADCAST_BIT 0
	254
e516572f	255	#endif /* HW_ICH9_H */