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target-mips: Add ASE DSP processors
[qemu.git] / cpu-exec.c
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7d13299d 1/*
e965fc38 2 * emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
e4533c7a 19#include "config.h"
cea5f9a2 20#include "cpu.h"
956034d7 21#include "disas.h"
7cb69cae 22#include "tcg.h"
1d93f0f0 23#include "qemu-barrier.h"
c7f0f3b1 24#include "qtest.h"
7d13299d 25
36bdbe54
FB		 26int tb_invalidated_flag;
27
f0667e66 28//#define CONFIG_DEBUG_EXEC
7d13299d 29
9349b4f9 30bool qemu_cpu_has_work(CPUArchState *env)
6a4955a8
AL		 31{
32 return cpu_has_work(env);
33}
34
9349b4f9 35void cpu_loop_exit(CPUArchState *env)
e4533c7a 36{
cea5f9a2
BS		 37 env->current_tb = NULL;
38 longjmp(env->jmp_env, 1);
e4533c7a 39}
bfed01fc 40
fbf9eeb3
FB		 41/* exit the current TB from a signal handler. The host registers are
42 restored in a state compatible with the CPU emulator
43 */
9eff14f3 44#if defined(CONFIG_SOFTMMU)
9349b4f9 45void cpu_resume_from_signal(CPUArchState *env, void *puc)
9eff14f3 46{
9eff14f3
BS		 47 /* XXX: restore cpu registers saved in host registers */
48
49 env->exception_index = -1;
50 longjmp(env->jmp_env, 1);
51}
9eff14f3 52#endif
fbf9eeb3 53
2e70f6ef
PB		 54/* Execute the code without caching the generated code. An interpreter
55 could be used if available. */
9349b4f9 56static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
cea5f9a2 57 TranslationBlock *orig_tb)
2e70f6ef 58{
69784eae 59 tcg_target_ulong next_tb;
2e70f6ef
PB		 60 TranslationBlock *tb;
61
62 /* Should never happen.
63 We only end up here when an existing TB is too long. */
64 if (max_cycles > CF_COUNT_MASK)
65 max_cycles = CF_COUNT_MASK;
66
67 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
68 max_cycles);
69 env->current_tb = tb;
70 /* execute the generated code */
cea5f9a2 71 next_tb = tcg_qemu_tb_exec(env, tb->tc_ptr);
1c3569fe 72 env->current_tb = NULL;
2e70f6ef
PB		 73
74 if ((next_tb & 3) == 2) {
75 /* Restore PC. This may happen if async event occurs before
76 the TB starts executing. */
622ed360 77 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 78 }
79 tb_phys_invalidate(tb, -1);
80 tb_free(tb);
81}
82
9349b4f9 83static TranslationBlock *tb_find_slow(CPUArchState *env,
cea5f9a2 84 target_ulong pc,
8a40a180 85 target_ulong cs_base,
c068688b 86 uint64_t flags)
8a40a180
FB		 87{
88 TranslationBlock *tb, **ptb1;
8a40a180 89 unsigned int h;
337fc758 90 tb_page_addr_t phys_pc, phys_page1;
41c1b1c9 91 target_ulong virt_page2;
3b46e624 92
8a40a180 93 tb_invalidated_flag = 0;
3b46e624 94
8a40a180 95 /* find translated block using physical mappings */
41c1b1c9 96 phys_pc = get_page_addr_code(env, pc);
8a40a180 97 phys_page1 = phys_pc & TARGET_PAGE_MASK;
8a40a180
FB		 98 h = tb_phys_hash_func(phys_pc);
99 ptb1 = &tb_phys_hash[h];
100 for(;;) {
101 tb = *ptb1;
102 if (!tb)
103 goto not_found;
5fafdf24 104 if (tb->pc == pc &&
8a40a180 105 tb->page_addr[0] == phys_page1 &&
5fafdf24 106 tb->cs_base == cs_base &&
8a40a180
FB		 107 tb->flags == flags) {
108 /* check next page if needed */
109 if (tb->page_addr[1] != -1) {
337fc758
BS		 110 tb_page_addr_t phys_page2;
111
5fafdf24 112 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180 113 TARGET_PAGE_SIZE;
41c1b1c9 114 phys_page2 = get_page_addr_code(env, virt_page2);
8a40a180
FB		 115 if (tb->page_addr[1] == phys_page2)
116 goto found;
117 } else {
118 goto found;
119 }
120 }
121 ptb1 = &tb->phys_hash_next;
122 }
123 not_found:
2e70f6ef
PB		 124 /* if no translated code available, then translate it now */
125 tb = tb_gen_code(env, pc, cs_base, flags, 0);
3b46e624 126
8a40a180 127 found:
2c90fe2b
KB		 128 /* Move the last found TB to the head of the list */
129 if (likely(*ptb1)) {
130 *ptb1 = tb->phys_hash_next;
131 tb->phys_hash_next = tb_phys_hash[h];
132 tb_phys_hash[h] = tb;
133 }
8a40a180
FB		 134 /* we add the TB in the virtual pc hash table */
135 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB		 136 return tb;
137}
138
9349b4f9 139static inline TranslationBlock *tb_find_fast(CPUArchState *env)
8a40a180
FB		 140{
141 TranslationBlock *tb;
142 target_ulong cs_base, pc;
6b917547 143 int flags;
8a40a180
FB		 144
145 /* we record a subset of the CPU state. It will
146 always be the same before a given translated block
147 is executed. */
6b917547 148 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bce61846 149 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS		 150 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
151 tb->flags != flags)) {
cea5f9a2 152 tb = tb_find_slow(env, pc, cs_base, flags);
8a40a180
FB		 153 }
154 return tb;
155}
156
1009d2ed
JK		 157static CPUDebugExcpHandler *debug_excp_handler;
158
84e3b602 159void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
1009d2ed 160{
1009d2ed 161 debug_excp_handler = handler;
1009d2ed
JK		 162}
163
9349b4f9 164static void cpu_handle_debug_exception(CPUArchState *env)
1009d2ed
JK		 165{
166 CPUWatchpoint *wp;
167
168 if (!env->watchpoint_hit) {
169 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
170 wp->flags &= ~BP_WATCHPOINT_HIT;
171 }
172 }
173 if (debug_excp_handler) {
174 debug_excp_handler(env);
175 }
176}
177
7d13299d
FB		 178/* main execution loop */
179
1a28cac3
MT		 180volatile sig_atomic_t exit_request;
181
9349b4f9 182int cpu_exec(CPUArchState *env)
7d13299d 183{
c356a1bc
AF		 184#ifdef TARGET_PPC
185 CPUState *cpu = ENV_GET_CPU(env);
186#endif
8a40a180 187 int ret, interrupt_request;
8a40a180 188 TranslationBlock *tb;
c27004ec 189 uint8_t *tc_ptr;
69784eae 190 tcg_target_ulong next_tb;
8c6939c0 191
cea5f9a2
BS		 192 if (env->halted) {
193 if (!cpu_has_work(env)) {
eda48c34
PB		 194 return EXCP_HALTED;
195 }
196
cea5f9a2 197 env->halted = 0;
eda48c34 198 }
5a1e3cfc 199
cea5f9a2 200 cpu_single_env = env;
e4533c7a 201
c629a4bc 202 if (unlikely(exit_request)) {
1a28cac3 203 env->exit_request = 1;
1a28cac3
MT		 204 }
205
ecb644f4 206#if defined(TARGET_I386)
6792a57b
JK		 207 /* put eflags in CPU temporary format */
208 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
209 DF = 1 - (2 * ((env->eflags >> 10) & 1));
210 CC_OP = CC_OP_EFLAGS;
211 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
93ac68bc 212#elif defined(TARGET_SPARC)
e6e5906b
PB		 213#elif defined(TARGET_M68K)
214 env->cc_op = CC_OP_FLAGS;
215 env->cc_dest = env->sr & 0xf;
216 env->cc_x = (env->sr >> 4) & 1;
ecb644f4
TS		 217#elif defined(TARGET_ALPHA)
218#elif defined(TARGET_ARM)
d2fbca94 219#elif defined(TARGET_UNICORE32)
ecb644f4 220#elif defined(TARGET_PPC)
4e85f82c 221 env->reserve_addr = -1;
81ea0e13 222#elif defined(TARGET_LM32)
b779e29e 223#elif defined(TARGET_MICROBLAZE)
6af0bf9c 224#elif defined(TARGET_MIPS)
e67db06e 225#elif defined(TARGET_OPENRISC)
fdf9b3e8 226#elif defined(TARGET_SH4)
f1ccf904 227#elif defined(TARGET_CRIS)
10ec5117 228#elif defined(TARGET_S390X)
2328826b 229#elif defined(TARGET_XTENSA)
fdf9b3e8 230 /* XXXXX */
e4533c7a
FB		 231#else
232#error unsupported target CPU
233#endif
3fb2ded1 234 env->exception_index = -1;
9d27abd9 235
7d13299d 236 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 237 for(;;) {
238 if (setjmp(env->jmp_env) == 0) {
239 /* if an exception is pending, we execute it here */
240 if (env->exception_index >= 0) {
241 if (env->exception_index >= EXCP_INTERRUPT) {
242 /* exit request from the cpu execution loop */
243 ret = env->exception_index;
1009d2ed
JK		 244 if (ret == EXCP_DEBUG) {
245 cpu_handle_debug_exception(env);
246 }
3fb2ded1 247 break;
72d239ed
AJ		 248 } else {
249#if defined(CONFIG_USER_ONLY)
3fb2ded1 250 /* if user mode only, we simulate a fake exception
9f083493 251 which will be handled outside the cpu execution
3fb2ded1 252 loop */
83479e77 253#if defined(TARGET_I386)
e694d4e2 254 do_interrupt(env);
83479e77 255#endif
3fb2ded1
FB		 256 ret = env->exception_index;
257 break;
72d239ed 258#else
b5ff1b31 259 do_interrupt(env);
301d2908 260 env->exception_index = -1;
83479e77 261#endif
3fb2ded1 262 }
5fafdf24 263 }
9df217a3 264
b5fc09ae 265 next_tb = 0; /* force lookup of first TB */
3fb2ded1 266 for(;;) {
68a79315 267 interrupt_request = env->interrupt_request;
e1638bd8 268 if (unlikely(interrupt_request)) {
269 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
270 /* Mask out external interrupts for this step. */
3125f763 271 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
e1638bd8 272 }
6658ffb8
PB		 273 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
274 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
275 env->exception_index = EXCP_DEBUG;
1162c041 276 cpu_loop_exit(env);
6658ffb8 277 }
a90b7318 278#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
b779e29e 279 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
d2fbca94 280 defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
a90b7318
AZ		 281 if (interrupt_request & CPU_INTERRUPT_HALT) {
282 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
283 env->halted = 1;
284 env->exception_index = EXCP_HLT;
1162c041 285 cpu_loop_exit(env);
a90b7318
AZ		 286 }
287#endif
68a79315 288#if defined(TARGET_I386)
5d62c43a
JK		 289#if !defined(CONFIG_USER_ONLY)
290 if (interrupt_request & CPU_INTERRUPT_POLL) {
291 env->interrupt_request &= ~CPU_INTERRUPT_POLL;
292 apic_poll_irq(env->apic_state);
293 }
294#endif
b09ea7d5 295 if (interrupt_request & CPU_INTERRUPT_INIT) {
77b2bc2c
BS		 296 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
297 0);
232fc23b 298 do_cpu_init(x86_env_get_cpu(env));
b09ea7d5 299 env->exception_index = EXCP_HALTED;
1162c041 300 cpu_loop_exit(env);
b09ea7d5 301 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
232fc23b 302 do_cpu_sipi(x86_env_get_cpu(env));
b09ea7d5 303 } else if (env->hflags2 & HF2_GIF_MASK) {
db620f46
FB		 304 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
305 !(env->hflags & HF_SMM_MASK)) {
77b2bc2c
BS		 306 cpu_svm_check_intercept_param(env, SVM_EXIT_SMI,
307 0);
db620f46 308 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
e694d4e2 309 do_smm_enter(env);
db620f46
FB		 310 next_tb = 0;
311 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
312 !(env->hflags2 & HF2_NMI_MASK)) {
313 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
314 env->hflags2 |= HF2_NMI_MASK;
e694d4e2 315 do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
db620f46 316 next_tb = 0;
e965fc38 317 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
79c4f6b0 318 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
e694d4e2 319 do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
79c4f6b0 320 next_tb = 0;
db620f46
FB		 321 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
322 (((env->hflags2 & HF2_VINTR_MASK) &&
323 (env->hflags2 & HF2_HIF_MASK)) ||
324 (!(env->hflags2 & HF2_VINTR_MASK) &&
325 (env->eflags & IF_MASK &&
326 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
327 int intno;
77b2bc2c
BS		 328 cpu_svm_check_intercept_param(env, SVM_EXIT_INTR,
329 0);
db620f46
FB		 330 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
331 intno = cpu_get_pic_interrupt(env);
4f213879 332 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
333 do_interrupt_x86_hardirq(env, intno, 1);
334 /* ensure that no TB jump will be modified as
335 the program flow was changed */
336 next_tb = 0;
0573fbfc 337#if !defined(CONFIG_USER_ONLY)
db620f46
FB		 338 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
339 (env->eflags & IF_MASK) &&
340 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
341 int intno;
342 /* FIXME: this should respect TPR */
77b2bc2c
BS		 343 cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
344 0);
db620f46 345 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
93fcfe39 346 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
e694d4e2 347 do_interrupt_x86_hardirq(env, intno, 1);
d40c54d6 348 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
db620f46 349 next_tb = 0;
907a5b26 350#endif
db620f46 351 }
68a79315 352 }
ce09776b 353#elif defined(TARGET_PPC)
9fddaa0c 354 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
c356a1bc 355 cpu_reset(cpu);
9fddaa0c 356 }
47103572 357 if (interrupt_request & CPU_INTERRUPT_HARD) {
e9df014c
JM		 358 ppc_hw_interrupt(env);
359 if (env->pending_interrupts == 0)
360 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
b5fc09ae 361 next_tb = 0;
ce09776b 362 }
81ea0e13
MW		 363#elif defined(TARGET_LM32)
364 if ((interrupt_request & CPU_INTERRUPT_HARD)
365 && (env->ie & IE_IE)) {
366 env->exception_index = EXCP_IRQ;
367 do_interrupt(env);
368 next_tb = 0;
369 }
b779e29e
EI		 370#elif defined(TARGET_MICROBLAZE)
371 if ((interrupt_request & CPU_INTERRUPT_HARD)
372 && (env->sregs[SR_MSR] & MSR_IE)
373 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
374 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
375 env->exception_index = EXCP_IRQ;
376 do_interrupt(env);
377 next_tb = 0;
378 }
6af0bf9c
FB		 379#elif defined(TARGET_MIPS)
380 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
4cdc1cd1 381 cpu_mips_hw_interrupts_pending(env)) {
6af0bf9c
FB		 382 /* Raise it */
383 env->exception_index = EXCP_EXT_INTERRUPT;
384 env->error_code = 0;
385 do_interrupt(env);
b5fc09ae 386 next_tb = 0;
6af0bf9c 387 }
b6a71ef7
JL		 388#elif defined(TARGET_OPENRISC)
389 {
390 int idx = -1;
391 if ((interrupt_request & CPU_INTERRUPT_HARD)
392 && (env->sr & SR_IEE)) {
393 idx = EXCP_INT;
394 }
395 if ((interrupt_request & CPU_INTERRUPT_TIMER)
396 && (env->sr & SR_TEE)) {
397 idx = EXCP_TICK;
398 }
399 if (idx >= 0) {
400 env->exception_index = idx;
401 do_interrupt(env);
402 next_tb = 0;
403 }
404 }
e95c8d51 405#elif defined(TARGET_SPARC)
d532b26c
IK		 406 if (interrupt_request & CPU_INTERRUPT_HARD) {
407 if (cpu_interrupts_enabled(env) &&
408 env->interrupt_index > 0) {
409 int pil = env->interrupt_index & 0xf;
410 int type = env->interrupt_index & 0xf0;
411
412 if (((type == TT_EXTINT) &&
413 cpu_pil_allowed(env, pil)) ||
414 type != TT_EXTINT) {
415 env->exception_index = env->interrupt_index;
416 do_interrupt(env);
417 next_tb = 0;
418 }
419 }
e965fc38 420 }
b5ff1b31
FB		 421#elif defined(TARGET_ARM)
422 if (interrupt_request & CPU_INTERRUPT_FIQ
423 && !(env->uncached_cpsr & CPSR_F)) {
424 env->exception_index = EXCP_FIQ;
425 do_interrupt(env);
b5fc09ae 426 next_tb = 0;
b5ff1b31 427 }
9ee6e8bb
PB		 428 /* ARMv7-M interrupt return works by loading a magic value
429 into the PC. On real hardware the load causes the
430 return to occur. The qemu implementation performs the
431 jump normally, then does the exception return when the
432 CPU tries to execute code at the magic address.
433 This will cause the magic PC value to be pushed to
a1c7273b 434 the stack if an interrupt occurred at the wrong time.
9ee6e8bb
PB		 435 We avoid this by disabling interrupts when
436 pc contains a magic address. */
b5ff1b31 437 if (interrupt_request & CPU_INTERRUPT_HARD
9ee6e8bb
PB		 438 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
439 || !(env->uncached_cpsr & CPSR_I))) {
b5ff1b31
FB		 440 env->exception_index = EXCP_IRQ;
441 do_interrupt(env);
b5fc09ae 442 next_tb = 0;
b5ff1b31 443 }
d2fbca94
GX		 444#elif defined(TARGET_UNICORE32)
445 if (interrupt_request & CPU_INTERRUPT_HARD
446 && !(env->uncached_asr & ASR_I)) {
d48813dd 447 env->exception_index = UC32_EXCP_INTR;
d2fbca94
GX		 448 do_interrupt(env);
449 next_tb = 0;
450 }
fdf9b3e8 451#elif defined(TARGET_SH4)
e96e2044
TS		 452 if (interrupt_request & CPU_INTERRUPT_HARD) {
453 do_interrupt(env);
b5fc09ae 454 next_tb = 0;
e96e2044 455 }
eddf68a6 456#elif defined(TARGET_ALPHA)
6a80e088
RH		 457 {
458 int idx = -1;
459 /* ??? This hard-codes the OSF/1 interrupt levels. */
e965fc38 460 switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
6a80e088
RH		 461 case 0 ... 3:
462 if (interrupt_request & CPU_INTERRUPT_HARD) {
463 idx = EXCP_DEV_INTERRUPT;
464 }
465 /* FALLTHRU */
466 case 4:
467 if (interrupt_request & CPU_INTERRUPT_TIMER) {
468 idx = EXCP_CLK_INTERRUPT;
469 }
470 /* FALLTHRU */
471 case 5:
472 if (interrupt_request & CPU_INTERRUPT_SMP) {
473 idx = EXCP_SMP_INTERRUPT;
474 }
475 /* FALLTHRU */
476 case 6:
477 if (interrupt_request & CPU_INTERRUPT_MCHK) {
478 idx = EXCP_MCHK;
479 }
480 }
481 if (idx >= 0) {
482 env->exception_index = idx;
483 env->error_code = 0;
484 do_interrupt(env);
485 next_tb = 0;
486 }
eddf68a6 487 }
f1ccf904 488#elif defined(TARGET_CRIS)
1b1a38b0 489 if (interrupt_request & CPU_INTERRUPT_HARD
fb9fb692
EI		 490 && (env->pregs[PR_CCS] & I_FLAG)
491 && !env->locked_irq) {
1b1a38b0
EI		 492 env->exception_index = EXCP_IRQ;
493 do_interrupt(env);
494 next_tb = 0;
495 }
8219314b
LP		 496 if (interrupt_request & CPU_INTERRUPT_NMI) {
497 unsigned int m_flag_archval;
498 if (env->pregs[PR_VR] < 32) {
499 m_flag_archval = M_FLAG_V10;
500 } else {
501 m_flag_archval = M_FLAG_V32;
502 }
503 if ((env->pregs[PR_CCS] & m_flag_archval)) {
504 env->exception_index = EXCP_NMI;
505 do_interrupt(env);
506 next_tb = 0;
507 }
f1ccf904 508 }
0633879f
PB		 509#elif defined(TARGET_M68K)
510 if (interrupt_request & CPU_INTERRUPT_HARD
511 && ((env->sr & SR_I) >> SR_I_SHIFT)
512 < env->pending_level) {
513 /* Real hardware gets the interrupt vector via an
514 IACK cycle at this point. Current emulated
515 hardware doesn't rely on this, so we
516 provide/save the vector when the interrupt is
517 first signalled. */
518 env->exception_index = env->pending_vector;
3c688828 519 do_interrupt_m68k_hardirq(env);
b5fc09ae 520 next_tb = 0;
0633879f 521 }
3110e292
AG		 522#elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
523 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
524 (env->psw.mask & PSW_MASK_EXT)) {
525 do_interrupt(env);
526 next_tb = 0;
527 }
40643d7c
MF		 528#elif defined(TARGET_XTENSA)
529 if (interrupt_request & CPU_INTERRUPT_HARD) {
530 env->exception_index = EXC_IRQ;
531 do_interrupt(env);
532 next_tb = 0;
533 }
68a79315 534#endif
ff2712ba 535 /* Don't use the cached interrupt_request value,
9d05095e 536 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 537 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 538 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
539 /* ensure that no TB jump will be modified as
540 the program flow was changed */
b5fc09ae 541 next_tb = 0;
bf3e8bf1 542 }
be214e6c
AJ		 543 }
544 if (unlikely(env->exit_request)) {
545 env->exit_request = 0;
546 env->exception_index = EXCP_INTERRUPT;
1162c041 547 cpu_loop_exit(env);
3fb2ded1 548 }
a73b1fd9 549#if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
8fec2b8c 550 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
3fb2ded1 551 /* restore flags in standard format */
ecb644f4 552#if defined(TARGET_I386)
e694d4e2
BS		 553 env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
554 | (DF & DF_MASK);
6fd2a026 555 log_cpu_state(env, CPU_DUMP_CCOP);
3fb2ded1 556 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e6e5906b
PB		 557#elif defined(TARGET_M68K)
558 cpu_m68k_flush_flags(env, env->cc_op);
559 env->cc_op = CC_OP_FLAGS;
560 env->sr = (env->sr & 0xffe0)
561 | env->cc_dest | (env->cc_x << 4);
93fcfe39 562 log_cpu_state(env, 0);
e4533c7a 563#else
a73b1fd9 564 log_cpu_state(env, 0);
e4533c7a 565#endif
3fb2ded1 566 }
a73b1fd9 567#endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
d5975363 568 spin_lock(&tb_lock);
cea5f9a2 569 tb = tb_find_fast(env);
d5975363
PB		 570 /* Note: we do it here to avoid a gcc bug on Mac OS X when
571 doing it in tb_find_slow */
572 if (tb_invalidated_flag) {
573 /* as some TB could have been invalidated because
574 of memory exceptions while generating the code, we
575 must recompute the hash index here */
576 next_tb = 0;
2e70f6ef 577 tb_invalidated_flag = 0;
d5975363 578 }
f0667e66 579#ifdef CONFIG_DEBUG_EXEC
3ba19255
SW		 580 qemu_log_mask(CPU_LOG_EXEC, "Trace %p [" TARGET_FMT_lx "] %s\n",
581 tb->tc_ptr, tb->pc,
93fcfe39 582 lookup_symbol(tb->pc));
9d27abd9 583#endif
8a40a180
FB		 584 /* see if we can patch the calling TB. When the TB
585 spans two pages, we cannot safely do a direct
586 jump. */
040f2fb2 587 if (next_tb != 0 && tb->page_addr[1] == -1) {
b5fc09ae 588 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
3fb2ded1 589 }
d5975363 590 spin_unlock(&tb_lock);
55e8b85e 591
592 /* cpu_interrupt might be called while translating the
593 TB, but before it is linked into a potentially
594 infinite loop and becomes env->current_tb. Avoid
595 starting execution if there is a pending interrupt. */
b0052d15
JK		 596 env->current_tb = tb;
597 barrier();
598 if (likely(!env->exit_request)) {
2e70f6ef 599 tc_ptr = tb->tc_ptr;
e965fc38 600 /* execute the generated code */
cea5f9a2 601 next_tb = tcg_qemu_tb_exec(env, tc_ptr);
2e70f6ef 602 if ((next_tb & 3) == 2) {
bf20dc07 603 /* Instruction counter expired. */
2e70f6ef 604 int insns_left;
69784eae 605 tb = (TranslationBlock *)(next_tb & ~3);
2e70f6ef 606 /* Restore PC. */
622ed360 607 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 608 insns_left = env->icount_decr.u32;
609 if (env->icount_extra && insns_left >= 0) {
610 /* Refill decrementer and continue execution. */
611 env->icount_extra += insns_left;
612 if (env->icount_extra > 0xffff) {
613 insns_left = 0xffff;
614 } else {
615 insns_left = env->icount_extra;
616 }
617 env->icount_extra -= insns_left;
618 env->icount_decr.u16.low = insns_left;
619 } else {
620 if (insns_left > 0) {
621 /* Execute remaining instructions. */
cea5f9a2 622 cpu_exec_nocache(env, insns_left, tb);
2e70f6ef
PB		 623 }
624 env->exception_index = EXCP_INTERRUPT;
625 next_tb = 0;
1162c041 626 cpu_loop_exit(env);
2e70f6ef
PB		 627 }
628 }
629 }
b0052d15 630 env->current_tb = NULL;
4cbf74b6
FB		 631 /* reset soft MMU for next block (it can currently
632 only be set by a memory fault) */
50a518e3 633 } /* for(;;) */
0d101938
JK		 634 } else {
635 /* Reload env after longjmp - the compiler may have smashed all
636 * local variables as longjmp is marked 'noreturn'. */
637 env = cpu_single_env;
7d13299d 638 }
3fb2ded1
FB		 639 } /* for(;;) */
640
7d13299d 641
e4533c7a 642#if defined(TARGET_I386)
9de5e440 643 /* restore flags in standard format */
e694d4e2
BS		 644 env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
645 | (DF & DF_MASK);
e4533c7a 646#elif defined(TARGET_ARM)
b7bcbe95 647 /* XXX: Save/restore host fpu exception state?. */
d2fbca94 648#elif defined(TARGET_UNICORE32)
93ac68bc 649#elif defined(TARGET_SPARC)
67867308 650#elif defined(TARGET_PPC)
81ea0e13 651#elif defined(TARGET_LM32)
e6e5906b
PB		 652#elif defined(TARGET_M68K)
653 cpu_m68k_flush_flags(env, env->cc_op);
654 env->cc_op = CC_OP_FLAGS;
655 env->sr = (env->sr & 0xffe0)
656 | env->cc_dest | (env->cc_x << 4);
b779e29e 657#elif defined(TARGET_MICROBLAZE)
6af0bf9c 658#elif defined(TARGET_MIPS)
e67db06e 659#elif defined(TARGET_OPENRISC)
fdf9b3e8 660#elif defined(TARGET_SH4)
eddf68a6 661#elif defined(TARGET_ALPHA)
f1ccf904 662#elif defined(TARGET_CRIS)
10ec5117 663#elif defined(TARGET_S390X)
2328826b 664#elif defined(TARGET_XTENSA)
fdf9b3e8 665 /* XXXXX */
e4533c7a
FB		 666#else
667#error unsupported target CPU
668#endif
1057eaa7 669
6a00d601 670 /* fail safe : never use cpu_single_env outside cpu_exec() */
5fafdf24 671 cpu_single_env = NULL;
7d13299d
FB		 672 return ret;
673}
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