[qemu.git] / target-unicore32 / helper.c

/*
 * Copyright (C) 2010-2011 GUAN Xue-tao
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Contributions from 2012-04-01 on are considered under GPL version 2,
 * or (at your option) any later version.
 */

#include "cpu.h"
#include "gdbstub.h"
#include "helper.h"
#include "host-utils.h"

static inline void set_feature(CPUUniCore32State *env, int feature)
{
    env->features |= feature;
}

CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
{
    UniCore32CPU *cpu;
    CPUUniCore32State *env;
    uint32_t id;
    static int inited = 1;

    if (object_class_by_name(cpu_model) == NULL) {
        return NULL;
    }
    cpu = UNICORE32_CPU(object_new(cpu_model));
    env = &cpu->env;

    id = env->cp0.c0_cpuid;
    switch (id) {
    case UC32_CPUID_UCV2:
        set_feature(env, UC32_HWCAP_CMOV);
        set_feature(env, UC32_HWCAP_UCF64);
        env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
        env->cp0.c0_cachetype = 0x1dd20d2;
        env->cp0.c1_sys = 0x00090078;
        break;
    case UC32_CPUID_ANY: /* For userspace emulation.  */
        set_feature(env, UC32_HWCAP_CMOV);
        set_feature(env, UC32_HWCAP_UCF64);
        break;
    default:
        cpu_abort(env, "Bad CPU ID: %x\n", id);
    }

    if (inited) {
        inited = 0;
        uc32_translate_init();
    }

    qemu_init_vcpu(env);
    return env;
}

uint32_t HELPER(clo)(uint32_t x)
{
    return clo32(x);
}

uint32_t HELPER(clz)(uint32_t x)
{
    return clz32(x);
}

void do_interrupt(CPUUniCore32State *env)
{
    env->exception_index = -1;
}

int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
                              int mmu_idx)
{
    env->exception_index = UC32_EXCP_TRAP;
    env->cp0.c4_faultaddr = address;
    return 1;
}

/* These should probably raise undefined insn exceptions.  */
void HELPER(set_cp)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
{
    int op1 = (insn >> 8) & 0xf;
    cpu_abort(env, "cp%i insn %08x\n", op1, insn);
    return;
}

uint32_t HELPER(get_cp)(CPUUniCore32State *env, uint32_t insn)
{
    int op1 = (insn >> 8) & 0xf;
    cpu_abort(env, "cp%i insn %08x\n", op1, insn);
    return 0;
}

void HELPER(set_cp0)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
{
    cpu_abort(env, "cp0 insn %08x\n", insn);
}

uint32_t HELPER(get_cp0)(CPUUniCore32State *env, uint32_t insn)
{
    cpu_abort(env, "cp0 insn %08x\n", insn);
    return 0;
}

void switch_mode(CPUUniCore32State *env, int mode)
{
    if (mode != ASR_MODE_USER) {
        cpu_abort(env, "Tried to switch out of user mode\n");
    }
}

void HELPER(set_r29_banked)(CPUUniCore32State *env, uint32_t mode, uint32_t val)
{
    cpu_abort(env, "banked r29 write\n");
}

uint32_t HELPER(get_r29_banked)(CPUUniCore32State *env, uint32_t mode)
{
    cpu_abort(env, "banked r29 read\n");
    return 0;
}

/* UniCore-F64 support.  We follow the convention used for F64 instrunctions:
   Single precition routines have a "s" suffix, double precision a
   "d" suffix.  */

/* Convert host exception flags to f64 form.  */
static inline int ucf64_exceptbits_from_host(int host_bits)
{
    int target_bits = 0;

    if (host_bits & float_flag_invalid) {
        target_bits |= UCF64_FPSCR_FLAG_INVALID;
    }
    if (host_bits & float_flag_divbyzero) {
        target_bits |= UCF64_FPSCR_FLAG_DIVZERO;
    }
    if (host_bits & float_flag_overflow) {
        target_bits |= UCF64_FPSCR_FLAG_OVERFLOW;
    }
    if (host_bits & float_flag_underflow) {
        target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW;
    }
    if (host_bits & float_flag_inexact) {
        target_bits |= UCF64_FPSCR_FLAG_INEXACT;
    }
    return target_bits;
}

uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
{
    int i;
    uint32_t fpscr;

    fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
    i = get_float_exception_flags(&env->ucf64.fp_status);
    fpscr |= ucf64_exceptbits_from_host(i);
    return fpscr;
}

/* Convert ucf64 exception flags to target form.  */
static inline int ucf64_exceptbits_to_host(int target_bits)
{
    int host_bits = 0;

    if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
        host_bits |= float_flag_invalid;
    }
    if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
        host_bits |= float_flag_divbyzero;
    }
    if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
        host_bits |= float_flag_overflow;
    }
    if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
        host_bits |= float_flag_underflow;
    }
    if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
        host_bits |= float_flag_inexact;
    }
    return host_bits;
}

void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
{
    int i;
    uint32_t changed;

    changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
    env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);

    changed ^= val;
    if (changed & (UCF64_FPSCR_RND_MASK)) {
        i = UCF64_FPSCR_RND(val);
        switch (i) {
        case 0:
            i = float_round_nearest_even;
            break;
        case 1:
            i = float_round_to_zero;
            break;
        case 2:
            i = float_round_up;
            break;
        case 3:
            i = float_round_down;
            break;
        default: /* 100 and 101 not implement */
            cpu_abort(env, "Unsupported UniCore-F64 round mode");
        }
        set_float_rounding_mode(i, &env->ucf64.fp_status);
    }

    i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
    set_float_exception_flags(i, &env->ucf64.fp_status);
}

float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
{
    return float32_add(a, b, &env->ucf64.fp_status);
}

float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
{
    return float64_add(a, b, &env->ucf64.fp_status);
}

float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
{
    return float32_sub(a, b, &env->ucf64.fp_status);
}

float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
{
    return float64_sub(a, b, &env->ucf64.fp_status);
}

float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
{
    return float32_mul(a, b, &env->ucf64.fp_status);
}

float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
{
    return float64_mul(a, b, &env->ucf64.fp_status);
}

float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
{
    return float32_div(a, b, &env->ucf64.fp_status);
}

float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUniCore32State *env)
{
    return float64_div(a, b, &env->ucf64.fp_status);
}

float32 HELPER(ucf64_negs)(float32 a)
{
    return float32_chs(a);
}

float64 HELPER(ucf64_negd)(float64 a)
{
    return float64_chs(a);
}

float32 HELPER(ucf64_abss)(float32 a)
{
    return float32_abs(a);
}

float64 HELPER(ucf64_absd)(float64 a)
{
    return float64_abs(a);
}

/* XXX: check quiet/signaling case */
void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUUniCore32State *env)
{
    int flag;
    flag = float32_compare_quiet(a, b, &env->ucf64.fp_status);
    env->CF = 0;
    switch (c & 0x7) {
    case 0: /* F */
        break;
    case 1: /* UN */
        if (flag == 2) {
            env->CF = 1;
        }
        break;
    case 2: /* EQ */
        if (flag == 0) {
            env->CF = 1;
        }
        break;
    case 3: /* UEQ */
        if ((flag == 0) || (flag == 2)) {
            env->CF = 1;
        }
        break;
    case 4: /* OLT */
        if (flag == -1) {
            env->CF = 1;
        }
        break;
    case 5: /* ULT */
        if ((flag == -1) || (flag == 2)) {
            env->CF = 1;
        }
        break;
    case 6: /* OLE */
        if ((flag == -1) || (flag == 0)) {
            env->CF = 1;
        }
        break;
    case 7: /* ULE */
        if (flag != 1) {
            env->CF = 1;
        }
        break;
    }
    env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
                    | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
}

void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c, CPUUniCore32State *env)
{
    int flag;
    flag = float64_compare_quiet(a, b, &env->ucf64.fp_status);
    env->CF = 0;
    switch (c & 0x7) {
    case 0: /* F */
        break;
    case 1: /* UN */
        if (flag == 2) {
            env->CF = 1;
        }
        break;
    case 2: /* EQ */
        if (flag == 0) {
            env->CF = 1;
        }
        break;
    case 3: /* UEQ */
        if ((flag == 0) || (flag == 2)) {
            env->CF = 1;
        }
        break;
    case 4: /* OLT */
        if (flag == -1) {
            env->CF = 1;
        }
        break;
    case 5: /* ULT */
        if ((flag == -1) || (flag == 2)) {
            env->CF = 1;
        }
        break;
    case 6: /* OLE */
        if ((flag == -1) || (flag == 0)) {
            env->CF = 1;
        }
        break;
    case 7: /* ULE */
        if (flag != 1) {
            env->CF = 1;
        }
        break;
    }
    env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
                    | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
}

/* Helper routines to perform bitwise copies between float and int.  */
static inline float32 ucf64_itos(uint32_t i)
{
    union {
        uint32_t i;
        float32 s;
    } v;

    v.i = i;
    return v.s;
}

static inline uint32_t ucf64_stoi(float32 s)
{
    union {
        uint32_t i;
        float32 s;
    } v;

    v.s = s;
    return v.i;
}

static inline float64 ucf64_itod(uint64_t i)
{
    union {
        uint64_t i;
        float64 d;
    } v;

    v.i = i;
    return v.d;
}

static inline uint64_t ucf64_dtoi(float64 d)
{
    union {
        uint64_t i;
        float64 d;
    } v;

    v.d = d;
    return v.i;
}

/* Integer to float conversion.  */
float32 HELPER(ucf64_si2sf)(float32 x, CPUUniCore32State *env)
{
    return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status);
}

float64 HELPER(ucf64_si2df)(float32 x, CPUUniCore32State *env)
{
    return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status);
}

/* Float to integer conversion.  */
float32 HELPER(ucf64_sf2si)(float32 x, CPUUniCore32State *env)
{
    return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status));
}

float32 HELPER(ucf64_df2si)(float64 x, CPUUniCore32State *env)
{
    return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));
}

/* floating point conversion */
float64 HELPER(ucf64_sf2df)(float32 x, CPUUniCore32State *env)
{
    return float32_to_float64(x, &env->ucf64.fp_status);
}

float32 HELPER(ucf64_df2sf)(float64 x, CPUUniCore32State *env)
{
    return float64_to_float32(x, &env->ucf64.fp_status);
}
Commit	Line	Data
6e64da3c GX	1	/*
	2	* Copyright (C) 2010-2011 GUAN Xue-tao
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
c3a8baa9 AF	7	*
	8	* Contributions from 2012-04-01 on are considered under GPL version 2,
	9	* or (at your option) any later version.
6e64da3c	10	*/
6e64da3c GX	11
6e64da3c GX	12	#include "cpu.h"
6e64da3c GX	13	#include "gdbstub.h"
6e64da3c GX	14	#include "helper.h"
6e64da3c GX	15	#include "host-utils.h"
6e64da3c GX	16
eb23b556	17	static inline void set_feature(CPUUniCore32State *env, int feature)
6e64da3c GX	18	{
	19	env->features \|= feature;
	20	}
	21
eb23b556	22	CPUUniCore32State uc32_cpu_init(const char cpu_model)
6e64da3c	23	{
ae0f5e9e	24	UniCore32CPU *cpu;
eb23b556	25	CPUUniCore32State *env;
6e64da3c GX	26	uint32_t id;
	27	static int inited = 1;
	28
ae0f5e9e AF	29	if (object_class_by_name(cpu_model) == NULL) {
	30	return NULL;
	31	}
	32	cpu = UNICORE32_CPU(object_new(cpu_model));
	33	env = &cpu->env;
6e64da3c	34
ae0f5e9e	35	id = env->cp0.c0_cpuid;
6e64da3c GX	36	switch (id) {
	37	case UC32_CPUID_UCV2:
	38	set_feature(env, UC32_HWCAP_CMOV);
	39	set_feature(env, UC32_HWCAP_UCF64);
	40	env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
	41	env->cp0.c0_cachetype = 0x1dd20d2;
	42	env->cp0.c1_sys = 0x00090078;
	43	break;
	44	case UC32_CPUID_ANY: /* For userspace emulation. */
	45	set_feature(env, UC32_HWCAP_CMOV);
	46	set_feature(env, UC32_HWCAP_UCF64);
	47	break;
	48	default:
	49	cpu_abort(env, "Bad CPU ID: %x\n", id);
	50	}
	51
6e64da3c GX	52	if (inited) {
	53	inited = 0;
	54	uc32_translate_init();
	55	}
	56
6e64da3c GX	57	qemu_init_vcpu(env);
	58	return env;
	59	}
	60
	61	uint32_t HELPER(clo)(uint32_t x)
	62	{
	63	return clo32(x);
	64	}
	65
	66	uint32_t HELPER(clz)(uint32_t x)
	67	{
	68	return clz32(x);
	69	}
	70
eb23b556	71	void do_interrupt(CPUUniCore32State *env)
6e64da3c GX	72	{
	73	env->exception_index = -1;
	74	}
	75
eb23b556	76	int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
97b348e7	77	int mmu_idx)
6e64da3c GX	78	{
	79	env->exception_index = UC32_EXCP_TRAP;
	80	env->cp0.c4_faultaddr = address;
	81	return 1;
	82	}
	83
	84	/* These should probably raise undefined insn exceptions. */
eb23b556	85	void HELPER(set_cp)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
6e64da3c GX	86	{
	87	int op1 = (insn >> 8) & 0xf;
	88	cpu_abort(env, "cp%i insn %08x\n", op1, insn);
	89	return;
	90	}
	91
eb23b556	92	uint32_t HELPER(get_cp)(CPUUniCore32State *env, uint32_t insn)
6e64da3c GX	93	{
	94	int op1 = (insn >> 8) & 0xf;
	95	cpu_abort(env, "cp%i insn %08x\n", op1, insn);
	96	return 0;
	97	}
	98
eb23b556	99	void HELPER(set_cp0)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
6e64da3c GX	100	{
	101	cpu_abort(env, "cp0 insn %08x\n", insn);
	102	}
	103
eb23b556	104	uint32_t HELPER(get_cp0)(CPUUniCore32State *env, uint32_t insn)
6e64da3c GX	105	{
	106	cpu_abort(env, "cp0 insn %08x\n", insn);
	107	return 0;
	108	}
	109
eb23b556	110	void switch_mode(CPUUniCore32State *env, int mode)
6e64da3c GX	111	{
	112	if (mode != ASR_MODE_USER) {
	113	cpu_abort(env, "Tried to switch out of user mode\n");
	114	}
	115	}
	116
eb23b556	117	void HELPER(set_r29_banked)(CPUUniCore32State *env, uint32_t mode, uint32_t val)
6e64da3c GX	118	{
	119	cpu_abort(env, "banked r29 write\n");
	120	}
	121
eb23b556	122	uint32_t HELPER(get_r29_banked)(CPUUniCore32State *env, uint32_t mode)
6e64da3c GX	123	{
	124	cpu_abort(env, "banked r29 read\n");
	125	return 0;
	126	}
	127
	128	/* UniCore-F64 support. We follow the convention used for F64 instrunctions:
	129	Single precition routines have a "s" suffix, double precision a
	130	"d" suffix. */
	131
	132	/* Convert host exception flags to f64 form. */
	133	static inline int ucf64_exceptbits_from_host(int host_bits)
	134	{
	135	int target_bits = 0;
	136
	137	if (host_bits & float_flag_invalid) {
	138	target_bits \|= UCF64_FPSCR_FLAG_INVALID;
	139	}
	140	if (host_bits & float_flag_divbyzero) {
	141	target_bits \|= UCF64_FPSCR_FLAG_DIVZERO;
	142	}
	143	if (host_bits & float_flag_overflow) {
	144	target_bits \|= UCF64_FPSCR_FLAG_OVERFLOW;
	145	}
	146	if (host_bits & float_flag_underflow) {
	147	target_bits \|= UCF64_FPSCR_FLAG_UNDERFLOW;
	148	}
	149	if (host_bits & float_flag_inexact) {
	150	target_bits \|= UCF64_FPSCR_FLAG_INEXACT;
	151	}
	152	return target_bits;
	153	}
	154
eb23b556	155	uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
6e64da3c GX	156	{
	157	int i;
	158	uint32_t fpscr;
	159
	160	fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
	161	i = get_float_exception_flags(&env->ucf64.fp_status);
	162	fpscr \|= ucf64_exceptbits_from_host(i);
	163	return fpscr;
	164	}
	165
	166	/* Convert ucf64 exception flags to target form. */
	167	static inline int ucf64_exceptbits_to_host(int target_bits)
	168	{
	169	int host_bits = 0;
	170
	171	if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
	172	host_bits \|= float_flag_invalid;
	173	}
	174	if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
	175	host_bits \|= float_flag_divbyzero;
	176	}
	177	if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
	178	host_bits \|= float_flag_overflow;
	179	}
	180	if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
	181	host_bits \|= float_flag_underflow;
	182	}
	183	if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
	184	host_bits \|= float_flag_inexact;
	185	}
	186	return host_bits;
	187	}
	188
eb23b556	189	void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
6e64da3c GX	190	{
	191	int i;
	192	uint32_t changed;
	193
	194	changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
	195	env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);
	196
	197	changed ^= val;
	198	if (changed & (UCF64_FPSCR_RND_MASK)) {
	199	i = UCF64_FPSCR_RND(val);
	200	switch (i) {
	201	case 0:
	202	i = float_round_nearest_even;
	203	break;
	204	case 1:
	205	i = float_round_to_zero;
	206	break;
	207	case 2:
	208	i = float_round_up;
	209	break;
	210	case 3:
	211	i = float_round_down;
	212	break;
	213	default: /* 100 and 101 not implement */
	214	cpu_abort(env, "Unsupported UniCore-F64 round mode");
	215	}
	216	set_float_rounding_mode(i, &env->ucf64.fp_status);
	217	}
	218
	219	i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
	220	set_float_exception_flags(i, &env->ucf64.fp_status);
	221	}
	222
eb23b556	223	float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
6e64da3c GX	224	{
	225	return float32_add(a, b, &env->ucf64.fp_status);
	226	}
	227
eb23b556	228	float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
6e64da3c GX	229	{
	230	return float64_add(a, b, &env->ucf64.fp_status);
	231	}
	232
eb23b556	233	float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
6e64da3c GX	234	{
	235	return float32_sub(a, b, &env->ucf64.fp_status);
	236	}
	237
eb23b556	238	float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
6e64da3c GX	239	{
	240	return float64_sub(a, b, &env->ucf64.fp_status);
	241	}
	242
eb23b556	243	float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
6e64da3c GX	244	{
	245	return float32_mul(a, b, &env->ucf64.fp_status);
	246	}
	247
eb23b556	248	float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
6e64da3c GX	249	{
	250	return float64_mul(a, b, &env->ucf64.fp_status);
	251	}
	252
eb23b556	253	float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
6e64da3c GX	254	{
	255	return float32_div(a, b, &env->ucf64.fp_status);
	256	}
	257
eb23b556	258	float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUniCore32State *env)
6e64da3c GX	259	{
	260	return float64_div(a, b, &env->ucf64.fp_status);
	261	}
	262
	263	float32 HELPER(ucf64_negs)(float32 a)
	264	{
	265	return float32_chs(a);
	266	}
	267
	268	float64 HELPER(ucf64_negd)(float64 a)
	269	{
	270	return float64_chs(a);
	271	}
	272
	273	float32 HELPER(ucf64_abss)(float32 a)
	274	{
	275	return float32_abs(a);
	276	}
	277
	278	float64 HELPER(ucf64_absd)(float64 a)
	279	{
	280	return float64_abs(a);
	281	}
	282
	283	/* XXX: check quiet/signaling case */
eb23b556	284	void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUUniCore32State *env)
6e64da3c GX	285	{
	286	int flag;
	287	flag = float32_compare_quiet(a, b, &env->ucf64.fp_status);
	288	env->CF = 0;
	289	switch (c & 0x7) {
	290	case 0: /* F */
	291	break;
	292	case 1: /* UN */
	293	if (flag == 2) {
	294	env->CF = 1;
	295	}
	296	break;
	297	case 2: /* EQ */
	298	if (flag == 0) {
	299	env->CF = 1;
	300	}
	301	break;
	302	case 3: /* UEQ */
	303	if ((flag == 0) \|\| (flag == 2)) {
	304	env->CF = 1;
	305	}
	306	break;
	307	case 4: /* OLT */
	308	if (flag == -1) {
	309	env->CF = 1;
	310	}
	311	break;
	312	case 5: /* ULT */
	313	if ((flag == -1) \|\| (flag == 2)) {
	314	env->CF = 1;
	315	}
	316	break;
	317	case 6: /* OLE */
	318	if ((flag == -1) \|\| (flag == 0)) {
	319	env->CF = 1;
	320	}
	321	break;
	322	case 7: /* ULE */
	323	if (flag != 1) {
	324	env->CF = 1;
	325	}
	326	break;
	327	}
	328	env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
	329	\| (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
	330	}
	331
eb23b556	332	void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c, CPUUniCore32State *env)
6e64da3c GX	333	{
	334	int flag;
	335	flag = float64_compare_quiet(a, b, &env->ucf64.fp_status);
	336	env->CF = 0;
	337	switch (c & 0x7) {
	338	case 0: /* F */
	339	break;
	340	case 1: /* UN */
	341	if (flag == 2) {
	342	env->CF = 1;
	343	}
	344	break;
	345	case 2: /* EQ */
	346	if (flag == 0) {
	347	env->CF = 1;
	348	}
	349	break;
	350	case 3: /* UEQ */
	351	if ((flag == 0) \|\| (flag == 2)) {
	352	env->CF = 1;
	353	}
	354	break;
	355	case 4: /* OLT */
	356	if (flag == -1) {
	357	env->CF = 1;
	358	}
	359	break;
	360	case 5: /* ULT */
	361	if ((flag == -1) \|\| (flag == 2)) {
	362	env->CF = 1;
	363	}
	364	break;
	365	case 6: /* OLE */
	366	if ((flag == -1) \|\| (flag == 0)) {
	367	env->CF = 1;
	368	}
	369	break;
	370	case 7: /* ULE */
	371	if (flag != 1) {
	372	env->CF = 1;
	373	}
	374	break;
	375	}
	376	env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
	377	\| (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
	378	}
	379
	380	/* Helper routines to perform bitwise copies between float and int. */
	381	static inline float32 ucf64_itos(uint32_t i)
	382	{
	383	union {
	384	uint32_t i;
	385	float32 s;
	386	} v;
	387
	388	v.i = i;
	389	return v.s;
	390	}
	391
	392	static inline uint32_t ucf64_stoi(float32 s)
	393	{
	394	union {
	395	uint32_t i;
	396	float32 s;
397	} v;
398
399	v.s = s;
400	return v.i;
401	}
402
403	static inline float64 ucf64_itod(uint64_t i)
404	{
405	union {
406	uint64_t i;
407	float64 d;
408	} v;
409
410	v.i = i;
411	return v.d;
412	}
413
414	static inline uint64_t ucf64_dtoi(float64 d)
415	{
416	union {
417	uint64_t i;
418	float64 d;
419	} v;
420
421	v.d = d;
422	return v.i;
423	}
424
425	/* Integer to float conversion. */
eb23b556	426	float32 HELPER(ucf64_si2sf)(float32 x, CPUUniCore32State *env)
6e64da3c GX	427	{
	428	return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status);
	429	}
	430
eb23b556	431	float64 HELPER(ucf64_si2df)(float32 x, CPUUniCore32State *env)
6e64da3c GX	432	{
	433	return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status);
	434	}
	435
	436	/* Float to integer conversion. */
eb23b556	437	float32 HELPER(ucf64_sf2si)(float32 x, CPUUniCore32State *env)
6e64da3c GX	438	{
	439	return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status));
	440	}
	441
eb23b556	442	float32 HELPER(ucf64_df2si)(float64 x, CPUUniCore32State *env)
6e64da3c GX	443	{
	444	return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));
	445	}
	446
	447	/* floating point conversion */
eb23b556	448	float64 HELPER(ucf64_sf2df)(float32 x, CPUUniCore32State *env)
6e64da3c GX	449	{
	450	return float32_to_float64(x, &env->ucf64.fp_status);
	451	}
	452
eb23b556	453	float32 HELPER(ucf64_df2sf)(float64 x, CPUUniCore32State *env)
6e64da3c GX	454	{
	455	return float64_to_float32(x, &env->ucf64.fp_status);
	456	}