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PowerPC 620 MMU do not have the same exact behavior as standard
[qemu.git] / target-ppc / cpu.h
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#if !defined (__CPU_PPC_H__)
21#define __CPU_PPC_H__
22
3fc6c082 23#include "config.h"
de270b3c 24#include <inttypes.h>
3fc6c082 25
a4f30719
JM		 26//#define PPC_EMULATE_32BITS_HYPV
27
76a66253 28#if defined (TARGET_PPC64)
3cd7d1dd 29/* PowerPC 64 definitions */
76a66253 30typedef uint64_t ppc_gpr_t;
0487d6a8 31#define TARGET_GPR_BITS 64
d9d7210c 32#define TARGET_LONG_BITS 64
76a66253 33#define REGX "%016" PRIx64
35cdaad6 34#define TARGET_PAGE_BITS 12
3cd7d1dd
JM		 35
36#else /* defined (TARGET_PPC64) */
37/* PowerPC 32 definitions */
d9d7210c
JM		 38#if (HOST_LONG_BITS >= 64)
39/* When using 64 bits temporary registers,
40 * we can use 64 bits GPR with no extra cost
3cd7d1dd 41 * It's even an optimization as this will prevent
d9d7210c
JM		 42 * the compiler to do unuseful masking in the micro-ops.
43 */
44typedef uint64_t ppc_gpr_t;
45#define TARGET_GPR_BITS 64
71c8b8fd 46#define REGX "%08" PRIx64
3cd7d1dd 47#else /* (HOST_LONG_BITS >= 64) */
76a66253 48typedef uint32_t ppc_gpr_t;
0487d6a8 49#define TARGET_GPR_BITS 32
71c8b8fd 50#define REGX "%08" PRIx32
3cd7d1dd
JM		 51#endif /* (HOST_LONG_BITS >= 64) */
52
d9d7210c 53#define TARGET_LONG_BITS 32
3cd7d1dd
JM		 54
55#if defined(TARGET_PPCEMB)
56/* Specific definitions for PowerPC embedded */
57/* BookE have 36 bits physical address space */
58#define TARGET_PHYS_ADDR_BITS 64
59#if defined(CONFIG_USER_ONLY)
60/* It looks like a lot of Linux programs assume page size
61 * is 4kB long. This is evil, but we have to deal with it...
62 */
35cdaad6 63#define TARGET_PAGE_BITS 12
3cd7d1dd
JM		 64#else /* defined(CONFIG_USER_ONLY) */
65/* Pages can be 1 kB small */
66#define TARGET_PAGE_BITS 10
67#endif /* defined(CONFIG_USER_ONLY) */
68#else /* defined(TARGET_PPCEMB) */
69/* "standard" PowerPC 32 definitions */
70#define TARGET_PAGE_BITS 12
71#endif /* defined(TARGET_PPCEMB) */
72
73#endif /* defined (TARGET_PPC64) */
3cf1e035 74
79aceca5
FB		 75#include "cpu-defs.h"
76
e96efcfc
JM		 77#define ADDRX TARGET_FMT_lx
78#define PADDRX TARGET_FMT_plx
79
79aceca5
FB		 80#include <setjmp.h>
81
4ecc3190
FB		 82#include "softfloat.h"
83
1fddef4b
FB		 84#define TARGET_HAS_ICE 1
85
76a66253
JM		 86#if defined (TARGET_PPC64)
87#define ELF_MACHINE EM_PPC64
88#else
89#define ELF_MACHINE EM_PPC
90#endif
9042c0e2 91
3fc6c082 92/*****************************************************************************/
a750fc0b 93/* MMU model */
7820dbf3
JM		 94typedef enum powerpc_mmu_t powerpc_mmu_t;
95enum powerpc_mmu_t {
add78955 96 POWERPC_MMU_UNKNOWN = 0x00000000,
a750fc0b 97 /* Standard 32 bits PowerPC MMU */
add78955 98 POWERPC_MMU_32B = 0x00000001,
a750fc0b 99 /* PowerPC 6xx MMU with software TLB */
add78955 100 POWERPC_MMU_SOFT_6xx = 0x00000002,
a750fc0b 101 /* PowerPC 74xx MMU with software TLB */
add78955 102 POWERPC_MMU_SOFT_74xx = 0x00000003,
a750fc0b 103 /* PowerPC 4xx MMU with software TLB */
add78955 104 POWERPC_MMU_SOFT_4xx = 0x00000004,
a750fc0b 105 /* PowerPC 4xx MMU with software TLB and zones protections */
add78955 106 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
b4095fed 107 /* PowerPC MMU in real mode only */
add78955 108 POWERPC_MMU_REAL = 0x00000006,
b4095fed 109 /* Freescale MPC8xx MMU model */
add78955 110 POWERPC_MMU_MPC8xx = 0x00000007,
a750fc0b 111 /* BookE MMU model */
add78955 112 POWERPC_MMU_BOOKE = 0x00000008,
a750fc0b 113 /* BookE FSL MMU model */
add78955 114 POWERPC_MMU_BOOKE_FSL = 0x00000009,
faadf50e 115 /* PowerPC 601 MMU model (specific BATs format) */
add78955 116 POWERPC_MMU_601 = 0x0000000A,
00af685f 117#if defined(TARGET_PPC64)
add78955 118#define POWERPC_MMU_64 0x00010000
12de9a39 119 /* 64 bits PowerPC MMU */
add78955
JM		 120 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
121 /* 620 variant (no segment exceptions) */
122 POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
00af685f 123#endif /* defined(TARGET_PPC64) */
3fc6c082
FB		 124};
125
126/*****************************************************************************/
a750fc0b 127/* Exception model */
7820dbf3
JM		 128typedef enum powerpc_excp_t powerpc_excp_t;
129enum powerpc_excp_t {
a750fc0b 130 POWERPC_EXCP_UNKNOWN = 0,
3fc6c082 131 /* Standard PowerPC exception model */
a750fc0b 132 POWERPC_EXCP_STD,
2662a059 133 /* PowerPC 40x exception model */
a750fc0b 134 POWERPC_EXCP_40x,
2662a059 135 /* PowerPC 601 exception model */
a750fc0b 136 POWERPC_EXCP_601,
2662a059 137 /* PowerPC 602 exception model */
a750fc0b 138 POWERPC_EXCP_602,
2662a059 139 /* PowerPC 603 exception model */
a750fc0b
JM		 140 POWERPC_EXCP_603,
141 /* PowerPC 603e exception model */
142 POWERPC_EXCP_603E,
143 /* PowerPC G2 exception model */
144 POWERPC_EXCP_G2,
2662a059 145 /* PowerPC 604 exception model */
a750fc0b 146 POWERPC_EXCP_604,
2662a059 147 /* PowerPC 7x0 exception model */
a750fc0b 148 POWERPC_EXCP_7x0,
2662a059 149 /* PowerPC 7x5 exception model */
a750fc0b 150 POWERPC_EXCP_7x5,
2662a059 151 /* PowerPC 74xx exception model */
a750fc0b 152 POWERPC_EXCP_74xx,
2662a059 153 /* BookE exception model */
a750fc0b 154 POWERPC_EXCP_BOOKE,
00af685f
JM		 155#if defined(TARGET_PPC64)
156 /* PowerPC 970 exception model */
157 POWERPC_EXCP_970,
158#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 159};
160
e1833e1f
JM		 161/*****************************************************************************/
162/* Exception vectors definitions */
163enum {
164 POWERPC_EXCP_NONE = -1,
165 /* The 64 first entries are used by the PowerPC embedded specification */
166 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
167 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
168 POWERPC_EXCP_DSI = 2, /* Data storage exception */
169 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
170 POWERPC_EXCP_EXTERNAL = 4, /* External input */
171 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
172 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
173 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
174 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
175 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
176 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
177 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
178 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
b4095fed
JM		 179 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
180 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
e1833e1f
JM		 181 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
182 /* Vectors 16 to 31 are reserved */
e1833e1f
JM		 183 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
184 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
185 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
186 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
187 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
188 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
e1833e1f
JM		 189 /* Vectors 38 to 63 are reserved */
190 /* Exceptions defined in the PowerPC server specification */
191 POWERPC_EXCP_RESET = 64, /* System reset exception */
e1833e1f
JM		 192 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
193 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
e1833e1f 194 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
e1833e1f 195 POWERPC_EXCP_TRACE = 68, /* Trace exception */
e1833e1f
JM		 196 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
197 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
198 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
199 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
e1833e1f
JM		 200 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
201 /* 40x specific exceptions */
202 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
203 /* 601 specific exceptions */
204 POWERPC_EXCP_IO = 75, /* IO error exception */
205 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
206 /* 602 specific exceptions */
207 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
208 /* 602/603 specific exceptions */
b4095fed 209 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
e1833e1f
JM		 210 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
211 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
212 /* Exceptions available on most PowerPC */
213 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
b4095fed
JM		 214 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
215 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
216 POWERPC_EXCP_SMI = 84, /* System management interrupt */
217 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
e1833e1f 218 /* 7xx/74xx specific exceptions */
b4095fed 219 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
e1833e1f 220 /* 74xx specific exceptions */
b4095fed 221 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
e1833e1f 222 /* 970FX specific exceptions */
b4095fed
JM		 223 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
224 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
225 /* Freescale embeded cores specific exceptions */
226 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
227 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
228 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
229 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
e1833e1f
JM		 230 /* EOL */
231 POWERPC_EXCP_NB = 96,
232 /* Qemu exceptions: used internally during code translation */
233 POWERPC_EXCP_STOP = 0x200, /* stop translation */
234 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
235 /* Qemu exceptions: special cases we want to stop translation */
236 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
237 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
238};
239
e1833e1f
JM		 240/* Exceptions error codes */
241enum {
242 /* Exception subtypes for POWERPC_EXCP_ALIGN */
243 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
244 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
245 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
246 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
247 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
248 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
249 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
250 /* FP exceptions */
251 POWERPC_EXCP_FP = 0x10,
252 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
253 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
254 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
255 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
7c58044c 256 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
e1833e1f
JM		 257 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
258 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
259 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
260 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
261 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
262 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
263 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
264 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
265 /* Invalid instruction */
266 POWERPC_EXCP_INVAL = 0x20,
267 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
268 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
269 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
270 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
271 /* Privileged instruction */
272 POWERPC_EXCP_PRIV = 0x30,
273 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
274 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
275 /* Trap */
276 POWERPC_EXCP_TRAP = 0x40,
277};
278
a750fc0b
JM		 279/*****************************************************************************/
280/* Input pins model */
7820dbf3
JM		 281typedef enum powerpc_input_t powerpc_input_t;
282enum powerpc_input_t {
a750fc0b 283 PPC_FLAGS_INPUT_UNKNOWN = 0,
2662a059 284 /* PowerPC 6xx bus */
a750fc0b 285 PPC_FLAGS_INPUT_6xx,
2662a059 286 /* BookE bus */
a750fc0b
JM		 287 PPC_FLAGS_INPUT_BookE,
288 /* PowerPC 405 bus */
289 PPC_FLAGS_INPUT_405,
2662a059 290 /* PowerPC 970 bus */
a750fc0b
JM		 291 PPC_FLAGS_INPUT_970,
292 /* PowerPC 401 bus */
293 PPC_FLAGS_INPUT_401,
b4095fed
JM		 294 /* Freescale RCPU bus */
295 PPC_FLAGS_INPUT_RCPU,
3fc6c082
FB		 296};
297
a750fc0b 298#define PPC_INPUT(env) (env->bus_model)
3fc6c082 299
be147d08 300/*****************************************************************************/
3fc6c082 301typedef struct ppc_def_t ppc_def_t;
a750fc0b 302typedef struct opc_handler_t opc_handler_t;
79aceca5 303
3fc6c082
FB		 304/*****************************************************************************/
305/* Types used to describe some PowerPC registers */
306typedef struct CPUPPCState CPUPPCState;
9fddaa0c 307typedef struct ppc_tb_t ppc_tb_t;
3fc6c082
FB		 308typedef struct ppc_spr_t ppc_spr_t;
309typedef struct ppc_dcr_t ppc_dcr_t;
a9d9eb8f 310typedef union ppc_avr_t ppc_avr_t;
1d0a48fb 311typedef union ppc_tlb_t ppc_tlb_t;
76a66253 312
3fc6c082
FB		 313/* SPR access micro-ops generations callbacks */
314struct ppc_spr_t {
315 void (*uea_read)(void *opaque, int spr_num);
316 void (*uea_write)(void *opaque, int spr_num);
76a66253 317#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 318 void (*oea_read)(void *opaque, int spr_num);
319 void (*oea_write)(void *opaque, int spr_num);
be147d08
JM		 320 void (*hea_read)(void *opaque, int spr_num);
321 void (*hea_write)(void *opaque, int spr_num);
76a66253 322#endif
3fc6c082
FB		 323 const unsigned char *name;
324};
325
326/* Altivec registers (128 bits) */
a9d9eb8f
JM		 327union ppc_avr_t {
328 uint8_t u8[16];
329 uint16_t u16[8];
330 uint32_t u32[4];
331 uint64_t u64[2];
3fc6c082 332};
9fddaa0c 333
3fc6c082 334/* Software TLB cache */
1d0a48fb
JM		 335typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
336struct ppc6xx_tlb_t {
76a66253
JM		 337 target_ulong pte0;
338 target_ulong pte1;
339 target_ulong EPN;
1d0a48fb
JM		 340};
341
342typedef struct ppcemb_tlb_t ppcemb_tlb_t;
343struct ppcemb_tlb_t {
c55e9aef 344 target_phys_addr_t RPN;
1d0a48fb 345 target_ulong EPN;
76a66253 346 target_ulong PID;
c55e9aef
JM		 347 target_ulong size;
348 uint32_t prot;
349 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 350};
351
352union ppc_tlb_t {
353 ppc6xx_tlb_t tlb6;
354 ppcemb_tlb_t tlbe;
3fc6c082
FB		 355};
356
357/*****************************************************************************/
358/* Machine state register bits definition */
76a66253 359#define MSR_SF 63 /* Sixty-four-bit mode hflags */
3fc6c082 360#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
a4f30719 361#define MSR_SHV 60 /* hypervisor state hflags */
363be49c
JM		 362#define MSR_CM 31 /* Computation mode for BookE hflags */
363#define MSR_ICM 30 /* Interrupt computation mode for BookE */
a4f30719 364#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
363be49c 365#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
d26bfc9a
JM		 366#define MSR_VR 25 /* altivec available x hflags */
367#define MSR_SPE 25 /* SPE enable for BookE x hflags */
76a66253
JM		 368#define MSR_AP 23 /* Access privilege state on 602 hflags */
369#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082 370#define MSR_KEY 19 /* key bit on 603e */
25ba3a68 371#define MSR_POW 18 /* Power management */
d26bfc9a
JM		 372#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
373#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
3fc6c082
FB		 374#define MSR_ILE 16 /* Interrupt little-endian mode */
375#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 376#define MSR_PR 14 /* Problem state hflags */
377#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 378#define MSR_ME 12 /* Machine check interrupt enable */
76a66253 379#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
d26bfc9a
JM		 380#define MSR_SE 10 /* Single-step trace enable x hflags */
381#define MSR_DWE 10 /* Debug wait enable on 405 x */
382#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
383#define MSR_BE 9 /* Branch trace enable x hflags */
384#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
76a66253 385#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082 386#define MSR_AL 7 /* AL bit on POWER */
0411a972 387#define MSR_EP 6 /* Exception prefix on 601 */
3fc6c082 388#define MSR_IR 5 /* Instruction relocate */
3fc6c082 389#define MSR_DR 4 /* Data relocate */
25ba3a68 390#define MSR_PE 3 /* Protection enable on 403 */
d26bfc9a
JM		 391#define MSR_PX 2 /* Protection exclusive on 403 x */
392#define MSR_PMM 2 /* Performance monitor mark on POWER x */
393#define MSR_RI 1 /* Recoverable interrupt 1 */
394#define MSR_LE 0 /* Little-endian mode 1 hflags */
0411a972
JM		 395
396#define msr_sf ((env->msr >> MSR_SF) & 1)
397#define msr_isf ((env->msr >> MSR_ISF) & 1)
a4f30719 398#define msr_shv ((env->msr >> MSR_SHV) & 1)
0411a972
JM		 399#define msr_cm ((env->msr >> MSR_CM) & 1)
400#define msr_icm ((env->msr >> MSR_ICM) & 1)
a4f30719 401#define msr_thv ((env->msr >> MSR_THV) & 1)
0411a972
JM		 402#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
403#define msr_vr ((env->msr >> MSR_VR) & 1)
404#define msr_spe ((env->msr >> MSR_SE) & 1)
405#define msr_ap ((env->msr >> MSR_AP) & 1)
406#define msr_sa ((env->msr >> MSR_SA) & 1)
407#define msr_key ((env->msr >> MSR_KEY) & 1)
408#define msr_pow ((env->msr >> MSR_POW) & 1)
409#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
410#define msr_ce ((env->msr >> MSR_CE) & 1)
411#define msr_ile ((env->msr >> MSR_ILE) & 1)
412#define msr_ee ((env->msr >> MSR_EE) & 1)
413#define msr_pr ((env->msr >> MSR_PR) & 1)
414#define msr_fp ((env->msr >> MSR_FP) & 1)
415#define msr_me ((env->msr >> MSR_ME) & 1)
416#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
417#define msr_se ((env->msr >> MSR_SE) & 1)
418#define msr_dwe ((env->msr >> MSR_DWE) & 1)
419#define msr_uble ((env->msr >> MSR_UBLE) & 1)
420#define msr_be ((env->msr >> MSR_BE) & 1)
421#define msr_de ((env->msr >> MSR_DE) & 1)
422#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
423#define msr_al ((env->msr >> MSR_AL) & 1)
424#define msr_ep ((env->msr >> MSR_EP) & 1)
425#define msr_ir ((env->msr >> MSR_IR) & 1)
426#define msr_dr ((env->msr >> MSR_DR) & 1)
427#define msr_pe ((env->msr >> MSR_PE) & 1)
428#define msr_px ((env->msr >> MSR_PX) & 1)
429#define msr_pmm ((env->msr >> MSR_PMM) & 1)
430#define msr_ri ((env->msr >> MSR_RI) & 1)
431#define msr_le ((env->msr >> MSR_LE) & 1)
a4f30719
JM		 432/* Hypervisor bit is more specific */
433#if defined(TARGET_PPC64)
434#define MSR_HVB (1ULL << MSR_SHV)
435#define msr_hv msr_shv
436#else
437#if defined(PPC_EMULATE_32BITS_HYPV)
438#define MSR_HVB (1ULL << MSR_THV)
439#define msr_hv msr_thv
a4f30719
JM		 440#else
441#define MSR_HVB (0ULL)
442#define msr_hv (0)
443#endif
444#endif
79aceca5 445
d26bfc9a 446enum {
4018bae9 447 POWERPC_FLAG_NONE = 0x00000000,
d26bfc9a 448 /* Flag for MSR bit 25 signification (VRE/SPE) */
4018bae9
JM		 449 POWERPC_FLAG_SPE = 0x00000001,
450 POWERPC_FLAG_VRE = 0x00000002,
d26bfc9a 451 /* Flag for MSR bit 17 signification (TGPR/CE) */
4018bae9
JM		 452 POWERPC_FLAG_TGPR = 0x00000004,
453 POWERPC_FLAG_CE = 0x00000008,
d26bfc9a 454 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
4018bae9
JM		 455 POWERPC_FLAG_SE = 0x00000010,
456 POWERPC_FLAG_DWE = 0x00000020,
457 POWERPC_FLAG_UBLE = 0x00000040,
d26bfc9a 458 /* Flag for MSR bit 9 signification (BE/DE) */
4018bae9
JM		 459 POWERPC_FLAG_BE = 0x00000080,
460 POWERPC_FLAG_DE = 0x00000100,
a4f30719 461 /* Flag for MSR bit 2 signification (PX/PMM) */
4018bae9
JM		 462 POWERPC_FLAG_PX = 0x00000200,
463 POWERPC_FLAG_PMM = 0x00000400,
464 /* Flag for special features */
465 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
466 POWERPC_FLAG_RTC_CLK = 0x00010000,
467 POWERPC_FLAG_BUS_CLK = 0x00020000,
d26bfc9a
JM		 468};
469
7c58044c
JM		 470/*****************************************************************************/
471/* Floating point status and control register */
472#define FPSCR_FX 31 /* Floating-point exception summary */
473#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
474#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
475#define FPSCR_OX 28 /* Floating-point overflow exception */
476#define FPSCR_UX 27 /* Floating-point underflow exception */
477#define FPSCR_ZX 26 /* Floating-point zero divide exception */
478#define FPSCR_XX 25 /* Floating-point inexact exception */
479#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
480#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
481#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
482#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
483#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
484#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
485#define FPSCR_FR 18 /* Floating-point fraction rounded */
486#define FPSCR_FI 17 /* Floating-point fraction inexact */
487#define FPSCR_C 16 /* Floating-point result class descriptor */
488#define FPSCR_FL 15 /* Floating-point less than or negative */
489#define FPSCR_FG 14 /* Floating-point greater than or negative */
490#define FPSCR_FE 13 /* Floating-point equal or zero */
491#define FPSCR_FU 12 /* Floating-point unordered or NaN */
492#define FPSCR_FPCC 12 /* Floating-point condition code */
493#define FPSCR_FPRF 12 /* Floating-point result flags */
494#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
495#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
496#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
497#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
498#define FPSCR_OE 6 /* Floating-point overflow exception enable */
499#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
500#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
501#define FPSCR_XE 3 /* Floating-point inexact exception enable */
502#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
503#define FPSCR_RN1 1
504#define FPSCR_RN 0 /* Floating-point rounding control */
505#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
506#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
507#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
508#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
509#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
510#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
511#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
512#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
513#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
514#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
515#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
516#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
517#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
518#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
519#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
520#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
521#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
522#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
523#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
524#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
525#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
526#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
527#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
528/* Invalid operation exception summary */
529#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
530 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
531 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
532 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
533 (1 << FPSCR_VXCVI)))
534/* exception summary */
535#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
536/* enabled exception summary */
537#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
538 0x1F)
539
540/*****************************************************************************/
541/* The whole PowerPC CPU context */
6ebbf390 542#define NB_MMU_MODES 3
6ebbf390 543
3fc6c082
FB		 544struct CPUPPCState {
545 /* First are the most commonly used resources
546 * during translated code execution
547 */
57c26279 548#if (HOST_LONG_BITS == 32)
3fc6c082 549 /* temporary fixed-point registers
57c26279 550 * used to emulate 64 bits registers on 32 bits hosts
5fafdf24 551 */
57c26279 552 uint64_t t0, t1, t2;
3fc6c082 553#endif
a9d9eb8f 554 ppc_avr_t avr0, avr1, avr2;
d9bce9d9 555
79aceca5 556 /* general purpose registers */
76a66253 557 ppc_gpr_t gpr[32];
65d6c0f3 558#if !defined(TARGET_PPC64)
3cd7d1dd
JM		 559 /* Storage for GPR MSB, used by the SPE extension */
560 ppc_gpr_t gprh[32];
561#endif
3fc6c082
FB		 562 /* LR */
563 target_ulong lr;
564 /* CTR */
565 target_ulong ctr;
566 /* condition register */
567 uint8_t crf[8];
79aceca5 568 /* XER */
3fc6c082
FB		 569 /* XXX: We use only 5 fields, but we want to keep the structure aligned */
570 uint8_t xer[8];
79aceca5 571 /* Reservation address */
3fc6c082
FB		 572 target_ulong reserve;
573
574 /* Those ones are used in supervisor mode only */
79aceca5 575 /* machine state register */
0411a972 576 target_ulong msr;
3fc6c082 577 /* temporary general purpose registers */
76a66253 578 ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 579
580 /* Floating point execution context */
76a66253 581 /* temporary float registers */
4ecc3190
FB		 582 float64 ft0;
583 float64 ft1;
584 float64 ft2;
585 float_status fp_status;
3fc6c082
FB		 586 /* floating point registers */
587 float64 fpr[32];
588 /* floating point status and control register */
7c58044c 589 uint32_t fpscr;
4ecc3190 590
a316d335
FB		 591 CPU_COMMON
592
50443c98
FB		 593 int halted; /* TRUE if the CPU is in suspend state */
594
ac9eb073
FB		 595 int access_type; /* when a memory exception occurs, the access
596 type is stored here */
a541f297 597
f2e63a42
JM		 598 /* MMU context - only relevant for full system emulation */
599#if !defined(CONFIG_USER_ONLY)
600#if defined(TARGET_PPC64)
3fc6c082
FB		 601 /* Address space register */
602 target_ulong asr;
f2e63a42
JM		 603 /* PowerPC 64 SLB area */
604 int slb_nr;
605#endif
3fc6c082
FB		 606 /* segment registers */
607 target_ulong sdr1;
608 target_ulong sr[16];
609 /* BATs */
610 int nb_BATs;
611 target_ulong DBAT[2][8];
612 target_ulong IBAT[2][8];
f2e63a42
JM		 613 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
614 int nb_tlb; /* Total number of TLB */
615 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
616 int nb_ways; /* Number of ways in the TLB set */
617 int last_way; /* Last used way used to allocate TLB in a LRU way */
618 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
619 int nb_pids; /* Number of available PID registers */
620 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
621 /* 403 dedicated access protection registers */
622 target_ulong pb[4];
623#endif
9fddaa0c 624
3fc6c082
FB		 625 /* Other registers */
626 /* Special purpose registers */
627 target_ulong spr[1024];
f2e63a42 628 ppc_spr_t spr_cb[1024];
3fc6c082
FB		 629 /* Altivec registers */
630 ppc_avr_t avr[32];
631 uint32_t vscr;
d9bce9d9
JM		 632 /* SPE registers */
633 ppc_gpr_t spe_acc;
0487d6a8 634 float_status spe_status;
d9bce9d9 635 uint32_t spe_fscr;
3fc6c082
FB		 636
637 /* Internal devices resources */
9fddaa0c
FB		 638 /* Time base and decrementer */
639 ppc_tb_t *tb_env;
3fc6c082 640 /* Device control registers */
3fc6c082
FB		 641 ppc_dcr_t *dcr_env;
642
d63001d1
JM		 643 int dcache_line_size;
644 int icache_line_size;
645
3fc6c082
FB		 646 /* Those resources are used during exception processing */
647 /* CPU model definition */
a750fc0b 648 target_ulong msr_mask;
7820dbf3
JM		 649 powerpc_mmu_t mmu_model;
650 powerpc_excp_t excp_model;
651 powerpc_input_t bus_model;
237c0af0 652 int bfd_mach;
3fc6c082
FB		 653 uint32_t flags;
654
655 int exception_index;
656 int error_code;
657 int interrupt_request;
47103572 658 uint32_t pending_interrupts;
e9df014c
JM		 659#if !defined(CONFIG_USER_ONLY)
660 /* This is the IRQ controller, which is implementation dependant
661 * and only relevant when emulating a complete machine.
662 */
663 uint32_t irq_input_state;
664 void **irq_inputs;
e1833e1f
JM		 665 /* Exception vectors */
666 target_ulong excp_vectors[POWERPC_EXCP_NB];
667 target_ulong excp_prefix;
668 target_ulong ivor_mask;
669 target_ulong ivpr_mask;
d63001d1 670 target_ulong hreset_vector;
e9df014c 671#endif
3fc6c082
FB		 672
673 /* Those resources are used only during code translation */
674 /* Next instruction pointer */
675 target_ulong nip;
f2e63a42 676
3fc6c082
FB		 677 /* opcode handlers */
678 opc_handler_t *opcodes[0x40];
679
680 /* Those resources are used only in Qemu core */
681 jmp_buf jmp_env;
682 int user_mode_only; /* user mode only simulation */
056401ea
JM		 683 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
684 target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
6ebbf390 685 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
3fc6c082 686
9fddaa0c
FB		 687 /* Power management */
688 int power_mode;
cd346349 689 int (*check_pow)(CPUPPCState *env);
a541f297 690
6d506e6d
FB		 691 /* temporary hack to handle OSI calls (only used if non NULL) */
692 int (*osi_call)(struct CPUPPCState *env);
3fc6c082 693};
79aceca5 694
76a66253
JM		 695/* Context used internally during MMU translations */
696typedef struct mmu_ctx_t mmu_ctx_t;
697struct mmu_ctx_t {
698 target_phys_addr_t raddr; /* Real address */
699 int prot; /* Protection bits */
700 target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
701 target_ulong ptem; /* Virtual segment ID | API */
702 int key; /* Access key */
b227a8e9 703 int nx; /* Non-execute area */
76a66253
JM		 704};
705
3fc6c082 706/*****************************************************************************/
aaed909a 707CPUPPCState *cpu_ppc_init (const char *cpu_model);
36081602
JM		 708int cpu_ppc_exec (CPUPPCState *s);
709void cpu_ppc_close (CPUPPCState *s);
79aceca5
FB		 710/* you can call this signal handler from your SIGBUS and SIGSEGV
711 signal handlers to inform the virtual CPU of exceptions. non zero
712 is returned if the signal was handled by the virtual CPU. */
36081602
JM		 713int cpu_ppc_signal_handler (int host_signum, void *pinfo,
714 void *puc);
79aceca5 715
a541f297 716void do_interrupt (CPUPPCState *env);
e9df014c 717void ppc_hw_interrupt (CPUPPCState *env);
36081602 718void cpu_loop_exit (void);
a541f297 719
9a64fbe4 720void dump_stack (CPUPPCState *env);
a541f297 721
76a66253 722#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 723target_ulong do_load_ibatu (CPUPPCState *env, int nr);
724target_ulong do_load_ibatl (CPUPPCState *env, int nr);
725void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
726void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
727target_ulong do_load_dbatu (CPUPPCState *env, int nr);
728target_ulong do_load_dbatl (CPUPPCState *env, int nr);
729void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
730void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
056401ea
JM		 731void do_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
732void do_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
3fc6c082
FB		 733target_ulong do_load_sdr1 (CPUPPCState *env);
734void do_store_sdr1 (CPUPPCState *env, target_ulong value);
d9bce9d9
JM		 735#if defined(TARGET_PPC64)
736target_ulong ppc_load_asr (CPUPPCState *env);
737void ppc_store_asr (CPUPPCState *env, target_ulong value);
12de9a39
JM		 738target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
739void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs);
740#endif /* defined(TARGET_PPC64) */
741#if 0 // Unused
3fc6c082 742target_ulong do_load_sr (CPUPPCState *env, int srnum);
76a66253 743#endif
12de9a39
JM		 744void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
745#endif /* !defined(CONFIG_USER_ONLY) */
bfa1e5cf
JM		 746target_ulong ppc_load_xer (CPUPPCState *env);
747void ppc_store_xer (CPUPPCState *env, target_ulong value);
0411a972 748void ppc_store_msr (CPUPPCState *env, target_ulong value);
3fc6c082 749
0a032cbe 750void cpu_ppc_reset (void *opaque);
a541f297 751
3fc6c082 752void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
aaed909a
FB		 753
754const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name);
aaed909a 755int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
85c4adf6 756
9fddaa0c
FB		 757/* Time-base and decrementer management */
758#ifndef NO_CPU_IO_DEFS
759uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
760uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
761void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
762void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
a062e36c
JM		 763uint32_t cpu_ppc_load_atbl (CPUPPCState *env);
764uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
765void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
766void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
9fddaa0c
FB		 767uint32_t cpu_ppc_load_decr (CPUPPCState *env);
768void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
58a7d328
JM		 769uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
770void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
771uint64_t cpu_ppc_load_purr (CPUPPCState *env);
772void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
d9bce9d9
JM		 773uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
774uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
775#if !defined(CONFIG_USER_ONLY)
776void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
777void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
778target_ulong load_40x_pit (CPUPPCState *env);
779void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 780void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 781void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM		 782void store_booke_tcr (CPUPPCState *env, target_ulong val);
783void store_booke_tsr (CPUPPCState *env, target_ulong val);
0a032cbe 784void ppc_tlb_invalidate_all (CPUPPCState *env);
daf4f96e
JM		 785void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
786#if defined(TARGET_PPC64)
787void ppc_slb_invalidate_all (CPUPPCState *env);
788void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
789#endif
36081602 790int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
d9bce9d9 791#endif
9fddaa0c 792#endif
79aceca5 793
2e719ba3
JM		 794/* Device control registers */
795int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
796int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
797
9467d44c
TS		 798#define CPUState CPUPPCState
799#define cpu_init cpu_ppc_init
800#define cpu_exec cpu_ppc_exec
801#define cpu_gen_code cpu_ppc_gen_code
802#define cpu_signal_handler cpu_ppc_signal_handler
c732abe2 803#define cpu_list ppc_cpu_list
9467d44c 804
6ebbf390
JM		 805/* MMU modes definitions */
806#define MMU_MODE0_SUFFIX _user
807#define MMU_MODE1_SUFFIX _kernel
6ebbf390 808#define MMU_MODE2_SUFFIX _hypv
6ebbf390
JM		 809#define MMU_USER_IDX 0
810static inline int cpu_mmu_index (CPUState *env)
811{
812 return env->mmu_idx;
813}
814
79aceca5
FB		 815#include "cpu-all.h"
816
3fc6c082
FB		 817/*****************************************************************************/
818/* Registers definitions */
79aceca5
FB		 819#define XER_SO 31
820#define XER_OV 30
821#define XER_CA 29
3fc6c082 822#define XER_CMP 8
36081602 823#define XER_BC 0
3fc6c082
FB		 824#define xer_so env->xer[4]
825#define xer_ov env->xer[6]
826#define xer_ca env->xer[2]
827#define xer_cmp env->xer[1]
36081602 828#define xer_bc env->xer[0]
79aceca5 829
3fc6c082 830/* SPR definitions */
80d11f44
JM		 831#define SPR_MQ (0x000)
832#define SPR_XER (0x001)
833#define SPR_601_VRTCU (0x004)
834#define SPR_601_VRTCL (0x005)
835#define SPR_601_UDECR (0x006)
836#define SPR_LR (0x008)
837#define SPR_CTR (0x009)
838#define SPR_DSISR (0x012)
839#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
840#define SPR_601_RTCU (0x014)
841#define SPR_601_RTCL (0x015)
842#define SPR_DECR (0x016)
843#define SPR_SDR1 (0x019)
844#define SPR_SRR0 (0x01A)
845#define SPR_SRR1 (0x01B)
846#define SPR_AMR (0x01D)
847#define SPR_BOOKE_PID (0x030)
848#define SPR_BOOKE_DECAR (0x036)
849#define SPR_BOOKE_CSRR0 (0x03A)
850#define SPR_BOOKE_CSRR1 (0x03B)
851#define SPR_BOOKE_DEAR (0x03D)
852#define SPR_BOOKE_ESR (0x03E)
853#define SPR_BOOKE_IVPR (0x03F)
854#define SPR_MPC_EIE (0x050)
855#define SPR_MPC_EID (0x051)
856#define SPR_MPC_NRI (0x052)
857#define SPR_CTRL (0x088)
858#define SPR_MPC_CMPA (0x090)
859#define SPR_MPC_CMPB (0x091)
860#define SPR_MPC_CMPC (0x092)
861#define SPR_MPC_CMPD (0x093)
862#define SPR_MPC_ECR (0x094)
863#define SPR_MPC_DER (0x095)
864#define SPR_MPC_COUNTA (0x096)
865#define SPR_MPC_COUNTB (0x097)
866#define SPR_UCTRL (0x098)
867#define SPR_MPC_CMPE (0x098)
868#define SPR_MPC_CMPF (0x099)
869#define SPR_MPC_CMPG (0x09A)
870#define SPR_MPC_CMPH (0x09B)
871#define SPR_MPC_LCTRL1 (0x09C)
872#define SPR_MPC_LCTRL2 (0x09D)
873#define SPR_MPC_ICTRL (0x09E)
874#define SPR_MPC_BAR (0x09F)
875#define SPR_VRSAVE (0x100)
876#define SPR_USPRG0 (0x100)
877#define SPR_USPRG1 (0x101)
878#define SPR_USPRG2 (0x102)
879#define SPR_USPRG3 (0x103)
880#define SPR_USPRG4 (0x104)
881#define SPR_USPRG5 (0x105)
882#define SPR_USPRG6 (0x106)
883#define SPR_USPRG7 (0x107)
884#define SPR_VTBL (0x10C)
885#define SPR_VTBU (0x10D)
886#define SPR_SPRG0 (0x110)
887#define SPR_SPRG1 (0x111)
888#define SPR_SPRG2 (0x112)
889#define SPR_SPRG3 (0x113)
890#define SPR_SPRG4 (0x114)
891#define SPR_SCOMC (0x114)
892#define SPR_SPRG5 (0x115)
893#define SPR_SCOMD (0x115)
894#define SPR_SPRG6 (0x116)
895#define SPR_SPRG7 (0x117)
896#define SPR_ASR (0x118)
897#define SPR_EAR (0x11A)
898#define SPR_TBL (0x11C)
899#define SPR_TBU (0x11D)
900#define SPR_TBU40 (0x11E)
901#define SPR_SVR (0x11E)
902#define SPR_BOOKE_PIR (0x11E)
903#define SPR_PVR (0x11F)
904#define SPR_HSPRG0 (0x130)
905#define SPR_BOOKE_DBSR (0x130)
906#define SPR_HSPRG1 (0x131)
907#define SPR_HDSISR (0x132)
908#define SPR_HDAR (0x133)
909#define SPR_BOOKE_DBCR0 (0x134)
910#define SPR_IBCR (0x135)
911#define SPR_PURR (0x135)
912#define SPR_BOOKE_DBCR1 (0x135)
913#define SPR_DBCR (0x136)
914#define SPR_HDEC (0x136)
915#define SPR_BOOKE_DBCR2 (0x136)
916#define SPR_HIOR (0x137)
917#define SPR_MBAR (0x137)
918#define SPR_RMOR (0x138)
919#define SPR_BOOKE_IAC1 (0x138)
920#define SPR_HRMOR (0x139)
921#define SPR_BOOKE_IAC2 (0x139)
922#define SPR_HSRR0 (0x13A)
923#define SPR_BOOKE_IAC3 (0x13A)
924#define SPR_HSRR1 (0x13B)
925#define SPR_BOOKE_IAC4 (0x13B)
926#define SPR_LPCR (0x13C)
927#define SPR_BOOKE_DAC1 (0x13C)
928#define SPR_LPIDR (0x13D)
929#define SPR_DABR2 (0x13D)
930#define SPR_BOOKE_DAC2 (0x13D)
931#define SPR_BOOKE_DVC1 (0x13E)
932#define SPR_BOOKE_DVC2 (0x13F)
933#define SPR_BOOKE_TSR (0x150)
934#define SPR_BOOKE_TCR (0x154)
935#define SPR_BOOKE_IVOR0 (0x190)
936#define SPR_BOOKE_IVOR1 (0x191)
937#define SPR_BOOKE_IVOR2 (0x192)
938#define SPR_BOOKE_IVOR3 (0x193)
939#define SPR_BOOKE_IVOR4 (0x194)
940#define SPR_BOOKE_IVOR5 (0x195)
941#define SPR_BOOKE_IVOR6 (0x196)
942#define SPR_BOOKE_IVOR7 (0x197)
943#define SPR_BOOKE_IVOR8 (0x198)
944#define SPR_BOOKE_IVOR9 (0x199)
945#define SPR_BOOKE_IVOR10 (0x19A)
946#define SPR_BOOKE_IVOR11 (0x19B)
947#define SPR_BOOKE_IVOR12 (0x19C)
948#define SPR_BOOKE_IVOR13 (0x19D)
949#define SPR_BOOKE_IVOR14 (0x19E)
950#define SPR_BOOKE_IVOR15 (0x19F)
951#define SPR_BOOKE_SPEFSCR (0x200)
952#define SPR_Exxx_BBEAR (0x201)
953#define SPR_Exxx_BBTAR (0x202)
954#define SPR_Exxx_L1CFG0 (0x203)
955#define SPR_Exxx_NPIDR (0x205)
956#define SPR_ATBL (0x20E)
957#define SPR_ATBU (0x20F)
958#define SPR_IBAT0U (0x210)
959#define SPR_BOOKE_IVOR32 (0x210)
960#define SPR_RCPU_MI_GRA (0x210)
961#define SPR_IBAT0L (0x211)
962#define SPR_BOOKE_IVOR33 (0x211)
963#define SPR_IBAT1U (0x212)
964#define SPR_BOOKE_IVOR34 (0x212)
965#define SPR_IBAT1L (0x213)
966#define SPR_BOOKE_IVOR35 (0x213)
967#define SPR_IBAT2U (0x214)
968#define SPR_BOOKE_IVOR36 (0x214)
969#define SPR_IBAT2L (0x215)
970#define SPR_BOOKE_IVOR37 (0x215)
971#define SPR_IBAT3U (0x216)
972#define SPR_IBAT3L (0x217)
973#define SPR_DBAT0U (0x218)
974#define SPR_RCPU_L2U_GRA (0x218)
975#define SPR_DBAT0L (0x219)
976#define SPR_DBAT1U (0x21A)
977#define SPR_DBAT1L (0x21B)
978#define SPR_DBAT2U (0x21C)
979#define SPR_DBAT2L (0x21D)
980#define SPR_DBAT3U (0x21E)
981#define SPR_DBAT3L (0x21F)
982#define SPR_IBAT4U (0x230)
983#define SPR_RPCU_BBCMCR (0x230)
984#define SPR_MPC_IC_CST (0x230)
985#define SPR_Exxx_CTXCR (0x230)
986#define SPR_IBAT4L (0x231)
987#define SPR_MPC_IC_ADR (0x231)
988#define SPR_Exxx_DBCR3 (0x231)
989#define SPR_IBAT5U (0x232)
990#define SPR_MPC_IC_DAT (0x232)
991#define SPR_Exxx_DBCNT (0x232)
992#define SPR_IBAT5L (0x233)
993#define SPR_IBAT6U (0x234)
994#define SPR_IBAT6L (0x235)
995#define SPR_IBAT7U (0x236)
996#define SPR_IBAT7L (0x237)
997#define SPR_DBAT4U (0x238)
998#define SPR_RCPU_L2U_MCR (0x238)
999#define SPR_MPC_DC_CST (0x238)
1000#define SPR_Exxx_ALTCTXCR (0x238)
1001#define SPR_DBAT4L (0x239)
1002#define SPR_MPC_DC_ADR (0x239)
1003#define SPR_DBAT5U (0x23A)
1004#define SPR_BOOKE_MCSRR0 (0x23A)
1005#define SPR_MPC_DC_DAT (0x23A)
1006#define SPR_DBAT5L (0x23B)
1007#define SPR_BOOKE_MCSRR1 (0x23B)
1008#define SPR_DBAT6U (0x23C)
1009#define SPR_BOOKE_MCSR (0x23C)
1010#define SPR_DBAT6L (0x23D)
1011#define SPR_Exxx_MCAR (0x23D)
1012#define SPR_DBAT7U (0x23E)
1013#define SPR_BOOKE_DSRR0 (0x23E)
1014#define SPR_DBAT7L (0x23F)
1015#define SPR_BOOKE_DSRR1 (0x23F)
1016#define SPR_BOOKE_SPRG8 (0x25C)
1017#define SPR_BOOKE_SPRG9 (0x25D)
1018#define SPR_BOOKE_MAS0 (0x270)
1019#define SPR_BOOKE_MAS1 (0x271)
1020#define SPR_BOOKE_MAS2 (0x272)
1021#define SPR_BOOKE_MAS3 (0x273)
1022#define SPR_BOOKE_MAS4 (0x274)
1023#define SPR_BOOKE_MAS5 (0x275)
1024#define SPR_BOOKE_MAS6 (0x276)
1025#define SPR_BOOKE_PID1 (0x279)
1026#define SPR_BOOKE_PID2 (0x27A)
1027#define SPR_MPC_DPDR (0x280)
1028#define SPR_MPC_IMMR (0x288)
1029#define SPR_BOOKE_TLB0CFG (0x2B0)
1030#define SPR_BOOKE_TLB1CFG (0x2B1)
1031#define SPR_BOOKE_TLB2CFG (0x2B2)
1032#define SPR_BOOKE_TLB3CFG (0x2B3)
1033#define SPR_BOOKE_EPR (0x2BE)
1034#define SPR_PERF0 (0x300)
1035#define SPR_RCPU_MI_RBA0 (0x300)
1036#define SPR_MPC_MI_CTR (0x300)
1037#define SPR_PERF1 (0x301)
1038#define SPR_RCPU_MI_RBA1 (0x301)
1039#define SPR_PERF2 (0x302)
1040#define SPR_RCPU_MI_RBA2 (0x302)
1041#define SPR_MPC_MI_AP (0x302)
1042#define SPR_PERF3 (0x303)
1043#define SPR_RCPU_MI_RBA3 (0x303)
1044#define SPR_MPC_MI_EPN (0x303)
1045#define SPR_PERF4 (0x304)
1046#define SPR_PERF5 (0x305)
1047#define SPR_MPC_MI_TWC (0x305)
1048#define SPR_PERF6 (0x306)
1049#define SPR_MPC_MI_RPN (0x306)
1050#define SPR_PERF7 (0x307)
1051#define SPR_PERF8 (0x308)
1052#define SPR_RCPU_L2U_RBA0 (0x308)
1053#define SPR_MPC_MD_CTR (0x308)
1054#define SPR_PERF9 (0x309)
1055#define SPR_RCPU_L2U_RBA1 (0x309)
1056#define SPR_MPC_MD_CASID (0x309)
1057#define SPR_PERFA (0x30A)
1058#define SPR_RCPU_L2U_RBA2 (0x30A)
1059#define SPR_MPC_MD_AP (0x30A)
1060#define SPR_PERFB (0x30B)
1061#define SPR_RCPU_L2U_RBA3 (0x30B)
1062#define SPR_MPC_MD_EPN (0x30B)
1063#define SPR_PERFC (0x30C)
1064#define SPR_MPC_MD_TWB (0x30C)
1065#define SPR_PERFD (0x30D)
1066#define SPR_MPC_MD_TWC (0x30D)
1067#define SPR_PERFE (0x30E)
1068#define SPR_MPC_MD_RPN (0x30E)
1069#define SPR_PERFF (0x30F)
1070#define SPR_MPC_MD_TW (0x30F)
1071#define SPR_UPERF0 (0x310)
1072#define SPR_UPERF1 (0x311)
1073#define SPR_UPERF2 (0x312)
1074#define SPR_UPERF3 (0x313)
1075#define SPR_UPERF4 (0x314)
1076#define SPR_UPERF5 (0x315)
1077#define SPR_UPERF6 (0x316)
1078#define SPR_UPERF7 (0x317)
1079#define SPR_UPERF8 (0x318)
1080#define SPR_UPERF9 (0x319)
1081#define SPR_UPERFA (0x31A)
1082#define SPR_UPERFB (0x31B)
1083#define SPR_UPERFC (0x31C)
1084#define SPR_UPERFD (0x31D)
1085#define SPR_UPERFE (0x31E)
1086#define SPR_UPERFF (0x31F)
1087#define SPR_RCPU_MI_RA0 (0x320)
1088#define SPR_MPC_MI_DBCAM (0x320)
1089#define SPR_RCPU_MI_RA1 (0x321)
1090#define SPR_MPC_MI_DBRAM0 (0x321)
1091#define SPR_RCPU_MI_RA2 (0x322)
1092#define SPR_MPC_MI_DBRAM1 (0x322)
1093#define SPR_RCPU_MI_RA3 (0x323)
1094#define SPR_RCPU_L2U_RA0 (0x328)
1095#define SPR_MPC_MD_DBCAM (0x328)
1096#define SPR_RCPU_L2U_RA1 (0x329)
1097#define SPR_MPC_MD_DBRAM0 (0x329)
1098#define SPR_RCPU_L2U_RA2 (0x32A)
1099#define SPR_MPC_MD_DBRAM1 (0x32A)
1100#define SPR_RCPU_L2U_RA3 (0x32B)
1101#define SPR_440_INV0 (0x370)
1102#define SPR_440_INV1 (0x371)
1103#define SPR_440_INV2 (0x372)
1104#define SPR_440_INV3 (0x373)
1105#define SPR_440_ITV0 (0x374)
1106#define SPR_440_ITV1 (0x375)
1107#define SPR_440_ITV2 (0x376)
1108#define SPR_440_ITV3 (0x377)
1109#define SPR_440_CCR1 (0x378)
1110#define SPR_DCRIPR (0x37B)
1111#define SPR_PPR (0x380)
1112#define SPR_440_DNV0 (0x390)
1113#define SPR_440_DNV1 (0x391)
1114#define SPR_440_DNV2 (0x392)
1115#define SPR_440_DNV3 (0x393)
1116#define SPR_440_DTV0 (0x394)
1117#define SPR_440_DTV1 (0x395)
1118#define SPR_440_DTV2 (0x396)
1119#define SPR_440_DTV3 (0x397)
1120#define SPR_440_DVLIM (0x398)
1121#define SPR_440_IVLIM (0x399)
1122#define SPR_440_RSTCFG (0x39B)
1123#define SPR_BOOKE_DCDBTRL (0x39C)
1124#define SPR_BOOKE_DCDBTRH (0x39D)
1125#define SPR_BOOKE_ICDBTRL (0x39E)
1126#define SPR_BOOKE_ICDBTRH (0x39F)
1127#define SPR_UMMCR2 (0x3A0)
1128#define SPR_UPMC5 (0x3A1)
1129#define SPR_UPMC6 (0x3A2)
1130#define SPR_UBAMR (0x3A7)
1131#define SPR_UMMCR0 (0x3A8)
1132#define SPR_UPMC1 (0x3A9)
1133#define SPR_UPMC2 (0x3AA)
1134#define SPR_USIAR (0x3AB)
1135#define SPR_UMMCR1 (0x3AC)
1136#define SPR_UPMC3 (0x3AD)
1137#define SPR_UPMC4 (0x3AE)
1138#define SPR_USDA (0x3AF)
1139#define SPR_40x_ZPR (0x3B0)
1140#define SPR_BOOKE_MAS7 (0x3B0)
1141#define SPR_620_PMR0 (0x3B0)
1142#define SPR_MMCR2 (0x3B0)
1143#define SPR_PMC5 (0x3B1)
1144#define SPR_40x_PID (0x3B1)
1145#define SPR_620_PMR1 (0x3B1)
1146#define SPR_PMC6 (0x3B2)
1147#define SPR_440_MMUCR (0x3B2)
1148#define SPR_620_PMR2 (0x3B2)
1149#define SPR_4xx_CCR0 (0x3B3)
1150#define SPR_BOOKE_EPLC (0x3B3)
1151#define SPR_620_PMR3 (0x3B3)
1152#define SPR_405_IAC3 (0x3B4)
1153#define SPR_BOOKE_EPSC (0x3B4)
1154#define SPR_620_PMR4 (0x3B4)
1155#define SPR_405_IAC4 (0x3B5)
1156#define SPR_620_PMR5 (0x3B5)
1157#define SPR_405_DVC1 (0x3B6)
1158#define SPR_620_PMR6 (0x3B6)
1159#define SPR_405_DVC2 (0x3B7)
1160#define SPR_620_PMR7 (0x3B7)
1161#define SPR_BAMR (0x3B7)
1162#define SPR_MMCR0 (0x3B8)
1163#define SPR_620_PMR8 (0x3B8)
1164#define SPR_PMC1 (0x3B9)
1165#define SPR_40x_SGR (0x3B9)
1166#define SPR_620_PMR9 (0x3B9)
1167#define SPR_PMC2 (0x3BA)
1168#define SPR_40x_DCWR (0x3BA)
1169#define SPR_620_PMRA (0x3BA)
1170#define SPR_SIAR (0x3BB)
1171#define SPR_405_SLER (0x3BB)
1172#define SPR_620_PMRB (0x3BB)
1173#define SPR_MMCR1 (0x3BC)
1174#define SPR_405_SU0R (0x3BC)
1175#define SPR_620_PMRC (0x3BC)
1176#define SPR_401_SKR (0x3BC)
1177#define SPR_PMC3 (0x3BD)
1178#define SPR_405_DBCR1 (0x3BD)
1179#define SPR_620_PMRD (0x3BD)
1180#define SPR_PMC4 (0x3BE)
1181#define SPR_620_PMRE (0x3BE)
1182#define SPR_SDA (0x3BF)
1183#define SPR_620_PMRF (0x3BF)
1184#define SPR_403_VTBL (0x3CC)
1185#define SPR_403_VTBU (0x3CD)
1186#define SPR_DMISS (0x3D0)
1187#define SPR_DCMP (0x3D1)
1188#define SPR_HASH1 (0x3D2)
1189#define SPR_HASH2 (0x3D3)
1190#define SPR_BOOKE_ICDBDR (0x3D3)
1191#define SPR_TLBMISS (0x3D4)
1192#define SPR_IMISS (0x3D4)
1193#define SPR_40x_ESR (0x3D4)
1194#define SPR_PTEHI (0x3D5)
1195#define SPR_ICMP (0x3D5)
1196#define SPR_40x_DEAR (0x3D5)
1197#define SPR_PTELO (0x3D6)
1198#define SPR_RPA (0x3D6)
1199#define SPR_40x_EVPR (0x3D6)
1200#define SPR_L3PM (0x3D7)
1201#define SPR_403_CDBCR (0x3D7)
1202#define SPR_L3OHCR (0x3D8)
1203#define SPR_TCR (0x3D8)
1204#define SPR_40x_TSR (0x3D8)
1205#define SPR_IBR (0x3DA)
1206#define SPR_40x_TCR (0x3DA)
1207#define SPR_ESASRR (0x3DB)
1208#define SPR_40x_PIT (0x3DB)
1209#define SPR_403_TBL (0x3DC)
1210#define SPR_403_TBU (0x3DD)
1211#define SPR_SEBR (0x3DE)
1212#define SPR_40x_SRR2 (0x3DE)
1213#define SPR_SER (0x3DF)
1214#define SPR_40x_SRR3 (0x3DF)
1215#define SPR_L3ITCR0 (0x3E8)
1216#define SPR_L3ITCR1 (0x3E9)
1217#define SPR_L3ITCR2 (0x3EA)
1218#define SPR_L3ITCR3 (0x3EB)
1219#define SPR_HID0 (0x3F0)
1220#define SPR_40x_DBSR (0x3F0)
1221#define SPR_HID1 (0x3F1)
1222#define SPR_IABR (0x3F2)
1223#define SPR_40x_DBCR0 (0x3F2)
1224#define SPR_601_HID2 (0x3F2)
1225#define SPR_Exxx_L1CSR0 (0x3F2)
1226#define SPR_ICTRL (0x3F3)
1227#define SPR_HID2 (0x3F3)
1228#define SPR_Exxx_L1CSR1 (0x3F3)
1229#define SPR_440_DBDR (0x3F3)
1230#define SPR_LDSTDB (0x3F4)
1231#define SPR_40x_IAC1 (0x3F4)
1232#define SPR_MMUCSR0 (0x3F4)
1233#define SPR_DABR (0x3F5)
3fc6c082 1234#define DABR_MASK (~(target_ulong)0x7)
80d11f44
JM		 1235#define SPR_Exxx_BUCSR (0x3F5)
1236#define SPR_40x_IAC2 (0x3F5)
1237#define SPR_601_HID5 (0x3F5)
1238#define SPR_40x_DAC1 (0x3F6)
1239#define SPR_MSSCR0 (0x3F6)
1240#define SPR_970_HID5 (0x3F6)
1241#define SPR_MSSSR0 (0x3F7)
1242#define SPR_DABRX (0x3F7)
1243#define SPR_40x_DAC2 (0x3F7)
1244#define SPR_MMUCFG (0x3F7)
1245#define SPR_LDSTCR (0x3F8)
1246#define SPR_L2PMCR (0x3F8)
1247#define SPR_750_HID2 (0x3F8)
1248#define SPR_620_HID8 (0x3F8)
1249#define SPR_Exxx_L1FINV0 (0x3F8)
1250#define SPR_L2CR (0x3F9)
1251#define SPR_620_HID9 (0x3F9)
1252#define SPR_L3CR (0x3FA)
1253#define SPR_IABR2 (0x3FA)
1254#define SPR_40x_DCCR (0x3FA)
1255#define SPR_ICTC (0x3FB)
1256#define SPR_40x_ICCR (0x3FB)
1257#define SPR_THRM1 (0x3FC)
1258#define SPR_403_PBL1 (0x3FC)
1259#define SPR_SP (0x3FD)
1260#define SPR_THRM2 (0x3FD)
1261#define SPR_403_PBU1 (0x3FD)
1262#define SPR_604_HID13 (0x3FD)
1263#define SPR_LT (0x3FE)
1264#define SPR_THRM3 (0x3FE)
1265#define SPR_RCPU_FPECR (0x3FE)
1266#define SPR_403_PBL2 (0x3FE)
1267#define SPR_PIR (0x3FF)
1268#define SPR_403_PBU2 (0x3FF)
1269#define SPR_601_HID15 (0x3FF)
1270#define SPR_604_HID15 (0x3FF)
1271#define SPR_E500_SVR (0x3FF)
79aceca5 1272
76a66253 1273/*****************************************************************************/
9a64fbe4
FB		 1274/* Memory access type :
1275 * may be needed for precise access rights control and precise exceptions.
1276 */
79aceca5 1277enum {
9a64fbe4
FB		 1278 /* 1 bit to define user level / supervisor access */
1279 ACCESS_USER = 0x00,
1280 ACCESS_SUPER = 0x01,
1281 /* Type of instruction that generated the access */
1282 ACCESS_CODE = 0x10, /* Code fetch access */
1283 ACCESS_INT = 0x20, /* Integer load/store access */
1284 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1285 ACCESS_RES = 0x40, /* load/store with reservation */
1286 ACCESS_EXT = 0x50, /* external access */
1287 ACCESS_CACHE = 0x60, /* Cache manipulation */
1288};
1289
47103572
JM		 1290/* Hardware interruption sources:
1291 * all those exception can be raised simulteaneously
1292 */
e9df014c
JM		 1293/* Input pins definitions */
1294enum {
1295 /* 6xx bus input pins */
24be5ae3
JM		 1296 PPC6xx_INPUT_HRESET = 0,
1297 PPC6xx_INPUT_SRESET = 1,
1298 PPC6xx_INPUT_CKSTP_IN = 2,
1299 PPC6xx_INPUT_MCP = 3,
1300 PPC6xx_INPUT_SMI = 4,
1301 PPC6xx_INPUT_INT = 5,
d68f1306
JM		 1302 PPC6xx_INPUT_TBEN = 6,
1303 PPC6xx_INPUT_WAKEUP = 7,
1304 PPC6xx_INPUT_NB,
24be5ae3
JM		 1305};
1306
1307enum {
e9df014c 1308 /* Embedded PowerPC input pins */
24be5ae3
JM		 1309 PPCBookE_INPUT_HRESET = 0,
1310 PPCBookE_INPUT_SRESET = 1,
1311 PPCBookE_INPUT_CKSTP_IN = 2,
1312 PPCBookE_INPUT_MCP = 3,
1313 PPCBookE_INPUT_SMI = 4,
1314 PPCBookE_INPUT_INT = 5,
1315 PPCBookE_INPUT_CINT = 6,
d68f1306 1316 PPCBookE_INPUT_NB,
24be5ae3
JM		 1317};
1318
a750fc0b 1319enum {
4e290a0b
JM		 1320 /* PowerPC 40x input pins */
1321 PPC40x_INPUT_RESET_CORE = 0,
1322 PPC40x_INPUT_RESET_CHIP = 1,
1323 PPC40x_INPUT_RESET_SYS = 2,
1324 PPC40x_INPUT_CINT = 3,
1325 PPC40x_INPUT_INT = 4,
1326 PPC40x_INPUT_HALT = 5,
1327 PPC40x_INPUT_DEBUG = 6,
1328 PPC40x_INPUT_NB,
e9df014c
JM		 1329};
1330
b4095fed
JM		 1331enum {
1332 /* RCPU input pins */
1333 PPCRCPU_INPUT_PORESET = 0,
1334 PPCRCPU_INPUT_HRESET = 1,
1335 PPCRCPU_INPUT_SRESET = 2,
1336 PPCRCPU_INPUT_IRQ0 = 3,
1337 PPCRCPU_INPUT_IRQ1 = 4,
1338 PPCRCPU_INPUT_IRQ2 = 5,
1339 PPCRCPU_INPUT_IRQ3 = 6,
1340 PPCRCPU_INPUT_IRQ4 = 7,
1341 PPCRCPU_INPUT_IRQ5 = 8,
1342 PPCRCPU_INPUT_IRQ6 = 9,
1343 PPCRCPU_INPUT_IRQ7 = 10,
1344 PPCRCPU_INPUT_NB,
1345};
1346
00af685f 1347#if defined(TARGET_PPC64)
d0dfae6e
JM		 1348enum {
1349 /* PowerPC 970 input pins */
1350 PPC970_INPUT_HRESET = 0,
1351 PPC970_INPUT_SRESET = 1,
1352 PPC970_INPUT_CKSTP = 2,
1353 PPC970_INPUT_TBEN = 3,
1354 PPC970_INPUT_MCP = 4,
1355 PPC970_INPUT_INT = 5,
1356 PPC970_INPUT_THINT = 6,
7b62a955 1357 PPC970_INPUT_NB,
d0dfae6e 1358};
00af685f 1359#endif
d0dfae6e 1360
e9df014c 1361/* Hardware exceptions definitions */
47103572 1362enum {
e9df014c 1363 /* External hardware exception sources */
e1833e1f 1364 PPC_INTERRUPT_RESET = 0, /* Reset exception */
d68f1306
JM		 1365 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
1366 PPC_INTERRUPT_MCK, /* Machine check exception */
1367 PPC_INTERRUPT_EXT, /* External interrupt */
1368 PPC_INTERRUPT_SMI, /* System management interrupt */
1369 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
1370 PPC_INTERRUPT_DEBUG, /* External debug exception */
1371 PPC_INTERRUPT_THERM, /* Thermal exception */
e9df014c 1372 /* Internal hardware exception sources */
d68f1306
JM		 1373 PPC_INTERRUPT_DECR, /* Decrementer exception */
1374 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
1375 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
1376 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
1377 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
1378 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
1379 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
1380 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
47103572
JM		 1381};
1382
9a64fbe4
FB		 1383/*****************************************************************************/
1384
79aceca5 1385#endif /* !defined (__CPU_PPC_H__) */
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