]> Git Repo - qemu.git/blame - target-microblaze/translate.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branch 'kwolf/for-anthony' into staging
[qemu.git] / target-microblaze / translate.c
CommitLineData
4acb54ba
EI		 1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
dadc1064 5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
4acb54ba
EI		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba
EI		 19 */
20
4acb54ba 21#include "cpu.h"
4acb54ba
EI		 22#include "disas.h"
23#include "tcg-op.h"
24#include "helper.h"
25#include "microblaze-decode.h"
4acb54ba
EI		 26
27#define GEN_HELPER 1
28#include "helper.h"
29
30#define SIM_COMPAT 0
31#define DISAS_GNU 1
32#define DISAS_MB 1
33#if DISAS_MB && !SIM_COMPAT
34# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
35#else
36# define LOG_DIS(...) do { } while (0)
37#endif
38
39#define D(x)
40
41#define EXTRACT_FIELD(src, start, end) \
42 (((src) >> start) & ((1 << (end - start + 1)) - 1))
43
44static TCGv env_debug;
45static TCGv_ptr cpu_env;
46static TCGv cpu_R[32];
47static TCGv cpu_SR[18];
48static TCGv env_imm;
49static TCGv env_btaken;
50static TCGv env_btarget;
51static TCGv env_iflags;
52
53#include "gen-icount.h"
54
55/* This is the state at translation time. */
56typedef struct DisasContext {
68cee38a 57 CPUMBState *env;
a5efa644 58 target_ulong pc;
4acb54ba
EI		 59
60 /* Decoder. */
61 int type_b;
62 uint32_t ir;
63 uint8_t opcode;
64 uint8_t rd, ra, rb;
65 uint16_t imm;
66
67 unsigned int cpustate_changed;
68 unsigned int delayed_branch;
69 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
70 unsigned int clear_imm;
71 int is_jmp;
72
844bab60
EI		 73#define JMP_NOJMP 0
74#define JMP_DIRECT 1
75#define JMP_DIRECT_CC 2
76#define JMP_INDIRECT 3
4acb54ba
EI		 77 unsigned int jmp;
78 uint32_t jmp_pc;
79
80 int abort_at_next_insn;
81 int nr_nops;
82 struct TranslationBlock *tb;
83 int singlestep_enabled;
84} DisasContext;
85
38972938 86static const char *regnames[] =
4acb54ba
EI		 87{
88 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
89 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
90 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
91 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
92};
93
38972938 94static const char *special_regnames[] =
4acb54ba
EI		 95{
96 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
97 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
98 "sr16", "sr17", "sr18"
99};
100
101/* Sign extend at translation time. */
102static inline int sign_extend(unsigned int val, unsigned int width)
103{
104 int sval;
105
106 /* LSL. */
107 val <<= 31 - width;
108 sval = val;
109 /* ASR. */
110 sval >>= 31 - width;
111 return sval;
112}
113
114static inline void t_sync_flags(DisasContext *dc)
115{
4abf79a4 116 /* Synch the tb dependent flags between translator and runtime. */
4acb54ba
EI		 117 if (dc->tb_flags != dc->synced_flags) {
118 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
119 dc->synced_flags = dc->tb_flags;
120 }
121}
122
123static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
124{
125 TCGv_i32 tmp = tcg_const_i32(index);
126
127 t_sync_flags(dc);
128 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
64254eba 129 gen_helper_raise_exception(cpu_env, tmp);
4acb54ba
EI		 130 tcg_temp_free_i32(tmp);
131 dc->is_jmp = DISAS_UPDATE;
132}
133
134static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
135{
136 TranslationBlock *tb;
137 tb = dc->tb;
138 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
139 tcg_gen_goto_tb(n);
140 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
4b4a72e5 141 tcg_gen_exit_tb((tcg_target_long)tb + n);
4acb54ba
EI		 142 } else {
143 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
144 tcg_gen_exit_tb(0);
145 }
146}
147
ee8b246f
EI		 148static void read_carry(DisasContext *dc, TCGv d)
149{
150 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
151}
152
153static void write_carry(DisasContext *dc, TCGv v)
154{
155 TCGv t0 = tcg_temp_new();
156 tcg_gen_shli_tl(t0, v, 31);
157 tcg_gen_sari_tl(t0, t0, 31);
158 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
159 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
160 ~(MSR_C | MSR_CC));
161 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
162 tcg_temp_free(t0);
163}
164
8cc9b43f
PC		 165static void write_carryi(DisasContext *dc, int carry)
166{
167 TCGv t0 = tcg_temp_new();
168 tcg_gen_movi_tl(t0, carry ? 1 : 0);
169 write_carry(dc, t0);
170 tcg_temp_free(t0);
171}
172
61204ce8
EI		 173/* True if ALU operand b is a small immediate that may deserve
174 faster treatment. */
175static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
176{
177 /* Immediate insn without the imm prefix ? */
178 return dc->type_b && !(dc->tb_flags & IMM_FLAG);
179}
180
4acb54ba
EI		 181static inline TCGv *dec_alu_op_b(DisasContext *dc)
182{
183 if (dc->type_b) {
184 if (dc->tb_flags & IMM_FLAG)
185 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
186 else
187 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
188 return &env_imm;
189 } else
190 return &cpu_R[dc->rb];
191}
192
193static void dec_add(DisasContext *dc)
194{
195 unsigned int k, c;
40cbf5b7 196 TCGv cf;
4acb54ba
EI		 197
198 k = dc->opcode & 4;
199 c = dc->opcode & 2;
200
201 LOG_DIS("add%s%s%s r%d r%d r%d\n",
202 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
203 dc->rd, dc->ra, dc->rb);
204
40cbf5b7
EI		 205 /* Take care of the easy cases first. */
206 if (k) {
207 /* k - keep carry, no need to update MSR. */
208 /* If rd == r0, it's a nop. */
209 if (dc->rd) {
210 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
211
212 if (c) {
213 /* c - Add carry into the result. */
214 cf = tcg_temp_new();
215
216 read_carry(dc, cf);
217 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
218 tcg_temp_free(cf);
219 }
220 }
221 return;
222 }
223
224 /* From now on, we can assume k is zero. So we need to update MSR. */
225 /* Extract carry. */
226 cf = tcg_temp_new();
227 if (c) {
228 read_carry(dc, cf);
229 } else {
230 tcg_gen_movi_tl(cf, 0);
231 }
232
233 if (dc->rd) {
234 TCGv ncf = tcg_temp_new();
5d0bb823 235 gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
4acb54ba 236 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
40cbf5b7
EI		 237 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
238 write_carry(dc, ncf);
239 tcg_temp_free(ncf);
240 } else {
5d0bb823 241 gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
40cbf5b7 242 write_carry(dc, cf);
4acb54ba 243 }
40cbf5b7 244 tcg_temp_free(cf);
4acb54ba
EI		 245}
246
247static void dec_sub(DisasContext *dc)
248{
249 unsigned int u, cmp, k, c;
e0a42ebc 250 TCGv cf, na;
4acb54ba
EI		 251
252 u = dc->imm & 2;
253 k = dc->opcode & 4;
254 c = dc->opcode & 2;
255 cmp = (dc->imm & 1) && (!dc->type_b) && k;
256
257 if (cmp) {
258 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
259 if (dc->rd) {
260 if (u)
261 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
262 else
263 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
264 }
e0a42ebc
EI		 265 return;
266 }
267
268 LOG_DIS("sub%s%s r%d, r%d r%d\n",
269 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
270
271 /* Take care of the easy cases first. */
272 if (k) {
273 /* k - keep carry, no need to update MSR. */
274 /* If rd == r0, it's a nop. */
275 if (dc->rd) {
4acb54ba 276 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
e0a42ebc
EI		 277
278 if (c) {
279 /* c - Add carry into the result. */
280 cf = tcg_temp_new();
281
282 read_carry(dc, cf);
283 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
284 tcg_temp_free(cf);
285 }
286 }
287 return;
288 }
289
290 /* From now on, we can assume k is zero. So we need to update MSR. */
291 /* Extract carry. And complement a into na. */
292 cf = tcg_temp_new();
293 na = tcg_temp_new();
294 if (c) {
295 read_carry(dc, cf);
296 } else {
297 tcg_gen_movi_tl(cf, 1);
298 }
299
300 /* d = b + ~a + c. carry defaults to 1. */
301 tcg_gen_not_tl(na, cpu_R[dc->ra]);
302
303 if (dc->rd) {
304 TCGv ncf = tcg_temp_new();
5d0bb823 305 gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf);
e0a42ebc
EI		 306 tcg_gen_add_tl(cpu_R[dc->rd], na, *(dec_alu_op_b(dc)));
307 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
308 write_carry(dc, ncf);
309 tcg_temp_free(ncf);
310 } else {
5d0bb823 311 gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf);
e0a42ebc 312 write_carry(dc, cf);
4acb54ba 313 }
e0a42ebc
EI		 314 tcg_temp_free(cf);
315 tcg_temp_free(na);
4acb54ba
EI		 316}
317
318static void dec_pattern(DisasContext *dc)
319{
320 unsigned int mode;
321 int l1;
322
1567a005 323 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 324 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 325 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
326 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
327 t_gen_raise_exception(dc, EXCP_HW_EXCP);
328 }
329
4acb54ba
EI		 330 mode = dc->opcode & 3;
331 switch (mode) {
332 case 0:
333 /* pcmpbf. */
334 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
335 if (dc->rd)
336 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
337 break;
338 case 2:
339 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
340 if (dc->rd) {
341 TCGv t0 = tcg_temp_local_new();
342 l1 = gen_new_label();
343 tcg_gen_movi_tl(t0, 1);
344 tcg_gen_brcond_tl(TCG_COND_EQ,
345 cpu_R[dc->ra], cpu_R[dc->rb], l1);
346 tcg_gen_movi_tl(t0, 0);
347 gen_set_label(l1);
348 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
349 tcg_temp_free(t0);
350 }
351 break;
352 case 3:
353 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
354 l1 = gen_new_label();
355 if (dc->rd) {
356 TCGv t0 = tcg_temp_local_new();
357 tcg_gen_movi_tl(t0, 1);
358 tcg_gen_brcond_tl(TCG_COND_NE,
359 cpu_R[dc->ra], cpu_R[dc->rb], l1);
360 tcg_gen_movi_tl(t0, 0);
361 gen_set_label(l1);
362 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
363 tcg_temp_free(t0);
364 }
365 break;
366 default:
367 cpu_abort(dc->env,
368 "unsupported pattern insn opcode=%x\n", dc->opcode);
369 break;
370 }
371}
372
373static void dec_and(DisasContext *dc)
374{
375 unsigned int not;
376
377 if (!dc->type_b && (dc->imm & (1 << 10))) {
378 dec_pattern(dc);
379 return;
380 }
381
382 not = dc->opcode & (1 << 1);
383 LOG_DIS("and%s\n", not ? "n" : "");
384
385 if (!dc->rd)
386 return;
387
388 if (not) {
389 TCGv t = tcg_temp_new();
390 tcg_gen_not_tl(t, *(dec_alu_op_b(dc)));
391 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t);
392 tcg_temp_free(t);
393 } else
394 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
395}
396
397static void dec_or(DisasContext *dc)
398{
399 if (!dc->type_b && (dc->imm & (1 << 10))) {
400 dec_pattern(dc);
401 return;
402 }
403
404 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
405 if (dc->rd)
406 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
407}
408
409static void dec_xor(DisasContext *dc)
410{
411 if (!dc->type_b && (dc->imm & (1 << 10))) {
412 dec_pattern(dc);
413 return;
414 }
415
416 LOG_DIS("xor r%d\n", dc->rd);
417 if (dc->rd)
418 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
419}
420
4acb54ba
EI		 421static inline void msr_read(DisasContext *dc, TCGv d)
422{
423 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
424}
425
426static inline void msr_write(DisasContext *dc, TCGv v)
427{
97b833c5
EI		 428 TCGv t;
429
430 t = tcg_temp_new();
4acb54ba 431 dc->cpustate_changed = 1;
97b833c5 432 /* PVR bit is not writable. */
8a84fc6b
EI		 433 tcg_gen_andi_tl(t, v, ~MSR_PVR);
434 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR);
97b833c5
EI		 435 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v);
436 tcg_temp_free(t);
4acb54ba
EI		 437}
438
439static void dec_msr(DisasContext *dc)
440{
441 TCGv t0, t1;
442 unsigned int sr, to, rn;
1567a005 443 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 444
445 sr = dc->imm & ((1 << 14) - 1);
446 to = dc->imm & (1 << 14);
447 dc->type_b = 1;
448 if (to)
449 dc->cpustate_changed = 1;
450
451 /* msrclr and msrset. */
452 if (!(dc->imm & (1 << 15))) {
453 unsigned int clr = dc->ir & (1 << 16);
454
455 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
456 dc->rd, dc->imm);
1567a005
EI		 457
458 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
459 /* nop??? */
460 return;
461 }
462
463 if ((dc->tb_flags & MSR_EE_FLAG)
464 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
465 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
466 t_gen_raise_exception(dc, EXCP_HW_EXCP);
467 return;
468 }
469
4acb54ba
EI		 470 if (dc->rd)
471 msr_read(dc, cpu_R[dc->rd]);
472
473 t0 = tcg_temp_new();
474 t1 = tcg_temp_new();
475 msr_read(dc, t0);
476 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
477
478 if (clr) {
479 tcg_gen_not_tl(t1, t1);
480 tcg_gen_and_tl(t0, t0, t1);
481 } else
482 tcg_gen_or_tl(t0, t0, t1);
483 msr_write(dc, t0);
484 tcg_temp_free(t0);
485 tcg_temp_free(t1);
486 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
487 dc->is_jmp = DISAS_UPDATE;
488 return;
489 }
490
1567a005
EI		 491 if (to) {
492 if ((dc->tb_flags & MSR_EE_FLAG)
493 && mem_index == MMU_USER_IDX) {
494 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
495 t_gen_raise_exception(dc, EXCP_HW_EXCP);
496 return;
497 }
498 }
499
4acb54ba
EI		 500#if !defined(CONFIG_USER_ONLY)
501 /* Catch read/writes to the mmu block. */
502 if ((sr & ~0xff) == 0x1000) {
503 sr &= 7;
504 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
505 if (to)
64254eba 506 gen_helper_mmu_write(cpu_env, tcg_const_tl(sr), cpu_R[dc->ra]);
4acb54ba 507 else
64254eba 508 gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tcg_const_tl(sr));
4acb54ba
EI		 509 return;
510 }
511#endif
512
513 if (to) {
514 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
515 switch (sr) {
516 case 0:
517 break;
518 case 1:
519 msr_write(dc, cpu_R[dc->ra]);
520 break;
521 case 0x3:
522 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
523 break;
524 case 0x5:
525 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
526 break;
527 case 0x7:
97694c57 528 tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
4acb54ba 529 break;
5818dee5 530 case 0x800:
68cee38a 531 tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, slr));
5818dee5
EI		 532 break;
533 case 0x802:
68cee38a 534 tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr));
5818dee5 535 break;
4acb54ba
EI		 536 default:
537 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
538 break;
539 }
540 } else {
541 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
542
543 switch (sr) {
544 case 0:
545 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
546 break;
547 case 1:
548 msr_read(dc, cpu_R[dc->rd]);
549 break;
550 case 0x3:
551 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
552 break;
553 case 0x5:
554 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
555 break;
556 case 0x7:
97694c57 557 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]);
4acb54ba
EI		 558 break;
559 case 0xb:
560 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
561 break;
5818dee5 562 case 0x800:
68cee38a 563 tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, slr));
5818dee5
EI		 564 break;
565 case 0x802:
68cee38a 566 tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, shr));
5818dee5 567 break;
4acb54ba
EI		 568 case 0x2000:
569 case 0x2001:
570 case 0x2002:
571 case 0x2003:
572 case 0x2004:
573 case 0x2005:
574 case 0x2006:
575 case 0x2007:
576 case 0x2008:
577 case 0x2009:
578 case 0x200a:
579 case 0x200b:
580 case 0x200c:
581 rn = sr & 0xf;
582 tcg_gen_ld_tl(cpu_R[dc->rd],
68cee38a 583 cpu_env, offsetof(CPUMBState, pvr.regs[rn]));
4acb54ba
EI		 584 break;
585 default:
586 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
587 break;
588 }
589 }
ee7dbcf8
EI		 590
591 if (dc->rd == 0) {
592 tcg_gen_movi_tl(cpu_R[0], 0);
593 }
4acb54ba
EI		 594}
595
596/* 64-bit signed mul, lower result in d and upper in d2. */
597static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
598{
599 TCGv_i64 t0, t1;
600
601 t0 = tcg_temp_new_i64();
602 t1 = tcg_temp_new_i64();
603
604 tcg_gen_ext_i32_i64(t0, a);
605 tcg_gen_ext_i32_i64(t1, b);
606 tcg_gen_mul_i64(t0, t0, t1);
607
608 tcg_gen_trunc_i64_i32(d, t0);
609 tcg_gen_shri_i64(t0, t0, 32);
610 tcg_gen_trunc_i64_i32(d2, t0);
611
612 tcg_temp_free_i64(t0);
613 tcg_temp_free_i64(t1);
614}
615
616/* 64-bit unsigned muls, lower result in d and upper in d2. */
617static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
618{
619 TCGv_i64 t0, t1;
620
621 t0 = tcg_temp_new_i64();
622 t1 = tcg_temp_new_i64();
623
624 tcg_gen_extu_i32_i64(t0, a);
625 tcg_gen_extu_i32_i64(t1, b);
626 tcg_gen_mul_i64(t0, t0, t1);
627
628 tcg_gen_trunc_i64_i32(d, t0);
629 tcg_gen_shri_i64(t0, t0, 32);
630 tcg_gen_trunc_i64_i32(d2, t0);
631
632 tcg_temp_free_i64(t0);
633 tcg_temp_free_i64(t1);
634}
635
636/* Multiplier unit. */
637static void dec_mul(DisasContext *dc)
638{
639 TCGv d[2];
640 unsigned int subcode;
641
1567a005 642 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 643 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 644 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
645 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
646 t_gen_raise_exception(dc, EXCP_HW_EXCP);
647 return;
648 }
649
4acb54ba
EI		 650 subcode = dc->imm & 3;
651 d[0] = tcg_temp_new();
652 d[1] = tcg_temp_new();
653
654 if (dc->type_b) {
655 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
656 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
657 goto done;
658 }
659
1567a005
EI		 660 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
661 if (subcode >= 1 && subcode <= 3
662 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
663 /* nop??? */
664 }
665
4acb54ba
EI		 666 switch (subcode) {
667 case 0:
668 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
669 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
670 break;
671 case 1:
672 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
673 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
674 break;
675 case 2:
676 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
677 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
678 break;
679 case 3:
680 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
681 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
682 break;
683 default:
684 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
685 break;
686 }
687done:
688 tcg_temp_free(d[0]);
689 tcg_temp_free(d[1]);
690}
691
692/* Div unit. */
693static void dec_div(DisasContext *dc)
694{
695 unsigned int u;
696
697 u = dc->imm & 2;
698 LOG_DIS("div\n");
699
97f90cbf 700 if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 701 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
702 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
703 t_gen_raise_exception(dc, EXCP_HW_EXCP);
704 }
705
4acb54ba 706 if (u)
64254eba
BS		 707 gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
708 cpu_R[dc->ra]);
4acb54ba 709 else
64254eba
BS		 710 gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
711 cpu_R[dc->ra]);
4acb54ba
EI		 712 if (!dc->rd)
713 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
714}
715
716static void dec_barrel(DisasContext *dc)
717{
718 TCGv t0;
719 unsigned int s, t;
720
1567a005 721 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 722 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 723 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
724 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
725 t_gen_raise_exception(dc, EXCP_HW_EXCP);
726 return;
727 }
728
4acb54ba
EI		 729 s = dc->imm & (1 << 10);
730 t = dc->imm & (1 << 9);
731
732 LOG_DIS("bs%s%s r%d r%d r%d\n",
733 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
734
735 t0 = tcg_temp_new();
736
737 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
738 tcg_gen_andi_tl(t0, t0, 31);
739
740 if (s)
741 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
742 else {
743 if (t)
744 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
745 else
746 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
747 }
748}
749
750static void dec_bit(DisasContext *dc)
751{
752 TCGv t0, t1;
753 unsigned int op;
1567a005 754 int mem_index = cpu_mmu_index(dc->env);
4acb54ba 755
ace2e4da 756 op = dc->ir & ((1 << 9) - 1);
4acb54ba
EI		 757 switch (op) {
758 case 0x21:
759 /* src. */
760 t0 = tcg_temp_new();
761
762 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
763 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
764 if (dc->rd) {
765 t1 = tcg_temp_new();
766 read_carry(dc, t1);
767 tcg_gen_shli_tl(t1, t1, 31);
768
769 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
770 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
771 tcg_temp_free(t1);
772 }
773
774 /* Update carry. */
775 write_carry(dc, t0);
776 tcg_temp_free(t0);
777 break;
778
779 case 0x1:
780 case 0x41:
781 /* srl. */
782 t0 = tcg_temp_new();
783 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
784
785 /* Update carry. */
786 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
787 write_carry(dc, t0);
788 tcg_temp_free(t0);
789 if (dc->rd) {
790 if (op == 0x41)
791 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
792 else
793 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
794 }
795 break;
796 case 0x60:
797 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
798 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
799 break;
800 case 0x61:
801 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
802 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
803 break;
804 case 0x64:
f062a3c7
EI		 805 case 0x66:
806 case 0x74:
807 case 0x76:
4acb54ba
EI		 808 /* wdc. */
809 LOG_DIS("wdc r%d\n", dc->ra);
1567a005
EI		 810 if ((dc->tb_flags & MSR_EE_FLAG)
811 && mem_index == MMU_USER_IDX) {
812 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
813 t_gen_raise_exception(dc, EXCP_HW_EXCP);
814 return;
815 }
4acb54ba
EI		 816 break;
817 case 0x68:
818 /* wic. */
819 LOG_DIS("wic r%d\n", dc->ra);
1567a005
EI		 820 if ((dc->tb_flags & MSR_EE_FLAG)
821 && mem_index == MMU_USER_IDX) {
822 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
823 t_gen_raise_exception(dc, EXCP_HW_EXCP);
824 return;
825 }
4acb54ba 826 break;
48b5e96f
EI		 827 case 0xe0:
828 if ((dc->tb_flags & MSR_EE_FLAG)
829 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
830 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
831 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
832 t_gen_raise_exception(dc, EXCP_HW_EXCP);
833 }
834 if (dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR) {
835 gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]);
836 }
837 break;
ace2e4da
PC		 838 case 0x1e0:
839 /* swapb */
840 LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra);
841 tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
842 break;
b8c6a5d9 843 case 0x1e2:
ace2e4da
PC		 844 /*swaph */
845 LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra);
846 tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16);
847 break;
4acb54ba
EI		 848 default:
849 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
850 dc->pc, op, dc->rd, dc->ra, dc->rb);
851 break;
852 }
853}
854
855static inline void sync_jmpstate(DisasContext *dc)
856{
844bab60
EI		 857 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
858 if (dc->jmp == JMP_DIRECT) {
859 tcg_gen_movi_tl(env_btaken, 1);
860 }
23979dc5
EI		 861 dc->jmp = JMP_INDIRECT;
862 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
4acb54ba
EI		 863 }
864}
865
866static void dec_imm(DisasContext *dc)
867{
868 LOG_DIS("imm %x\n", dc->imm << 16);
869 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
870 dc->tb_flags |= IMM_FLAG;
871 dc->clear_imm = 0;
872}
873
874static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
875 unsigned int size)
876{
877 int mem_index = cpu_mmu_index(dc->env);
878
879 if (size == 1) {
880 tcg_gen_qemu_ld8u(dst, addr, mem_index);
881 } else if (size == 2) {
882 tcg_gen_qemu_ld16u(dst, addr, mem_index);
883 } else if (size == 4) {
884 tcg_gen_qemu_ld32u(dst, addr, mem_index);
885 } else
886 cpu_abort(dc->env, "Incorrect load size %d\n", size);
887}
888
889static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
890{
891 unsigned int extimm = dc->tb_flags & IMM_FLAG;
5818dee5
EI		 892 /* Should be set to one if r1 is used by loadstores. */
893 int stackprot = 0;
894
895 /* All load/stores use ra. */
896 if (dc->ra == 1) {
897 stackprot = 1;
898 }
4acb54ba 899
9ef55357 900 /* Treat the common cases first. */
4acb54ba 901 if (!dc->type_b) {
4b5ef0b5
EI		 902 /* If any of the regs is r0, return a ptr to the other. */
903 if (dc->ra == 0) {
904 return &cpu_R[dc->rb];
905 } else if (dc->rb == 0) {
906 return &cpu_R[dc->ra];
907 }
908
5818dee5
EI		 909 if (dc->rb == 1) {
910 stackprot = 1;
911 }
912
4acb54ba
EI		 913 *t = tcg_temp_new();
914 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
5818dee5
EI		 915
916 if (stackprot) {
64254eba 917 gen_helper_stackprot(cpu_env, *t);
5818dee5 918 }
4acb54ba
EI		 919 return t;
920 }
921 /* Immediate. */
922 if (!extimm) {
923 if (dc->imm == 0) {
924 return &cpu_R[dc->ra];
925 }
926 *t = tcg_temp_new();
927 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
928 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
929 } else {
930 *t = tcg_temp_new();
931 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
932 }
933
5818dee5 934 if (stackprot) {
64254eba 935 gen_helper_stackprot(cpu_env, *t);
5818dee5 936 }
4acb54ba
EI		 937 return t;
938}
939
9f8beb66
EI		 940static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size)
941{
942 if (size == 4) {
943 tcg_gen_bswap32_tl(dst, src);
944 } else if (size == 2) {
945 TCGv t = tcg_temp_new();
946
947 /* bswap16 assumes the high bits are zero. */
948 tcg_gen_andi_tl(t, src, 0xffff);
949 tcg_gen_bswap16_tl(dst, t);
950 tcg_temp_free(t);
951 } else {
952 /* Ignore.
953 cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
954 */
955 }
956}
957
4acb54ba
EI		 958static void dec_load(DisasContext *dc)
959{
960 TCGv t, *addr;
8cc9b43f 961 unsigned int size, rev = 0, ex = 0;
4acb54ba
EI		 962
963 size = 1 << (dc->opcode & 3);
9f8beb66
EI		 964
965 if (!dc->type_b) {
966 rev = (dc->ir >> 9) & 1;
8cc9b43f 967 ex = (dc->ir >> 10) & 1;
9f8beb66
EI		 968 }
969
0187688f 970 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
97f90cbf 971 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
0187688f
EI		 972 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
973 t_gen_raise_exception(dc, EXCP_HW_EXCP);
974 return;
975 }
4acb54ba 976
8cc9b43f
PC		 977 LOG_DIS("l%d%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
978 ex ? "x" : "");
9f8beb66 979
4acb54ba
EI		 980 t_sync_flags(dc);
981 addr = compute_ldst_addr(dc, &t);
982
9f8beb66
EI		 983 /*
984 * When doing reverse accesses we need to do two things.
985 *
4ff9786c 986 * 1. Reverse the address wrt endianness.
9f8beb66
EI		 987 * 2. Byteswap the data lanes on the way back into the CPU core.
988 */
989 if (rev && size != 4) {
990 /* Endian reverse the address. t is addr. */
991 switch (size) {
992 case 1:
993 {
994 /* 00 -> 11
995 01 -> 10
996 10 -> 10
997 11 -> 00 */
998 TCGv low = tcg_temp_new();
999
1000 /* Force addr into the temp. */
1001 if (addr != &t) {
1002 t = tcg_temp_new();
1003 tcg_gen_mov_tl(t, *addr);
1004 addr = &t;
1005 }
1006
1007 tcg_gen_andi_tl(low, t, 3);
1008 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1009 tcg_gen_andi_tl(t, t, ~3);
1010 tcg_gen_or_tl(t, t, low);
9f8beb66
EI		 1011 tcg_gen_mov_tl(env_imm, t);
1012 tcg_temp_free(low);
1013 break;
1014 }
1015
1016 case 2:
1017 /* 00 -> 10
1018 10 -> 00. */
1019 /* Force addr into the temp. */
1020 if (addr != &t) {
1021 t = tcg_temp_new();
1022 tcg_gen_xori_tl(t, *addr, 2);
1023 addr = &t;
1024 } else {
1025 tcg_gen_xori_tl(t, t, 2);
1026 }
1027 break;
1028 default:
1029 cpu_abort(dc->env, "Invalid reverse size\n");
1030 break;
1031 }
1032 }
1033
8cc9b43f
PC		 1034 /* lwx does not throw unaligned access errors, so force alignment */
1035 if (ex) {
1036 /* Force addr into the temp. */
1037 if (addr != &t) {
1038 t = tcg_temp_new();
1039 tcg_gen_mov_tl(t, *addr);
1040 addr = &t;
1041 }
1042 tcg_gen_andi_tl(t, t, ~3);
1043 }
1044
4acb54ba
EI		 1045 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1046 sync_jmpstate(dc);
968a40f6
EI		 1047
1048 /* Verify alignment if needed. */
1049 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
a12f6507
EI		 1050 TCGv v = tcg_temp_new();
1051
1052 /*
1053 * Microblaze gives MMU faults priority over faults due to
1054 * unaligned addresses. That's why we speculatively do the load
1055 * into v. If the load succeeds, we verify alignment of the
1056 * address and if that succeeds we write into the destination reg.
1057 */
1058 gen_load(dc, v, *addr, size);
1059
1060 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
64254eba 1061 gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
3aa80988 1062 tcg_const_tl(0), tcg_const_tl(size - 1));
9f8beb66
EI		 1063 if (dc->rd) {
1064 if (rev) {
1065 dec_byteswap(dc, cpu_R[dc->rd], v, size);
1066 } else {
1067 tcg_gen_mov_tl(cpu_R[dc->rd], v);
1068 }
1069 }
a12f6507 1070 tcg_temp_free(v);
968a40f6 1071 } else {
a12f6507
EI		 1072 if (dc->rd) {
1073 gen_load(dc, cpu_R[dc->rd], *addr, size);
9f8beb66
EI		 1074 if (rev) {
1075 dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size);
1076 }
a12f6507 1077 } else {
9f8beb66 1078 /* We are loading into r0, no need to reverse. */
a12f6507
EI		 1079 gen_load(dc, env_imm, *addr, size);
1080 }
4acb54ba
EI		 1081 }
1082
8cc9b43f
PC		 1083 if (ex) { /* lwx */
1084 /* no support for for AXI exclusive so always clear C */
1085 write_carryi(dc, 0);
1086 tcg_gen_st_tl(*addr, cpu_env, offsetof(CPUMBState, res_addr));
1087 }
1088
4acb54ba
EI		 1089 if (addr == &t)
1090 tcg_temp_free(t);
1091}
1092
1093static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
1094 unsigned int size)
1095{
1096 int mem_index = cpu_mmu_index(dc->env);
1097
1098 if (size == 1)
1099 tcg_gen_qemu_st8(val, addr, mem_index);
1100 else if (size == 2) {
1101 tcg_gen_qemu_st16(val, addr, mem_index);
1102 } else if (size == 4) {
1103 tcg_gen_qemu_st32(val, addr, mem_index);
1104 } else
1105 cpu_abort(dc->env, "Incorrect store size %d\n", size);
1106}
1107
1108static void dec_store(DisasContext *dc)
1109{
083dbf48 1110 TCGv t, *addr, swx_addr, r_check;
8cc9b43f
PC		 1111 int swx_skip = 0;
1112 unsigned int size, rev = 0, ex = 0;
4acb54ba
EI		 1113
1114 size = 1 << (dc->opcode & 3);
9f8beb66
EI		 1115 if (!dc->type_b) {
1116 rev = (dc->ir >> 9) & 1;
8cc9b43f 1117 ex = (dc->ir >> 10) & 1;
9f8beb66 1118 }
4acb54ba 1119
0187688f 1120 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
97f90cbf 1121 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
0187688f
EI		 1122 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1123 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1124 return;
1125 }
1126
8cc9b43f
PC		 1127 LOG_DIS("s%d%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
1128 ex ? "x" : "");
4acb54ba
EI		 1129 t_sync_flags(dc);
1130 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1131 sync_jmpstate(dc);
1132 addr = compute_ldst_addr(dc, &t);
968a40f6 1133
083dbf48
PC		 1134 r_check = tcg_temp_new();
1135 swx_addr = tcg_temp_local_new();
8cc9b43f 1136 if (ex) { /* swx */
8cc9b43f
PC		 1137
1138 /* Force addr into the swx_addr. */
1139 tcg_gen_mov_tl(swx_addr, *addr);
1140 addr = &swx_addr;
1141 /* swx does not throw unaligned access errors, so force alignment */
1142 tcg_gen_andi_tl(swx_addr, swx_addr, ~3);
1143
1144 tcg_gen_ld_tl(r_check, cpu_env, offsetof(CPUMBState, res_addr));
1145 write_carryi(dc, 1);
1146 swx_skip = gen_new_label();
1147 tcg_gen_brcond_tl(TCG_COND_NE, r_check, swx_addr, swx_skip);
1148 write_carryi(dc, 0);
1149 }
1150
9f8beb66
EI		 1151 if (rev && size != 4) {
1152 /* Endian reverse the address. t is addr. */
1153 switch (size) {
1154 case 1:
1155 {
1156 /* 00 -> 11
1157 01 -> 10
1158 10 -> 10
1159 11 -> 00 */
1160 TCGv low = tcg_temp_new();
1161
1162 /* Force addr into the temp. */
1163 if (addr != &t) {
1164 t = tcg_temp_new();
1165 tcg_gen_mov_tl(t, *addr);
1166 addr = &t;
1167 }
1168
1169 tcg_gen_andi_tl(low, t, 3);
1170 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1171 tcg_gen_andi_tl(t, t, ~3);
1172 tcg_gen_or_tl(t, t, low);
9f8beb66
EI		 1173 tcg_gen_mov_tl(env_imm, t);
1174 tcg_temp_free(low);
1175 break;
1176 }
1177
1178 case 2:
1179 /* 00 -> 10
1180 10 -> 00. */
1181 /* Force addr into the temp. */
1182 if (addr != &t) {
1183 t = tcg_temp_new();
1184 tcg_gen_xori_tl(t, *addr, 2);
1185 addr = &t;
1186 } else {
1187 tcg_gen_xori_tl(t, t, 2);
1188 }
1189 break;
1190 default:
1191 cpu_abort(dc->env, "Invalid reverse size\n");
1192 break;
1193 }
1194
1195 if (size != 1) {
1196 TCGv bs_data = tcg_temp_new();
1197 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1198 gen_store(dc, *addr, bs_data, size);
1199 tcg_temp_free(bs_data);
1200 } else {
1201 gen_store(dc, *addr, cpu_R[dc->rd], size);
1202 }
1203 } else {
1204 if (rev) {
1205 TCGv bs_data = tcg_temp_new();
1206 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1207 gen_store(dc, *addr, bs_data, size);
1208 tcg_temp_free(bs_data);
1209 } else {
1210 gen_store(dc, *addr, cpu_R[dc->rd], size);
1211 }
1212 }
a12f6507 1213
968a40f6
EI		 1214 /* Verify alignment if needed. */
1215 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
a12f6507
EI		 1216 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1217 /* FIXME: if the alignment is wrong, we should restore the value
4abf79a4 1218 * in memory. One possible way to achieve this is to probe
9f8beb66
EI		 1219 * the MMU prior to the memaccess, thay way we could put
1220 * the alignment checks in between the probe and the mem
1221 * access.
a12f6507 1222 */
64254eba 1223 gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
3aa80988 1224 tcg_const_tl(1), tcg_const_tl(size - 1));
968a40f6 1225 }
083dbf48 1226
8cc9b43f
PC		 1227 if (ex) {
1228 gen_set_label(swx_skip);
8cc9b43f 1229 }
083dbf48
PC		 1230 tcg_temp_free(r_check);
1231 tcg_temp_free(swx_addr);
968a40f6 1232
4acb54ba
EI		 1233 if (addr == &t)
1234 tcg_temp_free(t);
1235}
1236
1237static inline void eval_cc(DisasContext *dc, unsigned int cc,
1238 TCGv d, TCGv a, TCGv b)
1239{
4acb54ba
EI		 1240 switch (cc) {
1241 case CC_EQ:
b2565c69 1242 tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b);
4acb54ba
EI		 1243 break;
1244 case CC_NE:
b2565c69 1245 tcg_gen_setcond_tl(TCG_COND_NE, d, a, b);
4acb54ba
EI		 1246 break;
1247 case CC_LT:
b2565c69 1248 tcg_gen_setcond_tl(TCG_COND_LT, d, a, b);
4acb54ba
EI		 1249 break;
1250 case CC_LE:
b2565c69 1251 tcg_gen_setcond_tl(TCG_COND_LE, d, a, b);
4acb54ba
EI		 1252 break;
1253 case CC_GE:
b2565c69 1254 tcg_gen_setcond_tl(TCG_COND_GE, d, a, b);
4acb54ba
EI		 1255 break;
1256 case CC_GT:
b2565c69 1257 tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
4acb54ba
EI		 1258 break;
1259 default:
1260 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
1261 break;
1262 }
1263}
1264
1265static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
1266{
1267 int l1;
1268
1269 l1 = gen_new_label();
1270 /* Conditional jmp. */
1271 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
1272 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
1273 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
1274 gen_set_label(l1);
1275}
1276
1277static void dec_bcc(DisasContext *dc)
1278{
1279 unsigned int cc;
1280 unsigned int dslot;
1281
1282 cc = EXTRACT_FIELD(dc->ir, 21, 23);
1283 dslot = dc->ir & (1 << 25);
1284 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
1285
1286 dc->delayed_branch = 1;
1287 if (dslot) {
1288 dc->delayed_branch = 2;
1289 dc->tb_flags |= D_FLAG;
1290 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
68cee38a 1291 cpu_env, offsetof(CPUMBState, bimm));
4acb54ba
EI		 1292 }
1293
61204ce8
EI		 1294 if (dec_alu_op_b_is_small_imm(dc)) {
1295 int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
1296
1297 tcg_gen_movi_tl(env_btarget, dc->pc + offset);
844bab60 1298 dc->jmp = JMP_DIRECT_CC;
23979dc5 1299 dc->jmp_pc = dc->pc + offset;
61204ce8 1300 } else {
23979dc5 1301 dc->jmp = JMP_INDIRECT;
61204ce8
EI		 1302 tcg_gen_movi_tl(env_btarget, dc->pc);
1303 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1304 }
61204ce8 1305 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
4acb54ba
EI		 1306}
1307
1308static void dec_br(DisasContext *dc)
1309{
9f6113c7 1310 unsigned int dslot, link, abs, mbar;
ff21f70a 1311 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 1312
1313 dslot = dc->ir & (1 << 20);
1314 abs = dc->ir & (1 << 19);
1315 link = dc->ir & (1 << 18);
9f6113c7
EI		 1316
1317 /* Memory barrier. */
1318 mbar = (dc->ir >> 16) & 31;
1319 if (mbar == 2 && dc->imm == 4) {
1320 LOG_DIS("mbar %d\n", dc->rd);
1321 /* Break the TB. */
1322 dc->cpustate_changed = 1;
1323 return;
1324 }
1325
4acb54ba
EI		 1326 LOG_DIS("br%s%s%s%s imm=%x\n",
1327 abs ? "a" : "", link ? "l" : "",
1328 dc->type_b ? "i" : "", dslot ? "d" : "",
1329 dc->imm);
1330
1331 dc->delayed_branch = 1;
1332 if (dslot) {
1333 dc->delayed_branch = 2;
1334 dc->tb_flags |= D_FLAG;
1335 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
68cee38a 1336 cpu_env, offsetof(CPUMBState, bimm));
4acb54ba
EI		 1337 }
1338 if (link && dc->rd)
1339 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
1340
1341 dc->jmp = JMP_INDIRECT;
1342 if (abs) {
1343 tcg_gen_movi_tl(env_btaken, 1);
1344 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
ff21f70a
EI		 1345 if (link && !dslot) {
1346 if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
1347 t_gen_raise_exception(dc, EXCP_BREAK);
1348 if (dc->imm == 0) {
1349 if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
1350 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1351 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1352 return;
1353 }
1354
1355 t_gen_raise_exception(dc, EXCP_DEBUG);
1356 }
1357 }
4acb54ba 1358 } else {
61204ce8
EI		 1359 if (dec_alu_op_b_is_small_imm(dc)) {
1360 dc->jmp = JMP_DIRECT;
1361 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
1362 } else {
4acb54ba
EI		 1363 tcg_gen_movi_tl(env_btaken, 1);
1364 tcg_gen_movi_tl(env_btarget, dc->pc);
1365 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
4acb54ba
EI		 1366 }
1367 }
1368}
1369
1370static inline void do_rti(DisasContext *dc)
1371{
1372 TCGv t0, t1;
1373 t0 = tcg_temp_new();
1374 t1 = tcg_temp_new();
1375 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1376 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1377 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1378
1379 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1380 tcg_gen_or_tl(t1, t1, t0);
1381 msr_write(dc, t1);
1382 tcg_temp_free(t1);
1383 tcg_temp_free(t0);
1384 dc->tb_flags &= ~DRTI_FLAG;
1385}
1386
1387static inline void do_rtb(DisasContext *dc)
1388{
1389 TCGv t0, t1;
1390 t0 = tcg_temp_new();
1391 t1 = tcg_temp_new();
1392 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1393 tcg_gen_shri_tl(t0, t1, 1);
1394 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1395
1396 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1397 tcg_gen_or_tl(t1, t1, t0);
1398 msr_write(dc, t1);
1399 tcg_temp_free(t1);
1400 tcg_temp_free(t0);
1401 dc->tb_flags &= ~DRTB_FLAG;
1402}
1403
1404static inline void do_rte(DisasContext *dc)
1405{
1406 TCGv t0, t1;
1407 t0 = tcg_temp_new();
1408 t1 = tcg_temp_new();
1409
1410 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1411 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1412 tcg_gen_shri_tl(t0, t1, 1);
1413 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1414
1415 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1416 tcg_gen_or_tl(t1, t1, t0);
1417 msr_write(dc, t1);
1418 tcg_temp_free(t1);
1419 tcg_temp_free(t0);
1420 dc->tb_flags &= ~DRTE_FLAG;
1421}
1422
1423static void dec_rts(DisasContext *dc)
1424{
1425 unsigned int b_bit, i_bit, e_bit;
1567a005 1426 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 1427
1428 i_bit = dc->ir & (1 << 21);
1429 b_bit = dc->ir & (1 << 22);
1430 e_bit = dc->ir & (1 << 23);
1431
1432 dc->delayed_branch = 2;
1433 dc->tb_flags |= D_FLAG;
1434 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
68cee38a 1435 cpu_env, offsetof(CPUMBState, bimm));
4acb54ba
EI		 1436
1437 if (i_bit) {
1438 LOG_DIS("rtid ir=%x\n", dc->ir);
1567a005
EI		 1439 if ((dc->tb_flags & MSR_EE_FLAG)
1440 && mem_index == MMU_USER_IDX) {
1441 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1442 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1443 }
4acb54ba
EI		 1444 dc->tb_flags |= DRTI_FLAG;
1445 } else if (b_bit) {
1446 LOG_DIS("rtbd ir=%x\n", dc->ir);
1567a005
EI		 1447 if ((dc->tb_flags & MSR_EE_FLAG)
1448 && mem_index == MMU_USER_IDX) {
1449 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1450 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1451 }
4acb54ba
EI		 1452 dc->tb_flags |= DRTB_FLAG;
1453 } else if (e_bit) {
1454 LOG_DIS("rted ir=%x\n", dc->ir);
1567a005
EI		 1455 if ((dc->tb_flags & MSR_EE_FLAG)
1456 && mem_index == MMU_USER_IDX) {
1457 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1458 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1459 }
4acb54ba
EI		 1460 dc->tb_flags |= DRTE_FLAG;
1461 } else
1462 LOG_DIS("rts ir=%x\n", dc->ir);
1463
23979dc5 1464 dc->jmp = JMP_INDIRECT;
4acb54ba
EI		 1465 tcg_gen_movi_tl(env_btaken, 1);
1466 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1467}
1468
97694c57
EI		 1469static int dec_check_fpuv2(DisasContext *dc)
1470{
1471 int r;
1472
1473 r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
1474
1475 if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
1476 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
1477 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1478 }
1479 return r;
1480}
1481
1567a005
EI		 1482static void dec_fpu(DisasContext *dc)
1483{
97694c57
EI		 1484 unsigned int fpu_insn;
1485
1567a005 1486 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 1487 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005 1488 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
97694c57 1489 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1567a005
EI		 1490 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1491 return;
1492 }
1493
97694c57
EI		 1494 fpu_insn = (dc->ir >> 7) & 7;
1495
1496 switch (fpu_insn) {
1497 case 0:
64254eba
BS		 1498 gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1499 cpu_R[dc->rb]);
97694c57
EI		 1500 break;
1501
1502 case 1:
64254eba
BS		 1503 gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1504 cpu_R[dc->rb]);
97694c57
EI		 1505 break;
1506
1507 case 2:
64254eba
BS		 1508 gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1509 cpu_R[dc->rb]);
97694c57
EI		 1510 break;
1511
1512 case 3:
64254eba
BS		 1513 gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1514 cpu_R[dc->rb]);
97694c57
EI		 1515 break;
1516
1517 case 4:
1518 switch ((dc->ir >> 4) & 7) {
1519 case 0:
64254eba 1520 gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1521 cpu_R[dc->ra], cpu_R[dc->rb]);
1522 break;
1523 case 1:
64254eba 1524 gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1525 cpu_R[dc->ra], cpu_R[dc->rb]);
1526 break;
1527 case 2:
64254eba 1528 gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1529 cpu_R[dc->ra], cpu_R[dc->rb]);
1530 break;
1531 case 3:
64254eba 1532 gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1533 cpu_R[dc->ra], cpu_R[dc->rb]);
1534 break;
1535 case 4:
64254eba 1536 gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1537 cpu_R[dc->ra], cpu_R[dc->rb]);
1538 break;
1539 case 5:
64254eba 1540 gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1541 cpu_R[dc->ra], cpu_R[dc->rb]);
1542 break;
1543 case 6:
64254eba 1544 gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1545 cpu_R[dc->ra], cpu_R[dc->rb]);
1546 break;
1547 default:
71547a3b
BS		 1548 qemu_log_mask(LOG_UNIMP,
1549 "unimplemented fcmp fpu_insn=%x pc=%x"
1550 " opc=%x\n",
1551 fpu_insn, dc->pc, dc->opcode);
97694c57
EI		 1552 dc->abort_at_next_insn = 1;
1553 break;
1554 }
1555 break;
1556
1557 case 5:
1558 if (!dec_check_fpuv2(dc)) {
1559 return;
1560 }
64254eba 1561 gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
97694c57
EI		 1562 break;
1563
1564 case 6:
1565 if (!dec_check_fpuv2(dc)) {
1566 return;
1567 }
64254eba 1568 gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
97694c57
EI		 1569 break;
1570
1571 case 7:
1572 if (!dec_check_fpuv2(dc)) {
1573 return;
1574 }
64254eba 1575 gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
97694c57
EI		 1576 break;
1577
1578 default:
71547a3b
BS		 1579 qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x"
1580 " opc=%x\n",
1581 fpu_insn, dc->pc, dc->opcode);
97694c57
EI		 1582 dc->abort_at_next_insn = 1;
1583 break;
1584 }
1567a005
EI		 1585}
1586
4acb54ba
EI		 1587static void dec_null(DisasContext *dc)
1588{
02b33596
EI		 1589 if ((dc->tb_flags & MSR_EE_FLAG)
1590 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1591 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1592 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1593 return;
1594 }
4acb54ba
EI		 1595 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1596 dc->abort_at_next_insn = 1;
1597}
1598
6d76d23e
EI		 1599/* Insns connected to FSL or AXI stream attached devices. */
1600static void dec_stream(DisasContext *dc)
1601{
1602 int mem_index = cpu_mmu_index(dc->env);
1603 TCGv_i32 t_id, t_ctrl;
1604 int ctrl;
1605
1606 LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put",
1607 dc->type_b ? "" : "d", dc->imm);
1608
1609 if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index == MMU_USER_IDX)) {
1610 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1611 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1612 return;
1613 }
1614
1615 t_id = tcg_temp_new();
1616 if (dc->type_b) {
1617 tcg_gen_movi_tl(t_id, dc->imm & 0xf);
1618 ctrl = dc->imm >> 10;
1619 } else {
1620 tcg_gen_andi_tl(t_id, cpu_R[dc->rb], 0xf);
1621 ctrl = dc->imm >> 5;
1622 }
1623
1624 t_ctrl = tcg_const_tl(ctrl);
1625
1626 if (dc->rd == 0) {
1627 gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]);
1628 } else {
1629 gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl);
1630 }
1631 tcg_temp_free(t_id);
1632 tcg_temp_free(t_ctrl);
1633}
1634
4acb54ba
EI		 1635static struct decoder_info {
1636 struct {
1637 uint32_t bits;
1638 uint32_t mask;
1639 };
1640 void (*dec)(DisasContext *dc);
1641} decinfo[] = {
1642 {DEC_ADD, dec_add},
1643 {DEC_SUB, dec_sub},
1644 {DEC_AND, dec_and},
1645 {DEC_XOR, dec_xor},
1646 {DEC_OR, dec_or},
1647 {DEC_BIT, dec_bit},
1648 {DEC_BARREL, dec_barrel},
1649 {DEC_LD, dec_load},
1650 {DEC_ST, dec_store},
1651 {DEC_IMM, dec_imm},
1652 {DEC_BR, dec_br},
1653 {DEC_BCC, dec_bcc},
1654 {DEC_RTS, dec_rts},
1567a005 1655 {DEC_FPU, dec_fpu},
4acb54ba
EI		 1656 {DEC_MUL, dec_mul},
1657 {DEC_DIV, dec_div},
1658 {DEC_MSR, dec_msr},
6d76d23e 1659 {DEC_STREAM, dec_stream},
4acb54ba
EI		 1660 {{0, 0}, dec_null}
1661};
1662
64254eba 1663static inline void decode(DisasContext *dc, uint32_t ir)
4acb54ba 1664{
4acb54ba
EI		 1665 int i;
1666
fdefe51c 1667 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4acb54ba 1668 tcg_gen_debug_insn_start(dc->pc);
fdefe51c 1669 }
4acb54ba 1670
64254eba 1671 dc->ir = ir;
4acb54ba
EI		 1672 LOG_DIS("%8.8x\t", dc->ir);
1673
1674 if (dc->ir)
1675 dc->nr_nops = 0;
1676 else {
1567a005 1677 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf
EI		 1678 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1679 && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1567a005
EI		 1680 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1681 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1682 return;
1683 }
1684
4acb54ba
EI		 1685 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1686 dc->nr_nops++;
1687 if (dc->nr_nops > 4)
1688 cpu_abort(dc->env, "fetching nop sequence\n");
1689 }
1690 /* bit 2 seems to indicate insn type. */
1691 dc->type_b = ir & (1 << 29);
1692
1693 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1694 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1695 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1696 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1697 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1698
1699 /* Large switch for all insns. */
1700 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1701 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1702 decinfo[i].dec(dc);
1703 break;
1704 }
1705 }
1706}
1707
68cee38a 1708static void check_breakpoint(CPUMBState *env, DisasContext *dc)
4acb54ba
EI		 1709{
1710 CPUBreakpoint *bp;
1711
72cf2d4f
BS		 1712 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1713 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4acb54ba
EI		 1714 if (bp->pc == dc->pc) {
1715 t_gen_raise_exception(dc, EXCP_DEBUG);
1716 dc->is_jmp = DISAS_UPDATE;
1717 }
1718 }
1719 }
1720}
1721
1722/* generate intermediate code for basic block 'tb'. */
1723static void
68cee38a 1724gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb,
4acb54ba
EI		 1725 int search_pc)
1726{
1727 uint16_t *gen_opc_end;
1728 uint32_t pc_start;
1729 int j, lj;
1730 struct DisasContext ctx;
1731 struct DisasContext *dc = &ctx;
1732 uint32_t next_page_start, org_flags;
1733 target_ulong npc;
1734 int num_insns;
1735 int max_insns;
1736
1737 qemu_log_try_set_file(stderr);
1738
1739 pc_start = tb->pc;
1740 dc->env = env;
1741 dc->tb = tb;
1742 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1743
92414b31 1744 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4acb54ba
EI		 1745
1746 dc->is_jmp = DISAS_NEXT;
1747 dc->jmp = 0;
1748 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
23979dc5
EI		 1749 if (dc->delayed_branch) {
1750 dc->jmp = JMP_INDIRECT;
1751 }
4acb54ba 1752 dc->pc = pc_start;
4acb54ba
EI		 1753 dc->singlestep_enabled = env->singlestep_enabled;
1754 dc->cpustate_changed = 0;
1755 dc->abort_at_next_insn = 0;
1756 dc->nr_nops = 0;
1757
1758 if (pc_start & 3)
1759 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1760
1761 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1762#if !SIM_COMPAT
1763 qemu_log("--------------\n");
1764 log_cpu_state(env, 0);
1765#endif
1766 }
1767
1768 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1769 lj = -1;
1770 num_insns = 0;
1771 max_insns = tb->cflags & CF_COUNT_MASK;
1772 if (max_insns == 0)
1773 max_insns = CF_COUNT_MASK;
1774
1775 gen_icount_start();
1776 do
1777 {
1778#if SIM_COMPAT
1779 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1780 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1781 gen_helper_debug();
1782 }
1783#endif
1784 check_breakpoint(env, dc);
1785
1786 if (search_pc) {
92414b31 1787 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4acb54ba
EI		 1788 if (lj < j) {
1789 lj++;
1790 while (lj < j)
1791 gen_opc_instr_start[lj++] = 0;
1792 }
1793 gen_opc_pc[lj] = dc->pc;
1794 gen_opc_instr_start[lj] = 1;
1795 gen_opc_icount[lj] = num_insns;
1796 }
1797
1798 /* Pretty disas. */
1799 LOG_DIS("%8.8x:\t", dc->pc);
1800
1801 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1802 gen_io_start();
1803
1804 dc->clear_imm = 1;
64254eba 1805 decode(dc, cpu_ldl_code(env, dc->pc));
4acb54ba
EI		 1806 if (dc->clear_imm)
1807 dc->tb_flags &= ~IMM_FLAG;
4acb54ba
EI		 1808 dc->pc += 4;
1809 num_insns++;
1810
1811 if (dc->delayed_branch) {
1812 dc->delayed_branch--;
1813 if (!dc->delayed_branch) {
1814 if (dc->tb_flags & DRTI_FLAG)
1815 do_rti(dc);
1816 if (dc->tb_flags & DRTB_FLAG)
1817 do_rtb(dc);
1818 if (dc->tb_flags & DRTE_FLAG)
1819 do_rte(dc);
1820 /* Clear the delay slot flag. */
1821 dc->tb_flags &= ~D_FLAG;
1822 /* If it is a direct jump, try direct chaining. */
23979dc5 1823 if (dc->jmp == JMP_INDIRECT) {
4acb54ba
EI		 1824 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1825 dc->is_jmp = DISAS_JUMP;
23979dc5 1826 } else if (dc->jmp == JMP_DIRECT) {
844bab60
EI		 1827 t_sync_flags(dc);
1828 gen_goto_tb(dc, 0, dc->jmp_pc);
1829 dc->is_jmp = DISAS_TB_JUMP;
1830 } else if (dc->jmp == JMP_DIRECT_CC) {
23979dc5
EI		 1831 int l1;
1832
1833 t_sync_flags(dc);
1834 l1 = gen_new_label();
1835 /* Conditional jmp. */
1836 tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
1837 gen_goto_tb(dc, 1, dc->pc);
1838 gen_set_label(l1);
1839 gen_goto_tb(dc, 0, dc->jmp_pc);
1840
1841 dc->is_jmp = DISAS_TB_JUMP;
4acb54ba
EI		 1842 }
1843 break;
1844 }
1845 }
1846 if (env->singlestep_enabled)
1847 break;
1848 } while (!dc->is_jmp && !dc->cpustate_changed
efd7f486 1849 && tcg_ctx.gen_opc_ptr < gen_opc_end
4acb54ba
EI		 1850 && !singlestep
1851 && (dc->pc < next_page_start)
1852 && num_insns < max_insns);
1853
1854 npc = dc->pc;
844bab60 1855 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
4acb54ba
EI		 1856 if (dc->tb_flags & D_FLAG) {
1857 dc->is_jmp = DISAS_UPDATE;
1858 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1859 sync_jmpstate(dc);
1860 } else
1861 npc = dc->jmp_pc;
1862 }
1863
1864 if (tb->cflags & CF_LAST_IO)
1865 gen_io_end();
1866 /* Force an update if the per-tb cpu state has changed. */
1867 if (dc->is_jmp == DISAS_NEXT
1868 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1869 dc->is_jmp = DISAS_UPDATE;
1870 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1871 }
1872 t_sync_flags(dc);
1873
1874 if (unlikely(env->singlestep_enabled)) {
6c5f738d
EI		 1875 TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
1876
1877 if (dc->is_jmp != DISAS_JUMP) {
4acb54ba 1878 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
6c5f738d 1879 }
64254eba 1880 gen_helper_raise_exception(cpu_env, tmp);
6c5f738d 1881 tcg_temp_free_i32(tmp);
4acb54ba
EI		 1882 } else {
1883 switch(dc->is_jmp) {
1884 case DISAS_NEXT:
1885 gen_goto_tb(dc, 1, npc);
1886 break;
1887 default:
1888 case DISAS_JUMP:
1889 case DISAS_UPDATE:
1890 /* indicate that the hash table must be used
1891 to find the next TB */
1892 tcg_gen_exit_tb(0);
1893 break;
1894 case DISAS_TB_JUMP:
1895 /* nothing more to generate */
1896 break;
1897 }
1898 }
1899 gen_icount_end(tb, num_insns);
efd7f486 1900 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4acb54ba 1901 if (search_pc) {
92414b31 1902 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4acb54ba
EI		 1903 lj++;
1904 while (lj <= j)
1905 gen_opc_instr_start[lj++] = 0;
1906 } else {
1907 tb->size = dc->pc - pc_start;
1908 tb->icount = num_insns;
1909 }
1910
1911#ifdef DEBUG_DISAS
1912#if !SIM_COMPAT
1913 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1914 qemu_log("\n");
1915#if DISAS_GNU
f4359b9f 1916 log_target_disas(env, pc_start, dc->pc - pc_start, 0);
4acb54ba 1917#endif
e6aa0f11 1918 qemu_log("\nisize=%d osize=%td\n",
92414b31
EV		 1919 dc->pc - pc_start, tcg_ctx.gen_opc_ptr -
1920 tcg_ctx.gen_opc_buf);
4acb54ba
EI		 1921 }
1922#endif
1923#endif
1924 assert(!dc->abort_at_next_insn);
1925}
1926
68cee38a 1927void gen_intermediate_code (CPUMBState *env, struct TranslationBlock *tb)
4acb54ba
EI		 1928{
1929 gen_intermediate_code_internal(env, tb, 0);
1930}
1931
68cee38a 1932void gen_intermediate_code_pc (CPUMBState *env, struct TranslationBlock *tb)
4acb54ba
EI		 1933{
1934 gen_intermediate_code_internal(env, tb, 1);
1935}
1936
68cee38a 1937void cpu_dump_state (CPUMBState *env, FILE *f, fprintf_function cpu_fprintf,
4acb54ba
EI		 1938 int flags)
1939{
1940 int i;
1941
1942 if (!env || !f)
1943 return;
1944
1945 cpu_fprintf(f, "IN: PC=%x %s\n",
1946 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
97694c57 1947 cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
4c24aa0a 1948 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
97694c57 1949 env->debug, env->imm, env->iflags, env->sregs[SR_FSR]);
17c52a43 1950 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
4acb54ba
EI		 1951 env->btaken, env->btarget,
1952 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
17c52a43
EI		 1953 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
1954 (env->sregs[SR_MSR] & MSR_EIP),
1955 (env->sregs[SR_MSR] & MSR_IE));
1956
4acb54ba
EI		 1957 for (i = 0; i < 32; i++) {
1958 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1959 if ((i + 1) % 4 == 0)
1960 cpu_fprintf(f, "\n");
1961 }
1962 cpu_fprintf(f, "\n\n");
1963}
1964
b33ab1f7 1965MicroBlazeCPU *cpu_mb_init(const char *cpu_model)
4acb54ba 1966{
b77f98ca 1967 MicroBlazeCPU *cpu;
4acb54ba
EI		 1968 static int tcg_initialized = 0;
1969 int i;
1970
b77f98ca 1971 cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
4acb54ba 1972
61b6208f 1973 cpu_reset(CPU(cpu));
b33ab1f7 1974 qemu_init_vcpu(&cpu->env);
4acb54ba 1975
b33ab1f7
AF		 1976 if (tcg_initialized) {
1977 return cpu;
1978 }
4acb54ba
EI		 1979
1980 tcg_initialized = 1;
1981
1982 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1983
1984 env_debug = tcg_global_mem_new(TCG_AREG0,
68cee38a 1985 offsetof(CPUMBState, debug),
4acb54ba
EI		 1986 "debug0");
1987 env_iflags = tcg_global_mem_new(TCG_AREG0,
68cee38a 1988 offsetof(CPUMBState, iflags),
4acb54ba
EI		 1989 "iflags");
1990 env_imm = tcg_global_mem_new(TCG_AREG0,
68cee38a 1991 offsetof(CPUMBState, imm),
4acb54ba
EI		 1992 "imm");
1993 env_btarget = tcg_global_mem_new(TCG_AREG0,
68cee38a 1994 offsetof(CPUMBState, btarget),
4acb54ba
EI		 1995 "btarget");
1996 env_btaken = tcg_global_mem_new(TCG_AREG0,
68cee38a 1997 offsetof(CPUMBState, btaken),
4acb54ba
EI		 1998 "btaken");
1999 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
2000 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
68cee38a 2001 offsetof(CPUMBState, regs[i]),
4acb54ba
EI		 2002 regnames[i]);
2003 }
2004 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
2005 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
68cee38a 2006 offsetof(CPUMBState, sregs[i]),
4acb54ba
EI		 2007 special_regnames[i]);
2008 }
2009#define GEN_HELPER 2
2010#include "helper.h"
2011
b33ab1f7 2012 return cpu;
4acb54ba
EI		 2013}
2014
68cee38a 2015void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos)
4acb54ba
EI		 2016{
2017 env->sregs[SR_PC] = gen_opc_pc[pc_pos];
2018}
Empty description
This page took 0.744404 seconds and 4 git commands to generate.