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1 | /* |
2 | * Sparc32 interrupt helpers | |
3 | * | |
4 | * Copyright (c) 2003-2005 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "cpu.h" | |
11e66bca | 21 | #include "trace.h" |
ab3b491f BS |
22 | |
23 | //#define DEBUG_PCALL | |
24 | ||
25 | #ifdef DEBUG_PCALL | |
26 | static const char * const excp_names[0x80] = { | |
27 | [TT_TFAULT] = "Instruction Access Fault", | |
28 | [TT_ILL_INSN] = "Illegal Instruction", | |
29 | [TT_PRIV_INSN] = "Privileged Instruction", | |
30 | [TT_NFPU_INSN] = "FPU Disabled", | |
31 | [TT_WIN_OVF] = "Window Overflow", | |
32 | [TT_WIN_UNF] = "Window Underflow", | |
33 | [TT_UNALIGNED] = "Unaligned Memory Access", | |
34 | [TT_FP_EXCP] = "FPU Exception", | |
35 | [TT_DFAULT] = "Data Access Fault", | |
36 | [TT_TOVF] = "Tag Overflow", | |
37 | [TT_EXTINT | 0x1] = "External Interrupt 1", | |
38 | [TT_EXTINT | 0x2] = "External Interrupt 2", | |
39 | [TT_EXTINT | 0x3] = "External Interrupt 3", | |
40 | [TT_EXTINT | 0x4] = "External Interrupt 4", | |
41 | [TT_EXTINT | 0x5] = "External Interrupt 5", | |
42 | [TT_EXTINT | 0x6] = "External Interrupt 6", | |
43 | [TT_EXTINT | 0x7] = "External Interrupt 7", | |
44 | [TT_EXTINT | 0x8] = "External Interrupt 8", | |
45 | [TT_EXTINT | 0x9] = "External Interrupt 9", | |
46 | [TT_EXTINT | 0xa] = "External Interrupt 10", | |
47 | [TT_EXTINT | 0xb] = "External Interrupt 11", | |
48 | [TT_EXTINT | 0xc] = "External Interrupt 12", | |
49 | [TT_EXTINT | 0xd] = "External Interrupt 13", | |
50 | [TT_EXTINT | 0xe] = "External Interrupt 14", | |
51 | [TT_EXTINT | 0xf] = "External Interrupt 15", | |
52 | [TT_TOVF] = "Tag Overflow", | |
53 | [TT_CODE_ACCESS] = "Instruction Access Error", | |
54 | [TT_DATA_ACCESS] = "Data Access Error", | |
55 | [TT_DIV_ZERO] = "Division By Zero", | |
56 | [TT_NCP_INSN] = "Coprocessor Disabled", | |
57 | }; | |
58 | #endif | |
59 | ||
60 | void do_interrupt(CPUState *env) | |
61 | { | |
62 | int cwp, intno = env->exception_index; | |
63 | ||
64 | #ifdef DEBUG_PCALL | |
65 | if (qemu_loglevel_mask(CPU_LOG_INT)) { | |
66 | static int count; | |
67 | const char *name; | |
68 | ||
69 | if (intno < 0 || intno >= 0x100) { | |
70 | name = "Unknown"; | |
71 | } else if (intno >= 0x80) { | |
72 | name = "Trap Instruction"; | |
73 | } else { | |
74 | name = excp_names[intno]; | |
75 | if (!name) { | |
76 | name = "Unknown"; | |
77 | } | |
78 | } | |
79 | ||
80 | qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n", | |
81 | count, name, intno, | |
82 | env->pc, | |
83 | env->npc, env->regwptr[6]); | |
84 | log_cpu_state(env, 0); | |
85 | #if 0 | |
86 | { | |
87 | int i; | |
88 | uint8_t *ptr; | |
89 | ||
90 | qemu_log(" code="); | |
91 | ptr = (uint8_t *)env->pc; | |
92 | for (i = 0; i < 16; i++) { | |
93 | qemu_log(" %02x", ldub(ptr + i)); | |
94 | } | |
95 | qemu_log("\n"); | |
96 | } | |
97 | #endif | |
98 | count++; | |
99 | } | |
100 | #endif | |
101 | #if !defined(CONFIG_USER_ONLY) | |
102 | if (env->psret == 0) { | |
103 | cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", | |
104 | env->exception_index); | |
105 | return; | |
106 | } | |
107 | #endif | |
108 | env->psret = 0; | |
109 | cwp = cpu_cwp_dec(env, env->cwp - 1); | |
110 | cpu_set_cwp(env, cwp); | |
111 | env->regwptr[9] = env->pc; | |
112 | env->regwptr[10] = env->npc; | |
113 | env->psrps = env->psrs; | |
114 | env->psrs = 1; | |
115 | env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); | |
116 | env->pc = env->tbr; | |
117 | env->npc = env->pc + 4; | |
118 | env->exception_index = -1; | |
119 | ||
120 | #if !defined(CONFIG_USER_ONLY) | |
121 | /* IRQ acknowledgment */ | |
122 | if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) { | |
79227036 | 123 | env->qemu_irq_ack(env, env->irq_manager, intno); |
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124 | } |
125 | #endif | |
126 | } | |
79227036 BS |
127 | |
128 | #if !defined(CONFIG_USER_ONLY) | |
129 | static void leon3_cache_control_int(CPUState *env) | |
130 | { | |
131 | uint32_t state = 0; | |
132 | ||
133 | if (env->cache_control & CACHE_CTRL_IF) { | |
134 | /* Instruction cache state */ | |
135 | state = env->cache_control & CACHE_STATE_MASK; | |
136 | if (state == CACHE_ENABLED) { | |
137 | state = CACHE_FROZEN; | |
11e66bca | 138 | trace_int_helper_icache_freeze(); |
79227036 BS |
139 | } |
140 | ||
141 | env->cache_control &= ~CACHE_STATE_MASK; | |
142 | env->cache_control |= state; | |
143 | } | |
144 | ||
145 | if (env->cache_control & CACHE_CTRL_DF) { | |
146 | /* Data cache state */ | |
147 | state = (env->cache_control >> 2) & CACHE_STATE_MASK; | |
148 | if (state == CACHE_ENABLED) { | |
149 | state = CACHE_FROZEN; | |
11e66bca | 150 | trace_int_helper_dcache_freeze(); |
79227036 BS |
151 | } |
152 | ||
153 | env->cache_control &= ~(CACHE_STATE_MASK << 2); | |
154 | env->cache_control |= (state << 2); | |
155 | } | |
156 | } | |
157 | ||
158 | void leon3_irq_manager(CPUState *env, void *irq_manager, int intno) | |
159 | { | |
160 | leon3_irq_ack(irq_manager, intno); | |
161 | leon3_cache_control_int(env); | |
162 | } | |
163 | #endif |