[qemu.git] / hw / isa.h

#ifndef HW_ISA_H
#define HW_ISA_H
/* ISA bus */

extern target_phys_addr_t isa_mem_base;

int register_ioport_read(int start, int length, int size,
                         IOPortReadFunc *func, void *opaque);
int register_ioport_write(int start, int length, int size,
                          IOPortWriteFunc *func, void *opaque);
void isa_unassign_ioport(int start, int length);

void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);

/* dma.c */
int DMA_get_channel_mode (int nchan);
int DMA_read_memory (int nchan, void *buf, int pos, int size);
int DMA_write_memory (int nchan, void *buf, int pos, int size);
void DMA_hold_DREQ (int nchan);
void DMA_release_DREQ (int nchan);
void DMA_schedule(int nchan);
void DMA_init (int high_page_enable);
void DMA_register_channel (int nchan,
                           DMA_transfer_handler transfer_handler,
                           void *opaque);
#endif
Commit	Line	Data
79383c9c BS	1	#ifndef HW_ISA_H
79383c9c BS	2	#define HW_ISA_H
87ecb68b PB	3	/* ISA bus */
	4
	5	extern target_phys_addr_t isa_mem_base;
	6
	7	int register_ioport_read(int start, int length, int size,
	8	IOPortReadFunc func, void opaque);
	9	int register_ioport_write(int start, int length, int size,
	10	IOPortWriteFunc func, void opaque);
	11	void isa_unassign_ioport(int start, int length);
	12
	13	void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
	14
	15	/* dma.c */
	16	int DMA_get_channel_mode (int nchan);
	17	int DMA_read_memory (int nchan, void *buf, int pos, int size);
	18	int DMA_write_memory (int nchan, void *buf, int pos, int size);
	19	void DMA_hold_DREQ (int nchan);
	20	void DMA_release_DREQ (int nchan);
	21	void DMA_schedule(int nchan);
87ecb68b PB	22	void DMA_init (int high_page_enable);
	23	void DMA_register_channel (int nchan,
	24	DMA_transfer_handler transfer_handler,
	25	void *opaque);
79383c9c	26	#endif