[qemu.git] / cpu.c

/*
 * Target-specific parts of the CPU object
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qapi/error.h"

#include "exec/target_page.h"
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
#include "migration/vmstate.h"
#ifdef CONFIG_USER_ONLY
#include "qemu.h"
#else
#include "hw/core/sysemu-cpu-ops.h"
#include "exec/address-spaces.h"
#endif
#include "sysemu/tcg.h"
#include "sysemu/kvm.h"
#include "sysemu/replay.h"
#include "exec/translate-all.h"
#include "exec/log.h"
#include "hw/core/accel-cpu.h"
#include "trace/trace-root.h"

uintptr_t qemu_host_page_size;
intptr_t qemu_host_page_mask;

#ifndef CONFIG_USER_ONLY
static int cpu_common_post_load(void *opaque, int version_id)
{
    CPUState *cpu = opaque;

    /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
       version_id is increased. */
    cpu->interrupt_request &= ~0x01;
    tlb_flush(cpu);

    /* loadvm has just updated the content of RAM, bypassing the
     * usual mechanisms that ensure we flush TBs for writes to
     * memory we've translated code from. So we must flush all TBs,
     * which will now be stale.
     */
    tb_flush(cpu);

    return 0;
}

static int cpu_common_pre_load(void *opaque)
{
    CPUState *cpu = opaque;

    cpu->exception_index = -1;

    return 0;
}

static bool cpu_common_exception_index_needed(void *opaque)
{
    CPUState *cpu = opaque;

    return tcg_enabled() && cpu->exception_index != -1;
}

static const VMStateDescription vmstate_cpu_common_exception_index = {
    .name = "cpu_common/exception_index",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = cpu_common_exception_index_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(exception_index, CPUState),
        VMSTATE_END_OF_LIST()
    }
};

static bool cpu_common_crash_occurred_needed(void *opaque)
{
    CPUState *cpu = opaque;

    return cpu->crash_occurred;
}

static const VMStateDescription vmstate_cpu_common_crash_occurred = {
    .name = "cpu_common/crash_occurred",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = cpu_common_crash_occurred_needed,
    .fields = (VMStateField[]) {
        VMSTATE_BOOL(crash_occurred, CPUState),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_cpu_common = {
    .name = "cpu_common",
    .version_id = 1,
    .minimum_version_id = 1,
    .pre_load = cpu_common_pre_load,
    .post_load = cpu_common_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(halted, CPUState),
        VMSTATE_UINT32(interrupt_request, CPUState),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_cpu_common_exception_index,
        &vmstate_cpu_common_crash_occurred,
        NULL
    }
};
#endif

void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
#ifndef CONFIG_USER_ONLY
    CPUClass *cc = CPU_GET_CLASS(cpu);
#endif

    cpu_list_add(cpu);
    if (!accel_cpu_realizefn(cpu, errp)) {
        return;
    }
    /* NB: errp parameter is unused currently */
    if (tcg_enabled()) {
        tcg_exec_realizefn(cpu, errp);
    }

#ifdef CONFIG_USER_ONLY
    assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
           qdev_get_vmsd(DEVICE(cpu))->unmigratable);
#else
    if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
        vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
    }
    if (cc->sysemu_ops->legacy_vmsd != NULL) {
        vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
    }
#endif /* CONFIG_USER_ONLY */
}

void cpu_exec_unrealizefn(CPUState *cpu)
{
#ifndef CONFIG_USER_ONLY
    CPUClass *cc = CPU_GET_CLASS(cpu);

    if (cc->sysemu_ops->legacy_vmsd != NULL) {
        vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
    }
    if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
        vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
    }
#endif
    if (tcg_enabled()) {
        tcg_exec_unrealizefn(cpu);
    }

    cpu_list_remove(cpu);
}

/*
 * This can't go in hw/core/cpu.c because that file is compiled only
 * once for both user-mode and system builds.
 */
static Property cpu_common_props[] = {
#ifdef CONFIG_USER_ONLY
    /*
     * Create a property for the user-only object, so users can
     * adjust prctl(PR_SET_UNALIGN) from the command-line.
     * Has no effect if the target does not support the feature.
     */
    DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
                     prctl_unalign_sigbus, false),
#else
    /*
     * Create a memory property for softmmu CPU object, so users can
     * wire up its memory.  The default if no link is set up is to use
     * the system address space.
     */
    DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
                     MemoryRegion *),
#endif
    DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
    DEFINE_PROP_END_OF_LIST(),
};

void cpu_class_init_props(DeviceClass *dc)
{
    device_class_set_props(dc, cpu_common_props);
}

void cpu_exec_initfn(CPUState *cpu)
{
    cpu->as = NULL;
    cpu->num_ases = 0;

#ifndef CONFIG_USER_ONLY
    cpu->thread_id = qemu_get_thread_id();
    cpu->memory = get_system_memory();
    object_ref(OBJECT(cpu->memory));
#endif
}

const char *parse_cpu_option(const char *cpu_option)
{
    ObjectClass *oc;
    CPUClass *cc;
    gchar **model_pieces;
    const char *cpu_type;

    model_pieces = g_strsplit(cpu_option, ",", 2);
    if (!model_pieces[0]) {
        error_report("-cpu option cannot be empty");
        exit(1);
    }

    oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
    if (oc == NULL) {
        error_report("unable to find CPU model '%s'", model_pieces[0]);
        g_strfreev(model_pieces);
        exit(EXIT_FAILURE);
    }

    cpu_type = object_class_get_name(oc);
    cc = CPU_CLASS(oc);
    cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
    g_strfreev(model_pieces);
    return cpu_type;
}

#if defined(CONFIG_USER_ONLY)
void tb_invalidate_phys_addr(target_ulong addr)
{
    mmap_lock();
    tb_invalidate_phys_page_range(addr, addr + 1);
    mmap_unlock();
}
#else
void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
{
    ram_addr_t ram_addr;
    MemoryRegion *mr;
    hwaddr l = 1;

    if (!tcg_enabled()) {
        return;
    }

    RCU_READ_LOCK_GUARD();
    mr = address_space_translate(as, addr, &addr, &l, false, attrs);
    if (!(memory_region_is_ram(mr)
          || memory_region_is_romd(mr))) {
        return;
    }
    ram_addr = memory_region_get_ram_addr(mr) + addr;
    tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
}
#endif

/* Add a breakpoint.  */
int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
                          CPUBreakpoint **breakpoint)
{
    CPUClass *cc = CPU_GET_CLASS(cpu);
    CPUBreakpoint *bp;

    if (cc->gdb_adjust_breakpoint) {
        pc = cc->gdb_adjust_breakpoint(cpu, pc);
    }

    bp = g_malloc(sizeof(*bp));

    bp->pc = pc;
    bp->flags = flags;

    /* keep all GDB-injected breakpoints in front */
    if (flags & BP_GDB) {
        QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
    } else {
        QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
    }

    if (breakpoint) {
        *breakpoint = bp;
    }

    trace_breakpoint_insert(cpu->cpu_index, pc, flags);
    return 0;
}

/* Remove a specific breakpoint.  */
int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
{
    CPUClass *cc = CPU_GET_CLASS(cpu);
    CPUBreakpoint *bp;

    if (cc->gdb_adjust_breakpoint) {
        pc = cc->gdb_adjust_breakpoint(cpu, pc);
    }

    QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
        if (bp->pc == pc && bp->flags == flags) {
            cpu_breakpoint_remove_by_ref(cpu, bp);
            return 0;
        }
    }
    return -ENOENT;
}

/* Remove a specific breakpoint by reference.  */
void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp)
{
    QTAILQ_REMOVE(&cpu->breakpoints, bp, entry);

    trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags);
    g_free(bp);
}

/* Remove all matching breakpoints. */
void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
{
    CPUBreakpoint *bp, *next;

    QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
        if (bp->flags & mask) {
            cpu_breakpoint_remove_by_ref(cpu, bp);
        }
    }
}

/* enable or disable single step mode. EXCP_DEBUG is returned by the
   CPU loop after each instruction */
void cpu_single_step(CPUState *cpu, int enabled)
{
    if (cpu->singlestep_enabled != enabled) {
        cpu->singlestep_enabled = enabled;
        if (kvm_enabled()) {
            kvm_update_guest_debug(cpu, 0);
        }
        trace_breakpoint_singlestep(cpu->cpu_index, enabled);
    }
}

void cpu_abort(CPUState *cpu, const char *fmt, ...)
{
    va_list ap;
    va_list ap2;

    va_start(ap, fmt);
    va_copy(ap2, ap);
    fprintf(stderr, "qemu: fatal: ");
    vfprintf(stderr, fmt, ap);
    fprintf(stderr, "\n");
    cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
    if (qemu_log_separate()) {
        FILE *logfile = qemu_log_lock();
        qemu_log("qemu: fatal: ");
        qemu_log_vprintf(fmt, ap2);
        qemu_log("\n");
        log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
        qemu_log_flush();
        qemu_log_unlock(logfile);
        qemu_log_close();
    }
    va_end(ap2);
    va_end(ap);
    replay_finish();
#if defined(CONFIG_USER_ONLY)
    {
        struct sigaction act;
        sigfillset(&act.sa_mask);
        act.sa_handler = SIG_DFL;
        act.sa_flags = 0;
        sigaction(SIGABRT, &act, NULL);
    }
#endif
    abort();
}

/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
                        void *ptr, target_ulong len, bool is_write)
{
    int flags;
    target_ulong l, page;
    void * p;
    uint8_t *buf = ptr;

    while (len > 0) {
        page = addr & TARGET_PAGE_MASK;
        l = (page + TARGET_PAGE_SIZE) - addr;
        if (l > len)
            l = len;
        flags = page_get_flags(page);
        if (!(flags & PAGE_VALID))
            return -1;
        if (is_write) {
            if (!(flags & PAGE_WRITE))
                return -1;
            /* XXX: this code should not depend on lock_user */
            if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
                return -1;
            memcpy(p, buf, l);
            unlock_user(p, addr, l);
        } else {
            if (!(flags & PAGE_READ))
                return -1;
            /* XXX: this code should not depend on lock_user */
            if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
                return -1;
            memcpy(buf, p, l);
            unlock_user(p, addr, 0);
        }
        len -= l;
        buf += l;
        addr += l;
    }
    return 0;
}
#endif

bool target_words_bigendian(void)
{
#if defined(TARGET_WORDS_BIGENDIAN)
    return true;
#else
    return false;
#endif
}

void page_size_init(void)
{
    /* NOTE: we can always suppose that qemu_host_page_size >=
       TARGET_PAGE_SIZE */
    if (qemu_host_page_size == 0) {
        qemu_host_page_size = qemu_real_host_page_size;
    }
    if (qemu_host_page_size < TARGET_PAGE_SIZE) {
        qemu_host_page_size = TARGET_PAGE_SIZE;
    }
    qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
}
Commit	Line	Data
d9f24bf5 PB	1	/*
	2	* Target-specific parts of the CPU object
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "qemu/osdep.h"
	21	#include "qemu-common.h"
	22	#include "qapi/error.h"
	23
	24	#include "exec/target_page.h"
	25	#include "hw/qdev-core.h"
	26	#include "hw/qdev-properties.h"
	27	#include "qemu/error-report.h"
	28	#include "migration/vmstate.h"
	29	#ifdef CONFIG_USER_ONLY
	30	#include "qemu.h"
	31	#else
8b80bd28	32	#include "hw/core/sysemu-cpu-ops.h"
d9f24bf5 PB	33	#include "exec/address-spaces.h"
	34	#endif
	35	#include "sysemu/tcg.h"
	36	#include "sysemu/kvm.h"
	37	#include "sysemu/replay.h"
3b9bd3f4	38	#include "exec/translate-all.h"
d9f24bf5	39	#include "exec/log.h"
30565f10	40	#include "hw/core/accel-cpu.h"
ad1a706f	41	#include "trace/trace-root.h"
d9f24bf5 PB	42
	43	uintptr_t qemu_host_page_size;
	44	intptr_t qemu_host_page_mask;
	45
	46	#ifndef CONFIG_USER_ONLY
	47	static int cpu_common_post_load(void *opaque, int version_id)
	48	{
	49	CPUState *cpu = opaque;
	50
	51	/* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
	52	version_id is increased. */
	53	cpu->interrupt_request &= ~0x01;
	54	tlb_flush(cpu);
	55
	56	/* loadvm has just updated the content of RAM, bypassing the
	57	* usual mechanisms that ensure we flush TBs for writes to
	58	* memory we've translated code from. So we must flush all TBs,
	59	* which will now be stale.
	60	*/
	61	tb_flush(cpu);
	62
	63	return 0;
	64	}
	65
	66	static int cpu_common_pre_load(void *opaque)
	67	{
	68	CPUState *cpu = opaque;
	69
	70	cpu->exception_index = -1;
	71
	72	return 0;
	73	}
	74
	75	static bool cpu_common_exception_index_needed(void *opaque)
	76	{
	77	CPUState *cpu = opaque;
	78
	79	return tcg_enabled() && cpu->exception_index != -1;
	80	}
	81
	82	static const VMStateDescription vmstate_cpu_common_exception_index = {
	83	.name = "cpu_common/exception_index",
	84	.version_id = 1,
	85	.minimum_version_id = 1,
	86	.needed = cpu_common_exception_index_needed,
	87	.fields = (VMStateField[]) {
	88	VMSTATE_INT32(exception_index, CPUState),
	89	VMSTATE_END_OF_LIST()
	90	}
	91	};
	92
	93	static bool cpu_common_crash_occurred_needed(void *opaque)
	94	{
	95	CPUState *cpu = opaque;
	96
	97	return cpu->crash_occurred;
	98	}
	99
	100	static const VMStateDescription vmstate_cpu_common_crash_occurred = {
	101	.name = "cpu_common/crash_occurred",
	102	.version_id = 1,
	103	.minimum_version_id = 1,
	104	.needed = cpu_common_crash_occurred_needed,
	105	.fields = (VMStateField[]) {
106	VMSTATE_BOOL(crash_occurred, CPUState),
107	VMSTATE_END_OF_LIST()
108	}
109	};
110
111	const VMStateDescription vmstate_cpu_common = {
112	.name = "cpu_common",
113	.version_id = 1,
114	.minimum_version_id = 1,
115	.pre_load = cpu_common_pre_load,
116	.post_load = cpu_common_post_load,
117	.fields = (VMStateField[]) {
118	VMSTATE_UINT32(halted, CPUState),
119	VMSTATE_UINT32(interrupt_request, CPUState),
120	VMSTATE_END_OF_LIST()
121	},
122	.subsections = (const VMStateDescription*[]) {
123	&vmstate_cpu_common_exception_index,
124	&vmstate_cpu_common_crash_occurred,
125	NULL
126	}
127	};
128	#endif
129
7df5e3d6	130	void cpu_exec_realizefn(CPUState cpu, Error *errp)
d9f24bf5	131	{
feece4d0	132	#ifndef CONFIG_USER_ONLY
d9f24bf5	133	CPUClass *cc = CPU_GET_CLASS(cpu);
feece4d0	134	#endif
d9f24bf5	135
7df5e3d6	136	cpu_list_add(cpu);
9ea057dc CF	137	if (!accel_cpu_realizefn(cpu, errp)) {
	138	return;
	139	}
7df5e3d6 CF	140	/* NB: errp parameter is unused currently */
	141	if (tcg_enabled()) {
	142	tcg_exec_realizefn(cpu, errp);
	143	}
7df5e3d6 CF	144
7df5e3d6 CF	145	#ifdef CONFIG_USER_ONLY
4336073b PMD	146	assert(qdev_get_vmsd(DEVICE(cpu)) == NULL \|\|
4336073b PMD	147	qdev_get_vmsd(DEVICE(cpu))->unmigratable);
7df5e3d6 CF	148	#else
	149	if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
	150	vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
	151	}
feece4d0 PMD	152	if (cc->sysemu_ops->legacy_vmsd != NULL) {
feece4d0 PMD	153	vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
7df5e3d6 CF	154	}
	155	#endif /* CONFIG_USER_ONLY */
	156	}
	157
	158	void cpu_exec_unrealizefn(CPUState *cpu)
	159	{
feece4d0	160	#ifndef CONFIG_USER_ONLY
7df5e3d6	161	CPUClass *cc = CPU_GET_CLASS(cpu);
d9f24bf5	162
feece4d0 PMD	163	if (cc->sysemu_ops->legacy_vmsd != NULL) {
feece4d0 PMD	164	vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
d9f24bf5 PB	165	}
	166	if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
	167	vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
	168	}
d9f24bf5	169	#endif
7df5e3d6 CF	170	if (tcg_enabled()) {
	171	tcg_exec_unrealizefn(cpu);
	172	}
7df5e3d6 CF	173
7df5e3d6 CF	174	cpu_list_remove(cpu);
d9f24bf5 PB	175	}
d9f24bf5 PB	176
6e8dcacd RH	177	/*
	178	* This can't go in hw/core/cpu.c because that file is compiled only
	179	* once for both user-mode and system builds.
	180	*/
995b87de	181	static Property cpu_common_props[] = {
6e8dcacd RH	182	#ifdef CONFIG_USER_ONLY
	183	/*
	184	* Create a property for the user-only object, so users can
	185	* adjust prctl(PR_SET_UNALIGN) from the command-line.
	186	* Has no effect if the target does not support the feature.
	187	*/
	188	DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
	189	prctl_unalign_sigbus, false),
	190	#else
995b87de	191	/*
6e8dcacd RH	192	* Create a memory property for softmmu CPU object, so users can
6e8dcacd RH	193	* wire up its memory. The default if no link is set up is to use
995b87de RH	194	* the system address space.
	195	*/
	196	DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
	197	MemoryRegion *),
	198	#endif
	199	DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
	200	DEFINE_PROP_END_OF_LIST(),
	201	};
	202
	203	void cpu_class_init_props(DeviceClass *dc)
	204	{
	205	device_class_set_props(dc, cpu_common_props);
	206	}
	207
d9f24bf5 PB	208	void cpu_exec_initfn(CPUState *cpu)
	209	{
	210	cpu->as = NULL;
	211	cpu->num_ases = 0;
	212
	213	#ifndef CONFIG_USER_ONLY
	214	cpu->thread_id = qemu_get_thread_id();
	215	cpu->memory = get_system_memory();
	216	object_ref(OBJECT(cpu->memory));
	217	#endif
	218	}
	219
d9f24bf5 PB	220	const char parse_cpu_option(const char cpu_option)
	221	{
	222	ObjectClass *oc;
	223	CPUClass *cc;
	224	gchar **model_pieces;
	225	const char *cpu_type;
	226
	227	model_pieces = g_strsplit(cpu_option, ",", 2);
	228	if (!model_pieces[0]) {
	229	error_report("-cpu option cannot be empty");
	230	exit(1);
	231	}
	232
	233	oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
	234	if (oc == NULL) {
	235	error_report("unable to find CPU model '%s'", model_pieces[0]);
	236	g_strfreev(model_pieces);
	237	exit(EXIT_FAILURE);
	238	}
	239
	240	cpu_type = object_class_get_name(oc);
	241	cc = CPU_CLASS(oc);
	242	cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
	243	g_strfreev(model_pieces);
	244	return cpu_type;
	245	}
	246
	247	#if defined(CONFIG_USER_ONLY)
	248	void tb_invalidate_phys_addr(target_ulong addr)
	249	{
	250	mmap_lock();
	251	tb_invalidate_phys_page_range(addr, addr + 1);
	252	mmap_unlock();
	253	}
d9f24bf5 PB	254	#else
	255	void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
	256	{
	257	ram_addr_t ram_addr;
	258	MemoryRegion *mr;
	259	hwaddr l = 1;
	260
	261	if (!tcg_enabled()) {
	262	return;
	263	}
	264
	265	RCU_READ_LOCK_GUARD();
	266	mr = address_space_translate(as, addr, &addr, &l, false, attrs);
	267	if (!(memory_region_is_ram(mr)
	268	\|\| memory_region_is_romd(mr))) {
	269	return;
	270	}
	271	ram_addr = memory_region_get_ram_addr(mr) + addr;
	272	tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
	273	}
d9f24bf5 PB	274	#endif
	275
	276	/* Add a breakpoint. */
	277	int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
	278	CPUBreakpoint **breakpoint)
	279	{
5bc31e94	280	CPUClass *cc = CPU_GET_CLASS(cpu);
d9f24bf5 PB	281	CPUBreakpoint *bp;
d9f24bf5 PB	282
5bc31e94 RH	283	if (cc->gdb_adjust_breakpoint) {
	284	pc = cc->gdb_adjust_breakpoint(cpu, pc);
	285	}
	286
d9f24bf5 PB	287	bp = g_malloc(sizeof(*bp));
	288
	289	bp->pc = pc;
	290	bp->flags = flags;
	291
	292	/* keep all GDB-injected breakpoints in front */
	293	if (flags & BP_GDB) {
	294	QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
	295	} else {
	296	QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
	297	}
	298
d9f24bf5 PB	299	if (breakpoint) {
	300	*breakpoint = bp;
	301	}
ad1a706f RH	302
ad1a706f RH	303	trace_breakpoint_insert(cpu->cpu_index, pc, flags);
d9f24bf5 PB	304	return 0;
	305	}
	306
	307	/* Remove a specific breakpoint. */
	308	int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
	309	{
5bc31e94	310	CPUClass *cc = CPU_GET_CLASS(cpu);
d9f24bf5 PB	311	CPUBreakpoint *bp;
d9f24bf5 PB	312
5bc31e94 RH	313	if (cc->gdb_adjust_breakpoint) {
	314	pc = cc->gdb_adjust_breakpoint(cpu, pc);
	315	}
	316
d9f24bf5 PB	317	QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
	318	if (bp->pc == pc && bp->flags == flags) {
	319	cpu_breakpoint_remove_by_ref(cpu, bp);
	320	return 0;
	321	}
	322	}
	323	return -ENOENT;
	324	}
	325
	326	/* Remove a specific breakpoint by reference. */
ad1a706f	327	void cpu_breakpoint_remove_by_ref(CPUState cpu, CPUBreakpoint bp)
d9f24bf5	328	{
ad1a706f	329	QTAILQ_REMOVE(&cpu->breakpoints, bp, entry);
d9f24bf5	330
ad1a706f RH	331	trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags);
ad1a706f RH	332	g_free(bp);
d9f24bf5 PB	333	}
	334
	335	/* Remove all matching breakpoints. */
	336	void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
	337	{
	338	CPUBreakpoint bp, next;
	339
	340	QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
	341	if (bp->flags & mask) {
	342	cpu_breakpoint_remove_by_ref(cpu, bp);
	343	}
	344	}
	345	}
	346
	347	/* enable or disable single step mode. EXCP_DEBUG is returned by the
	348	CPU loop after each instruction */
	349	void cpu_single_step(CPUState *cpu, int enabled)
	350	{
	351	if (cpu->singlestep_enabled != enabled) {
	352	cpu->singlestep_enabled = enabled;
	353	if (kvm_enabled()) {
	354	kvm_update_guest_debug(cpu, 0);
d9f24bf5	355	}
ad1a706f	356	trace_breakpoint_singlestep(cpu->cpu_index, enabled);
d9f24bf5 PB	357	}
	358	}
	359
	360	void cpu_abort(CPUState cpu, const char fmt, ...)
	361	{
	362	va_list ap;
	363	va_list ap2;
	364
	365	va_start(ap, fmt);
	366	va_copy(ap2, ap);
	367	fprintf(stderr, "qemu: fatal: ");
	368	vfprintf(stderr, fmt, ap);
	369	fprintf(stderr, "\n");
	370	cpu_dump_state(cpu, stderr, CPU_DUMP_FPU \| CPU_DUMP_CCOP);
	371	if (qemu_log_separate()) {
	372	FILE *logfile = qemu_log_lock();
	373	qemu_log("qemu: fatal: ");
	374	qemu_log_vprintf(fmt, ap2);
	375	qemu_log("\n");
	376	log_cpu_state(cpu, CPU_DUMP_FPU \| CPU_DUMP_CCOP);
	377	qemu_log_flush();
	378	qemu_log_unlock(logfile);
	379	qemu_log_close();
	380	}
	381	va_end(ap2);
	382	va_end(ap);
	383	replay_finish();
	384	#if defined(CONFIG_USER_ONLY)
	385	{
	386	struct sigaction act;
	387	sigfillset(&act.sa_mask);
	388	act.sa_handler = SIG_DFL;
	389	act.sa_flags = 0;
	390	sigaction(SIGABRT, &act, NULL);
	391	}
	392	#endif
	393	abort();
	394	}
	395
	396	/* physical memory access (slow version, mainly for debug) */
	397	#if defined(CONFIG_USER_ONLY)
	398	int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
	399	void *ptr, target_ulong len, bool is_write)
	400	{
	401	int flags;
	402	target_ulong l, page;
	403	void * p;
	404	uint8_t *buf = ptr;
	405
	406	while (len > 0) {
	407	page = addr & TARGET_PAGE_MASK;
	408	l = (page + TARGET_PAGE_SIZE) - addr;
	409	if (l > len)
	410	l = len;
	411	flags = page_get_flags(page);
	412	if (!(flags & PAGE_VALID))
	413	return -1;
	414	if (is_write) {
	415	if (!(flags & PAGE_WRITE))
	416	return -1;
	417	/* XXX: this code should not depend on lock_user */
	418	if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
	419	return -1;
	420	memcpy(p, buf, l);
421	unlock_user(p, addr, l);
422	} else {
423	if (!(flags & PAGE_READ))
424	return -1;
425	/* XXX: this code should not depend on lock_user */
426	if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
427	return -1;
428	memcpy(buf, p, l);
429	unlock_user(p, addr, 0);
430	}
431	len -= l;
432	buf += l;
433	addr += l;
434	}
435	return 0;
436	}
437	#endif
438
439	bool target_words_bigendian(void)
440	{
441	#if defined(TARGET_WORDS_BIGENDIAN)
442	return true;
443	#else
444	return false;
445	#endif
446	}
447
448	void page_size_init(void)
449	{
450	/* NOTE: we can always suppose that qemu_host_page_size >=
451	TARGET_PAGE_SIZE */
452	if (qemu_host_page_size == 0) {
453	qemu_host_page_size = qemu_real_host_page_size;
454	}
455	if (qemu_host_page_size < TARGET_PAGE_SIZE) {
456	qemu_host_page_size = TARGET_PAGE_SIZE;
457	}
458	qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
459	}