]> Git Repo - qemu.git/blame - target-mips/translate_init.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
target-mips: enable CM GCR in MIPS64R6-generic CPU
[qemu.git] / target-mips / translate_init.c
CommitLineData
33d68b5f
TS		 1/*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
33d68b5f
TS		 19 */
20
3953d786
TS		 21/* CPU / CPU family specific config register values. */
22
6d35524c 23/* Have config1, uncached coherency */
3953d786 24#define MIPS_CONFIG0 \
f45cb2f4 25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
3953d786 26
ae5d8053 27/* Have config2, no coprocessor2 attached, no MDMX support attached,
3953d786
TS		 28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30#define MIPS_CONFIG1 \
f45cb2f4 31((1U << CP0C1_M) | \
3953d786
TS		 32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36/* Have config3, no tertiary/secondary caches implemented */
37#define MIPS_CONFIG2 \
f45cb2f4 38((1U << CP0C2_M))
3953d786 39
6d35524c 40/* No config4, no DSP ASE, no large physaddr (PABITS),
ff2712ba 41 no external interrupt controller, no vectored interrupts,
ead9360e 42 no 1kb pages, no SmartMIPS ASE, no trace logic */
3953d786
TS		 43#define MIPS_CONFIG3 \
44((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
ead9360e 46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
3953d786 47
b4160af1
PJ		 48#define MIPS_CONFIG4 \
49((0 << CP0C4_M))
50
b4dd99a3
PJ		 51#define MIPS_CONFIG5 \
52((0 << CP0C5_M))
53
6d35524c
TS		 54/* MMU types, the first four entries have the same layout as the
55 CP0C0_MT field. */
56enum mips_mmu_types {
57 MMU_TYPE_NONE,
58 MMU_TYPE_R4000,
59 MMU_TYPE_RESERVED,
60 MMU_TYPE_FMT,
61 MMU_TYPE_R3000,
62 MMU_TYPE_R6000,
63 MMU_TYPE_R8000
64};
65
c227f099 66struct mips_def_t {
50366fe9 67 const char *name;
33d68b5f
TS		 68 int32_t CP0_PRid;
69 int32_t CP0_Config0;
70 int32_t CP0_Config1;
3953d786
TS		 71 int32_t CP0_Config2;
72 int32_t CP0_Config3;
b4160af1
PJ		 73 int32_t CP0_Config4;
74 int32_t CP0_Config4_rw_bitmask;
b4dd99a3
PJ		 75 int32_t CP0_Config5;
76 int32_t CP0_Config5_rw_bitmask;
34ee2ede
TS		 77 int32_t CP0_Config6;
78 int32_t CP0_Config7;
2a6e32dd
AJ		 79 target_ulong CP0_LLAddr_rw_bitmask;
80 int CP0_LLAddr_shift;
2f644545
TS		 81 int32_t SYNCI_Step;
82 int32_t CCRes;
ead9360e
TS		 83 int32_t CP0_Status_rw_bitmask;
84 int32_t CP0_TCStatus_rw_bitmask;
85 int32_t CP0_SRSCtl;
3953d786 86 int32_t CP1_fcr0;
ba5c79f2 87 int32_t CP1_fcr31;
863f264d 88 int32_t MSAIR;
e034e2c3 89 int32_t SEGBITS;
6d35524c 90 int32_t PABITS;
ead9360e
TS		 91 int32_t CP0_SRSConf0_rw_bitmask;
92 int32_t CP0_SRSConf0;
93 int32_t CP0_SRSConf1_rw_bitmask;
94 int32_t CP0_SRSConf1;
95 int32_t CP0_SRSConf2_rw_bitmask;
96 int32_t CP0_SRSConf2;
97 int32_t CP0_SRSConf3_rw_bitmask;
98 int32_t CP0_SRSConf3;
99 int32_t CP0_SRSConf4_rw_bitmask;
100 int32_t CP0_SRSConf4;
7207c7f9
LA		 101 int32_t CP0_PageGrain_rw_bitmask;
102 int32_t CP0_PageGrain;
e189e748 103 int insn_flags;
6d35524c 104 enum mips_mmu_types mmu_type;
33d68b5f
TS		 105};
106
107/*****************************************************************************/
108/* MIPS CPU definitions */
c227f099 109static const mips_def_t mips_defs[] =
33d68b5f 110{
33d68b5f
TS		 111 {
112 .name = "4Kc",
113 .CP0_PRid = 0x00018000,
6d35524c 114 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
ae5d8053 115 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
6958549d 116 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
d19954f4 117 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
ab3aee26 118 (0 << CP0C1_CA),
3953d786
TS		 119 .CP0_Config2 = MIPS_CONFIG2,
120 .CP0_Config3 = MIPS_CONFIG3,
2a6e32dd
AJ		 121 .CP0_LLAddr_rw_bitmask = 0,
122 .CP0_LLAddr_shift = 4,
2f644545
TS		 123 .SYNCI_Step = 32,
124 .CCRes = 2,
ead9360e 125 .CP0_Status_rw_bitmask = 0x1278FF17,
6d35524c
TS		 126 .SEGBITS = 32,
127 .PABITS = 32,
73642f5b 128 .insn_flags = CPU_MIPS32,
6d35524c 129 .mmu_type = MMU_TYPE_R4000,
33d68b5f 130 },
8d162c2b
TS		 131 {
132 .name = "4Km",
133 .CP0_PRid = 0x00018300,
134 /* Config1 implemented, fixed mapping MMU,
135 no virtual icache, uncached coherency. */
6d35524c 136 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
8d162c2b 137 .CP0_Config1 = MIPS_CONFIG1 |
6958549d 138 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
d19954f4
NF		 139 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
140 (1 << CP0C1_CA),
8d162c2b
TS		 141 .CP0_Config2 = MIPS_CONFIG2,
142 .CP0_Config3 = MIPS_CONFIG3,
2a6e32dd
AJ		 143 .CP0_LLAddr_rw_bitmask = 0,
144 .CP0_LLAddr_shift = 4,
8d162c2b
TS		 145 .SYNCI_Step = 32,
146 .CCRes = 2,
147 .CP0_Status_rw_bitmask = 0x1258FF17,
6d35524c
TS		 148 .SEGBITS = 32,
149 .PABITS = 32,
8d162c2b 150 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
6d35524c 151 .mmu_type = MMU_TYPE_FMT,
8d162c2b 152 },
33d68b5f 153 {
34ee2ede 154 .name = "4KEcR1",
33d68b5f 155 .CP0_PRid = 0x00018400,
6d35524c 156 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
ae5d8053 157 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
6958549d 158 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
d19954f4 159 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
ab3aee26 160 (0 << CP0C1_CA),
34ee2ede
TS		 161 .CP0_Config2 = MIPS_CONFIG2,
162 .CP0_Config3 = MIPS_CONFIG3,
2a6e32dd
AJ		 163 .CP0_LLAddr_rw_bitmask = 0,
164 .CP0_LLAddr_shift = 4,
2f644545
TS		 165 .SYNCI_Step = 32,
166 .CCRes = 2,
ead9360e 167 .CP0_Status_rw_bitmask = 0x1278FF17,
6d35524c
TS		 168 .SEGBITS = 32,
169 .PABITS = 32,
73642f5b 170 .insn_flags = CPU_MIPS32,
6d35524c 171 .mmu_type = MMU_TYPE_R4000,
34ee2ede 172 },
8d162c2b
TS		 173 {
174 .name = "4KEmR1",
175 .CP0_PRid = 0x00018500,
6d35524c 176 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
8d162c2b 177 .CP0_Config1 = MIPS_CONFIG1 |
6958549d 178 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
d19954f4
NF		 179 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
180 (1 << CP0C1_CA),
8d162c2b
TS		 181 .CP0_Config2 = MIPS_CONFIG2,
182 .CP0_Config3 = MIPS_CONFIG3,
2a6e32dd
AJ		 183 .CP0_LLAddr_rw_bitmask = 0,
184 .CP0_LLAddr_shift = 4,
8d162c2b
TS		 185 .SYNCI_Step = 32,
186 .CCRes = 2,
187 .CP0_Status_rw_bitmask = 0x1258FF17,
6d35524c
TS		 188 .SEGBITS = 32,
189 .PABITS = 32,
8d162c2b 190 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
6d35524c 191 .mmu_type = MMU_TYPE_FMT,
8d162c2b 192 },
34ee2ede
TS		 193 {
194 .name = "4KEc",
195 .CP0_PRid = 0x00019000,
6d35524c
TS		 196 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
197 (MMU_TYPE_R4000 << CP0C0_MT),
ae5d8053 198 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
6958549d 199 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
d19954f4 200 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
ab3aee26 201 (0 << CP0C1_CA),
34ee2ede 202 .CP0_Config2 = MIPS_CONFIG2,
ead9360e 203 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
2a6e32dd
AJ		 204 .CP0_LLAddr_rw_bitmask = 0,
205 .CP0_LLAddr_shift = 4,
2f644545
TS		 206 .SYNCI_Step = 32,
207 .CCRes = 2,
ead9360e 208 .CP0_Status_rw_bitmask = 0x1278FF17,
6d35524c
TS		 209 .SEGBITS = 32,
210 .PABITS = 32,
73642f5b 211 .insn_flags = CPU_MIPS32R2,
6d35524c 212 .mmu_type = MMU_TYPE_R4000,
34ee2ede 213 },
3e4587d5
TS		 214 {
215 .name = "4KEm",
216 .CP0_PRid = 0x00019100,
6d35524c 217 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
6958549d 218 (MMU_TYPE_FMT << CP0C0_MT),
3e4587d5 219 .CP0_Config1 = MIPS_CONFIG1 |
6958549d 220 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
d19954f4
NF		 221 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
222 (1 << CP0C1_CA),
3e4587d5
TS		 223 .CP0_Config2 = MIPS_CONFIG2,
224 .CP0_Config3 = MIPS_CONFIG3,
2a6e32dd
AJ		 225 .CP0_LLAddr_rw_bitmask = 0,
226 .CP0_LLAddr_shift = 4,
3e4587d5
TS		 227 .SYNCI_Step = 32,
228 .CCRes = 2,
229 .CP0_Status_rw_bitmask = 0x1258FF17,
6d35524c
TS		 230 .SEGBITS = 32,
231 .PABITS = 32,
3e4587d5 232 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
6d35524c 233 .mmu_type = MMU_TYPE_FMT,
3e4587d5 234 },
34ee2ede
TS		 235 {
236 .name = "24Kc",
237 .CP0_PRid = 0x00019300,
6d35524c 238 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
6958549d 239 (MMU_TYPE_R4000 << CP0C0_MT),
ae5d8053 240 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
6958549d 241 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
d19954f4
NF		 242 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
243 (1 << CP0C1_CA),
3953d786 244 .CP0_Config2 = MIPS_CONFIG2,
ead9360e 245 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
2a6e32dd
AJ		 246 .CP0_LLAddr_rw_bitmask = 0,
247 .CP0_LLAddr_shift = 4,
2f644545
TS		 248 .SYNCI_Step = 32,
249 .CCRes = 2,
ead9360e 250 /* No DSP implemented. */
671880e6 251 .CP0_Status_rw_bitmask = 0x1278FF1F,
6d35524c
TS		 252 .SEGBITS = 32,
253 .PABITS = 32,
3e4587d5 254 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
6d35524c 255 .mmu_type = MMU_TYPE_R4000,
33d68b5f
TS		 256 },
257 {
258 .name = "24Kf",
259 .CP0_PRid = 0x00019300,
6d35524c
TS		 260 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
261 (MMU_TYPE_R4000 << CP0C0_MT),
ae5d8053 262 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
6958549d 263 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
d19954f4
NF		 264 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
265 (1 << CP0C1_CA),
3953d786 266 .CP0_Config2 = MIPS_CONFIG2,
ead9360e 267 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
2a6e32dd
AJ		 268 .CP0_LLAddr_rw_bitmask = 0,
269 .CP0_LLAddr_shift = 4,
2f644545
TS		 270 .SYNCI_Step = 32,
271 .CCRes = 2,
ead9360e 272 /* No DSP implemented. */
671880e6 273 .CP0_Status_rw_bitmask = 0x3678FF1F,
5a5012ec
TS		 274 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
275 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
6d35524c
TS		 276 .SEGBITS = 32,
277 .PABITS = 32,
3e4587d5 278 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
6d35524c 279 .mmu_type = MMU_TYPE_R4000,
33d68b5f 280 },
ead9360e
TS		 281 {
282 .name = "34Kf",
283 .CP0_PRid = 0x00019500,
6d35524c 284 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
6958549d 285 (MMU_TYPE_R4000 << CP0C0_MT),
ead9360e 286 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
6958549d 287 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
d19954f4
NF		 288 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
289 (1 << CP0C1_CA),
ead9360e 290 .CP0_Config2 = MIPS_CONFIG2,
b9ac5d92
YK		 291 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
292 (1 << CP0C3_DSPP),
2a6e32dd
AJ		 293 .CP0_LLAddr_rw_bitmask = 0,
294 .CP0_LLAddr_shift = 0,
ead9360e
TS		 295 .SYNCI_Step = 32,
296 .CCRes = 2,
b9ac5d92 297 .CP0_Status_rw_bitmask = 0x3778FF1F,
ead9360e
TS		 298 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
299 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
300 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
301 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
302 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
303 (0xff << CP0TCSt_TASID),
304 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
305 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
306 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
307 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
f45cb2f4 308 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
ead9360e
TS		 309 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
310 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
f45cb2f4 311 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
ead9360e
TS		 312 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
313 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
f45cb2f4 314 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
ead9360e
TS		 315 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
316 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
f45cb2f4 317 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
ead9360e
TS		 318 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
319 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
320 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
321 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
6d35524c
TS		 322 .SEGBITS = 32,
323 .PABITS = 32,
7385ac0b 324 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
6d35524c 325 .mmu_type = MMU_TYPE_R4000,
ead9360e 326 },
af13ae03
JL		 327 {
328 .name = "74Kf",
329 .CP0_PRid = 0x00019700,
330 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
331 (MMU_TYPE_R4000 << CP0C0_MT),
332 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
333 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
334 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
335 (1 << CP0C1_CA),
336 .CP0_Config2 = MIPS_CONFIG2,
e30614d5 337 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
4386f087 338 (1 << CP0C3_VInt),
af13ae03
JL		 339 .CP0_LLAddr_rw_bitmask = 0,
340 .CP0_LLAddr_shift = 4,
341 .SYNCI_Step = 32,
342 .CCRes = 2,
343 .CP0_Status_rw_bitmask = 0x3778FF1F,
344 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
345 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
346 .SEGBITS = 32,
347 .PABITS = 32,
348 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
349 .mmu_type = MMU_TYPE_R4000,
350 },
11f5ea10
MR		 351 {
352 .name = "M14K",
353 .CP0_PRid = 0x00019b00,
354 /* Config1 implemented, fixed mapping MMU,
355 no virtual icache, uncached coherency. */
356 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
357 (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
358 .CP0_Config1 = MIPS_CONFIG1,
359 .CP0_Config2 = MIPS_CONFIG2,
360 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
361 .CP0_LLAddr_rw_bitmask = 0,
362 .CP0_LLAddr_shift = 4,
363 .SYNCI_Step = 32,
364 .CCRes = 2,
365 .CP0_Status_rw_bitmask = 0x1258FF17,
366 .SEGBITS = 32,
367 .PABITS = 32,
368 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
369 .mmu_type = MMU_TYPE_FMT,
370 },
371 {
372 .name = "M14Kc",
373 /* This is the TLB-based MMU core. */
374 .CP0_PRid = 0x00019c00,
375 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
376 (MMU_TYPE_R4000 << CP0C0_MT),
377 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
378 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
379 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
380 .CP0_Config2 = MIPS_CONFIG2,
381 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
382 .CP0_LLAddr_rw_bitmask = 0,
383 .CP0_LLAddr_shift = 4,
384 .SYNCI_Step = 32,
385 .CCRes = 2,
386 .CP0_Status_rw_bitmask = 0x1278FF17,
387 .SEGBITS = 32,
388 .PABITS = 32,
389 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
390 .mmu_type = MMU_TYPE_R4000,
391 },
e527526d 392 {
aff2bc6d
YK		 393 /* FIXME:
394 * Config3: CMGCR, SC, PW, VZ, CTXTC, CDMM, TL
395 * Config4: MMUExtDef
396 * Config5: EVA, MRP
397 * FIR(FCR0): Has2008
398 * */
399 .name = "P5600",
400 .CP0_PRid = 0x0001A800,
401 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
e527526d 402 (MMU_TYPE_R4000 << CP0C0_MT),
aff2bc6d
YK		 403 .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
404 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
405 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
406 (1 << CP0C1_PC) | (1 << CP0C1_FP),
e527526d 407 .CP0_Config2 = MIPS_CONFIG2,
6773f9b6 408 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
aff2bc6d
YK		 409 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
410 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
411 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
412 (0x1c << CP0C4_KScrExist),
b4160af1 413 .CP0_Config4_rw_bitmask = 0,
aff2bc6d
YK		 414 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
415 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
416 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
417 (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
e527526d 418 .CP0_LLAddr_rw_bitmask = 0,
aff2bc6d 419 .CP0_LLAddr_shift = 0,
e527526d
PJ		 420 .SYNCI_Step = 32,
421 .CCRes = 2,
aff2bc6d
YK		 422 .CP0_Status_rw_bitmask = 0x3C68FF1F,
423 .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
424 (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
ba5c79f2
LA		 425 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) |
426 (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
427 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
428 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
e527526d 429 .SEGBITS = 32,
6773f9b6 430 .PABITS = 40,
aff2bc6d 431 .insn_flags = CPU_MIPS32R5 | ASE_MSA,
e527526d
PJ		 432 .mmu_type = MMU_TYPE_R4000,
433 },
4b3bcd01
YK		 434 {
435 /* A generic CPU supporting MIPS32 Release 6 ISA.
436 FIXME: Support IEEE 754-2008 FP.
437 Eventually this should be replaced by a real CPU model. */
438 .name = "mips32r6-generic",
439 .CP0_PRid = 0x00010000,
440 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
441 (MMU_TYPE_R4000 << CP0C0_MT),
442 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
443 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
444 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
445 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
446 .CP0_Config2 = MIPS_CONFIG2,
447 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
448 (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
449 (1 << CP0C3_RXI) | (1U << CP0C3_M),
450 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
451 (3 << CP0C4_IE) | (1U << CP0C4_M),
35ac9e34 452 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
4b3bcd01
YK		 453 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
454 (1 << CP0C5_UFE),
455 .CP0_LLAddr_rw_bitmask = 0,
456 .CP0_LLAddr_shift = 0,
457 .SYNCI_Step = 32,
458 .CCRes = 2,
459 .CP0_Status_rw_bitmask = 0x3058FF1F,
460 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
461 (1U << CP0PG_RIE),
462 .CP0_PageGrain_rw_bitmask = 0,
ba5c79f2
LA		 463 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
464 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
465 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
466 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
4b3bcd01
YK		 467 .SEGBITS = 32,
468 .PABITS = 32,
469 .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
470 .mmu_type = MMU_TYPE_R4000,
471 },
d26bc211 472#if defined(TARGET_MIPS64)
33d68b5f
TS		 473 {
474 .name = "R4000",
475 .CP0_PRid = 0x00000400,
6d35524c
TS		 476 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
477 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
6958549d 478 /* Note: Config1 is only used internally, the R4000 has only Config0. */
6d35524c 479 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
2a6e32dd
AJ		 480 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
481 .CP0_LLAddr_shift = 4,
2f644545
TS		 482 .SYNCI_Step = 16,
483 .CCRes = 2,
ead9360e 484 .CP0_Status_rw_bitmask = 0x3678FFFF,
6958549d 485 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
c9c1a064 486 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
e034e2c3 487 .SEGBITS = 40,
6d35524c 488 .PABITS = 36,
e189e748 489 .insn_flags = CPU_MIPS3,
6d35524c 490 .mmu_type = MMU_TYPE_R4000,
c9c1a064 491 },
e9c71dd1
TS		 492 {
493 .name = "VR5432",
494 .CP0_PRid = 0x00005400,
495 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
496 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
497 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
2a6e32dd
AJ		 498 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
499 .CP0_LLAddr_shift = 4,
e9c71dd1
TS		 500 .SYNCI_Step = 16,
501 .CCRes = 2,
502 .CP0_Status_rw_bitmask = 0x3678FFFF,
503 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
504 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
505 .SEGBITS = 40,
506 .PABITS = 32,
507 .insn_flags = CPU_VR54XX,
508 .mmu_type = MMU_TYPE_R4000,
509 },
c9c1a064
TS		 510 {
511 .name = "5Kc",
512 .CP0_PRid = 0x00018100,
29fe0e34 513 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
6958549d 514 (MMU_TYPE_R4000 << CP0C0_MT),
c9c1a064 515 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
6958549d
AJ		 516 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
517 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
518 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
c9c1a064
TS		 519 .CP0_Config2 = MIPS_CONFIG2,
520 .CP0_Config3 = MIPS_CONFIG3,
2a6e32dd
AJ		 521 .CP0_LLAddr_rw_bitmask = 0,
522 .CP0_LLAddr_shift = 4,
c9c1a064
TS		 523 .SYNCI_Step = 32,
524 .CCRes = 2,
196a7958 525 .CP0_Status_rw_bitmask = 0x12F8FFFF,
e034e2c3 526 .SEGBITS = 42,
6d35524c 527 .PABITS = 36,
e189e748 528 .insn_flags = CPU_MIPS64,
6d35524c 529 .mmu_type = MMU_TYPE_R4000,
c9c1a064
TS		 530 },
531 {
532 .name = "5Kf",
533 .CP0_PRid = 0x00018100,
29fe0e34 534 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
6958549d 535 (MMU_TYPE_R4000 << CP0C0_MT),
c9c1a064 536 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
6958549d
AJ		 537 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
538 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
539 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
c9c1a064
TS		 540 .CP0_Config2 = MIPS_CONFIG2,
541 .CP0_Config3 = MIPS_CONFIG3,
2a6e32dd
AJ		 542 .CP0_LLAddr_rw_bitmask = 0,
543 .CP0_LLAddr_shift = 4,
c9c1a064
TS		 544 .SYNCI_Step = 32,
545 .CCRes = 2,
ead9360e 546 .CP0_Status_rw_bitmask = 0x36F8FFFF,
6958549d 547 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
c9c1a064
TS		 548 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
549 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
e034e2c3 550 .SEGBITS = 42,
6d35524c 551 .PABITS = 36,
e189e748 552 .insn_flags = CPU_MIPS64,
6d35524c 553 .mmu_type = MMU_TYPE_R4000,
c9c1a064
TS		 554 },
555 {
556 .name = "20Kc",
6958549d 557 /* We emulate a later version of the 20Kc, earlier ones had a broken
bd04c6fe
TS		 558 WAIT instruction. */
559 .CP0_PRid = 0x000182a0,
29fe0e34 560 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
6d35524c 561 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
c9c1a064 562 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
6958549d
AJ		 563 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
564 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
565 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
c9c1a064
TS		 566 .CP0_Config2 = MIPS_CONFIG2,
567 .CP0_Config3 = MIPS_CONFIG3,
2a6e32dd
AJ		 568 .CP0_LLAddr_rw_bitmask = 0,
569 .CP0_LLAddr_shift = 0,
c9c1a064 570 .SYNCI_Step = 32,
a1daafd8 571 .CCRes = 1,
ead9360e 572 .CP0_Status_rw_bitmask = 0x36FBFFFF,
6958549d 573 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
c9c1a064 574 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
5a5012ec 575 (1 << FCR0_D) | (1 << FCR0_S) |
c9c1a064 576 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
e034e2c3 577 .SEGBITS = 40,
6d35524c 578 .PABITS = 36,
e189e748 579 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
6d35524c 580 .mmu_type = MMU_TYPE_R4000,
33d68b5f 581 },
d2123ead 582 {
6958549d 583 /* A generic CPU providing MIPS64 Release 2 features.
d2123ead
TS		 584 FIXME: Eventually this should be replaced by a real CPU model. */
585 .name = "MIPS64R2-generic",
8c89395e 586 .CP0_PRid = 0x00010000,
6d35524c 587 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
6958549d 588 (MMU_TYPE_R4000 << CP0C0_MT),
d2123ead 589 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
6958549d
AJ		 590 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
591 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
592 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
d2123ead 593 .CP0_Config2 = MIPS_CONFIG2,
6d35524c 594 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
2a6e32dd
AJ		 595 .CP0_LLAddr_rw_bitmask = 0,
596 .CP0_LLAddr_shift = 0,
d2123ead
TS		 597 .SYNCI_Step = 32,
598 .CCRes = 2,
599 .CP0_Status_rw_bitmask = 0x36FBFFFF,
ea4b07f7
TS		 600 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
601 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
602 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
6d35524c 603 .SEGBITS = 42,
6d35524c 604 .PABITS = 36,
d2123ead 605 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
6d35524c 606 .mmu_type = MMU_TYPE_R4000,
d2123ead 607 },
36b86e0d
MR		 608 {
609 .name = "5KEc",
610 .CP0_PRid = 0x00018900,
611 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
612 (MMU_TYPE_R4000 << CP0C0_MT),
613 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
614 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
615 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
616 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
617 .CP0_Config2 = MIPS_CONFIG2,
618 .CP0_Config3 = MIPS_CONFIG3,
619 .CP0_LLAddr_rw_bitmask = 0,
620 .CP0_LLAddr_shift = 4,
621 .SYNCI_Step = 32,
622 .CCRes = 2,
196a7958 623 .CP0_Status_rw_bitmask = 0x12F8FFFF,
36b86e0d
MR		 624 .SEGBITS = 42,
625 .PABITS = 36,
626 .insn_flags = CPU_MIPS64R2,
627 .mmu_type = MMU_TYPE_R4000,
628 },
629 {
630 .name = "5KEf",
631 .CP0_PRid = 0x00018900,
632 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
633 (MMU_TYPE_R4000 << CP0C0_MT),
634 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
635 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
636 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
637 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
638 .CP0_Config2 = MIPS_CONFIG2,
639 .CP0_Config3 = MIPS_CONFIG3,
640 .CP0_LLAddr_rw_bitmask = 0,
641 .CP0_LLAddr_shift = 4,
642 .SYNCI_Step = 32,
643 .CCRes = 2,
644 .CP0_Status_rw_bitmask = 0x36F8FFFF,
645 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
646 (1 << FCR0_D) | (1 << FCR0_S) |
647 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
648 .SEGBITS = 42,
649 .PABITS = 36,
650 .insn_flags = CPU_MIPS64R2,
651 .mmu_type = MMU_TYPE_R4000,
652 },
a773cc79
LA		 653 {
654 /* A generic CPU supporting MIPS64 Release 6 ISA.
be3a8c53 655 FIXME: Support IEEE 754-2008 FP.
a773cc79
LA		 656 Eventually this should be replaced by a real CPU model. */
657 .name = "MIPS64R6-generic",
658 .CP0_PRid = 0x00010000,
659 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
660 (MMU_TYPE_R4000 << CP0C0_MT),
661 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
662 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
663 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
664 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
665 .CP0_Config2 = MIPS_CONFIG2,
a9a95061
LA		 666 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
667 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
4dc89b78
YK		 668 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
669 (1 << CP0C3_RXI) | (1 << CP0C3_LPA),
670 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
671 (0xfc << CP0C4_KScrExist),
01bc435b
YK		 672 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
673 (1 << CP0C5_LLB),
4dc89b78
YK		 674 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
675 (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
a773cc79
LA		 676 .CP0_LLAddr_rw_bitmask = 0,
677 .CP0_LLAddr_shift = 0,
678 .SYNCI_Step = 32,
679 .CCRes = 2,
680 .CP0_Status_rw_bitmask = 0x30D8FFFF,
2d9e48bc
LA		 681 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
682 (1U << CP0PG_RIE),
6773f9b6 683 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
ba5c79f2
LA		 684 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
685 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
686 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
687 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
4dc89b78 688 .SEGBITS = 48,
6773f9b6 689 .PABITS = 48,
4dc89b78 690 .insn_flags = CPU_MIPS64R6 | ASE_MSA,
a773cc79
LA		 691 .mmu_type = MMU_TYPE_R4000,
692 },
5bc6fba8
HC		 693 {
694 .name = "Loongson-2E",
695 .CP0_PRid = 0x6302,
6225a4a0
MR		 696 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
697 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
698 (0x1<<5) | (0x1<<4) | (0x1<<1),
699 /* Note: Config1 is only used internally,
700 Loongson-2E has only Config0. */
5bc6fba8
HC		 701 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
702 .SYNCI_Step = 16,
703 .CCRes = 2,
704 .CP0_Status_rw_bitmask = 0x35D0FFFF,
705 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
706 .SEGBITS = 40,
707 .PABITS = 40,
708 .insn_flags = CPU_LOONGSON2E,
709 .mmu_type = MMU_TYPE_R4000,
710 },
711 {
6225a4a0
MR		 712 .name = "Loongson-2F",
713 .CP0_PRid = 0x6303,
714 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
715 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
716 (0x1<<5) | (0x1<<4) | (0x1<<1),
717 /* Note: Config1 is only used internally,
718 Loongson-2F has only Config0. */
719 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
720 .SYNCI_Step = 16,
721 .CCRes = 2,
722 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
723 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
724 .SEGBITS = 40,
725 .PABITS = 40,
726 .insn_flags = CPU_LOONGSON2F,
727 .mmu_type = MMU_TYPE_R4000,
5bc6fba8 728 },
af13ae03
JL		 729 {
730 /* A generic CPU providing MIPS64 ASE DSP 2 features.
731 FIXME: Eventually this should be replaced by a real CPU model. */
732 .name = "mips64dspr2",
733 .CP0_PRid = 0x00010000,
734 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
735 (MMU_TYPE_R4000 << CP0C0_MT),
736 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
737 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
738 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
739 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
740 .CP0_Config2 = MIPS_CONFIG2,
e30614d5
MR		 741 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
742 (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
af13ae03
JL		 743 .CP0_LLAddr_rw_bitmask = 0,
744 .CP0_LLAddr_shift = 0,
745 .SYNCI_Step = 32,
746 .CCRes = 2,
747 .CP0_Status_rw_bitmask = 0x37FBFFFF,
748 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
749 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
750 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
751 .SEGBITS = 42,
af13ae03
JL		 752 .PABITS = 36,
753 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
754 .mmu_type = MMU_TYPE_R4000,
755 },
5bc6fba8 756
33d68b5f
TS		 757#endif
758};
759
c227f099 760static const mips_def_t *cpu_mips_find_by_name (const char *name)
33d68b5f 761{
aaed909a 762 int i;
33d68b5f 763
b1503cda 764 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
33d68b5f 765 if (strcasecmp(name, mips_defs[i].name) == 0) {
aaed909a 766 return &mips_defs[i];
33d68b5f
TS		 767 }
768 }
aaed909a 769 return NULL;
33d68b5f
TS		 770}
771
9a78eead 772void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
33d68b5f
TS		 773{
774 int i;
775
b1503cda 776 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
33d68b5f
TS		 777 (*cpu_fprintf)(f, "MIPS '%s'\n",
778 mips_defs[i].name);
779 }
780}
781
f8a6ec58 782#ifndef CONFIG_USER_ONLY
c227f099 783static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
29929e34 784{
ead9360e
TS		 785 env->tlb->nb_tlb = 1;
786 env->tlb->map_address = &no_mmu_map_address;
29929e34
TS		 787}
788
c227f099 789static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
29929e34 790{
ead9360e
TS		 791 env->tlb->nb_tlb = 1;
792 env->tlb->map_address = &fixed_mmu_map_address;
29929e34
TS		 793}
794
c227f099 795static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
29929e34 796{
ead9360e
TS		 797 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
798 env->tlb->map_address = &r4k_map_address;
c01fccd2
AJ		 799 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
800 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
801 env->tlb->helper_tlbp = r4k_helper_tlbp;
802 env->tlb->helper_tlbr = r4k_helper_tlbr;
9456c2fb
LA		 803 env->tlb->helper_tlbinv = r4k_helper_tlbinv;
804 env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
ead9360e
TS		 805}
806
c227f099 807static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
ead9360e 808{
a47dddd7
AF		 809 MIPSCPU *cpu = mips_env_get_cpu(env);
810
7267c094 811 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
ead9360e 812
6d35524c
TS		 813 switch (def->mmu_type) {
814 case MMU_TYPE_NONE:
ead9360e
TS		 815 no_mmu_init(env, def);
816 break;
6d35524c 817 case MMU_TYPE_R4000:
ead9360e
TS		 818 r4k_mmu_init(env, def);
819 break;
6d35524c 820 case MMU_TYPE_FMT:
ead9360e
TS		 821 fixed_mmu_init(env, def);
822 break;
6d35524c
TS		 823 case MMU_TYPE_R3000:
824 case MMU_TYPE_R6000:
825 case MMU_TYPE_R8000:
ead9360e 826 default:
a47dddd7 827 cpu_abort(CPU(cpu), "MMU type not supported\n");
ead9360e 828 }
29929e34 829}
f8a6ec58 830#endif /* CONFIG_USER_ONLY */
29929e34 831
c227f099 832static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
ead9360e 833{
f01be154
TS		 834 int i;
835
836 for (i = 0; i < MIPS_FPU_MAX; i++)
837 env->fpus[i].fcr0 = def->CP1_fcr0;
ead9360e 838
f01be154 839 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
ead9360e
TS		 840}
841
c227f099 842static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
ead9360e 843{
7267c094 844 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
ead9360e
TS		 845
846 /* MVPConf1 implemented, TLB sharable, no gating storage support,
847 programmable cache partitioning implemented, number of allocatable
848 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
849 implemented, 5 TCs implemented. */
f45cb2f4 850 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
ead9360e 851 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
ead9360e
TS		 852// TODO: actually do 2 VPEs.
853// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
854// (0x04 << CP0MVPC0_PTC);
855 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
1dab005a 856 (0x00 << CP0MVPC0_PTC);
932e71cd 857#if !defined(CONFIG_USER_ONLY)
0eaef5aa 858 /* Usermode has no TLB support */
932e71cd
AJ		 859 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
860#endif
0eaef5aa 861
ead9360e
TS		 862 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
863 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
f45cb2f4 864 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
ead9360e
TS		 865 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
866 (0x1 << CP0MVPC1_PCP1);
867}
863f264d
YK		 868
869static void msa_reset(CPUMIPSState *env)
870{
871#ifdef CONFIG_USER_ONLY
872 /* MSA access enabled */
873 env->CP0_Config5 |= 1 << CP0C5_MSAEn;
874 env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
875#endif
876
877 /* MSA CSR:
878 - non-signaling floating point exception mode off (NX bit is 0)
879 - Cause, Enables, and Flags are all 0
880 - round to nearest / ties to even (RM bits are 0) */
881 env->active_tc.msacsr = 0;
882
64451111
LA		 883 restore_msa_fp_status(env);
884
863f264d
YK		 885 /* tininess detected after rounding.*/
886 set_float_detect_tininess(float_tininess_after_rounding,
887 &env->active_tc.msa_fp_status);
888
889 /* clear float_status exception flags */
890 set_float_exception_flags(0, &env->active_tc.msa_fp_status);
891
863f264d
YK		 892 /* clear float_status nan mode */
893 set_default_nan_mode(0, &env->active_tc.msa_fp_status);
894}
Empty description
This page took 0.905701 seconds and 4 git commands to generate.