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[qemu.git] / hw / timer / twl92230.c
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7e7c5e4c
AZ		 1/*
2 * TI TWL92230C energy-management companion device for the OMAP24xx.
3 * Aka. Menelaus (N4200 MENELAUS1_V2.2)
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
fad6cb1a 18 * You should have received a copy of the GNU General Public License along
8167ee88 19 * with this program; if not, see <http://www.gnu.org/licenses/>.
7e7c5e4c
AZ		 20 */
21
83c9f4ca 22#include "hw/hw.h"
1de7afc9 23#include "qemu/timer.h"
0d09e41a 24#include "hw/i2c/i2c.h"
9c17d615 25#include "sysemu/sysemu.h"
28ecbaee 26#include "ui/console.h"
7e7c5e4c
AZ		 27
28#define VERBOSE 1
29
dd37dfa9
AF		 30#define TYPE_TWL92230 "twl92230"
31#define TWL92230(obj) OBJECT_CHECK(MenelausState, (obj), TYPE_TWL92230)
32
33typedef struct MenelausState {
34 I2CSlave parent_obj;
7e7c5e4c
AZ		 35
36 int firstbyte;
37 uint8_t reg;
38
39 uint8_t vcore[5];
40 uint8_t dcdc[3];
41 uint8_t ldo[8];
42 uint8_t sleep[2];
43 uint8_t osc;
44 uint8_t detect;
45 uint16_t mask;
46 uint16_t status;
47 uint8_t dir;
48 uint8_t inputs;
49 uint8_t outputs;
50 uint8_t bbsms;
51 uint8_t pull[4];
52 uint8_t mmc_ctrl[3];
53 uint8_t mmc_debounce;
54 struct {
55 uint8_t ctrl;
56 uint16_t comp;
b0f74c87 57 QEMUTimer *hz_tm;
7e7c5e4c
AZ		 58 int64_t next;
59 struct tm tm;
60 struct tm new;
61 struct tm alm;
aec454d2
AZ		 62 int sec_offset;
63 int alm_sec;
64 int next_comp;
7e7c5e4c 65 } rtc;
f0495f56 66 uint16_t rtc_next_vmstate;
d3356811 67 qemu_irq out[4];
b53d44e5 68 uint8_t pwrbtn_state;
bc24a225 69} MenelausState;
7e7c5e4c 70
bc24a225 71static inline void menelaus_update(MenelausState *s)
7e7c5e4c 72{
d3356811 73 qemu_set_irq(s->out[3], s->status & ~s->mask);
7e7c5e4c
AZ		 74}
75
bc24a225 76static inline void menelaus_rtc_start(MenelausState *s)
7e7c5e4c 77{
884f17c2 78 s->rtc.next += qemu_clock_get_ms(rtc_clock);
bc72ad67 79 timer_mod(s->rtc.hz_tm, s->rtc.next);
7e7c5e4c
AZ		 80}
81
bc24a225 82static inline void menelaus_rtc_stop(MenelausState *s)
7e7c5e4c 83{
bc72ad67 84 timer_del(s->rtc.hz_tm);
884f17c2 85 s->rtc.next -= qemu_clock_get_ms(rtc_clock);
7e7c5e4c
AZ		 86 if (s->rtc.next < 1)
87 s->rtc.next = 1;
88}
89
bc24a225 90static void menelaus_rtc_update(MenelausState *s)
7e7c5e4c 91{
aec454d2 92 qemu_get_timedate(&s->rtc.tm, s->rtc.sec_offset);
7e7c5e4c
AZ		 93}
94
bc24a225 95static void menelaus_alm_update(MenelausState *s)
7e7c5e4c
AZ		 96{
97 if ((s->rtc.ctrl & 3) == 3)
aec454d2 98 s->rtc.alm_sec = qemu_timedate_diff(&s->rtc.alm) - s->rtc.sec_offset;
7e7c5e4c
AZ		 99}
100
101static void menelaus_rtc_hz(void *opaque)
102{
bc24a225 103 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c 104
aec454d2
AZ		 105 s->rtc.next_comp --;
106 s->rtc.alm_sec --;
7e7c5e4c 107 s->rtc.next += 1000;
bc72ad67 108 timer_mod(s->rtc.hz_tm, s->rtc.next);
7e7c5e4c
AZ		 109 if ((s->rtc.ctrl >> 3) & 3) { /* EVERY */
110 menelaus_rtc_update(s);
111 if (((s->rtc.ctrl >> 3) & 3) == 1 && !s->rtc.tm.tm_sec)
112 s->status |= 1 << 8; /* RTCTMR */
113 else if (((s->rtc.ctrl >> 3) & 3) == 2 && !s->rtc.tm.tm_min)
114 s->status |= 1 << 8; /* RTCTMR */
115 else if (!s->rtc.tm.tm_hour)
116 s->status |= 1 << 8; /* RTCTMR */
117 } else
118 s->status |= 1 << 8; /* RTCTMR */
119 if ((s->rtc.ctrl >> 1) & 1) { /* RTC_AL_EN */
aec454d2 120 if (s->rtc.alm_sec == 0)
7e7c5e4c
AZ		 121 s->status |= 1 << 9; /* RTCALM */
122 /* TODO: wake-up */
123 }
aec454d2 124 if (s->rtc.next_comp <= 0) {
7e7c5e4c 125 s->rtc.next -= muldiv64((int16_t) s->rtc.comp, 1000, 0x8000);
aec454d2 126 s->rtc.next_comp = 3600;
7e7c5e4c
AZ		 127 }
128 menelaus_update(s);
129}
130
9e07bdf8 131static void menelaus_reset(I2CSlave *i2c)
7e7c5e4c 132{
dd37dfa9
AF		 133 MenelausState *s = TWL92230(i2c);
134
7e7c5e4c
AZ		 135 s->reg = 0x00;
136
137 s->vcore[0] = 0x0c; /* XXX: X-loader needs 0x8c? check! */
138 s->vcore[1] = 0x05;
139 s->vcore[2] = 0x02;
140 s->vcore[3] = 0x0c;
141 s->vcore[4] = 0x03;
142 s->dcdc[0] = 0x33; /* Depends on wiring */
143 s->dcdc[1] = 0x03;
144 s->dcdc[2] = 0x00;
145 s->ldo[0] = 0x95;
146 s->ldo[1] = 0x7e;
147 s->ldo[2] = 0x00;
148 s->ldo[3] = 0x00; /* Depends on wiring */
149 s->ldo[4] = 0x03; /* Depends on wiring */
150 s->ldo[5] = 0x00;
151 s->ldo[6] = 0x00;
152 s->ldo[7] = 0x00;
153 s->sleep[0] = 0x00;
154 s->sleep[1] = 0x00;
155 s->osc = 0x01;
156 s->detect = 0x09;
157 s->mask = 0x0fff;
158 s->status = 0;
159 s->dir = 0x07;
160 s->outputs = 0x00;
161 s->bbsms = 0x00;
162 s->pull[0] = 0x00;
163 s->pull[1] = 0x00;
164 s->pull[2] = 0x00;
165 s->pull[3] = 0x00;
166 s->mmc_ctrl[0] = 0x03;
167 s->mmc_ctrl[1] = 0xc0;
168 s->mmc_ctrl[2] = 0x00;
169 s->mmc_debounce = 0x05;
170
7e7c5e4c
AZ		 171 if (s->rtc.ctrl & 1)
172 menelaus_rtc_stop(s);
173 s->rtc.ctrl = 0x00;
174 s->rtc.comp = 0x0000;
175 s->rtc.next = 1000;
aec454d2
AZ		 176 s->rtc.sec_offset = 0;
177 s->rtc.next_comp = 1800;
178 s->rtc.alm_sec = 1800;
7e7c5e4c
AZ		 179 s->rtc.alm.tm_sec = 0x00;
180 s->rtc.alm.tm_min = 0x00;
181 s->rtc.alm.tm_hour = 0x00;
182 s->rtc.alm.tm_mday = 0x01;
183 s->rtc.alm.tm_mon = 0x00;
184 s->rtc.alm.tm_year = 2004;
185 menelaus_update(s);
186}
187
7e7c5e4c
AZ		 188static void menelaus_gpio_set(void *opaque, int line, int level)
189{
bc24a225 190 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c 191
dd4427a6
PB		 192 if (line < 3) {
193 /* No interrupt generated */
194 s->inputs &= ~(1 << line);
195 s->inputs |= level << line;
196 return;
197 }
7e7c5e4c
AZ		 198
199 if (!s->pwrbtn_state && level) {
200 s->status |= 1 << 11; /* PSHBTN */
201 menelaus_update(s);
202 }
203 s->pwrbtn_state = level;
204}
205
206#define MENELAUS_REV 0x01
207#define MENELAUS_VCORE_CTRL1 0x02
208#define MENELAUS_VCORE_CTRL2 0x03
209#define MENELAUS_VCORE_CTRL3 0x04
210#define MENELAUS_VCORE_CTRL4 0x05
211#define MENELAUS_VCORE_CTRL5 0x06
212#define MENELAUS_DCDC_CTRL1 0x07
213#define MENELAUS_DCDC_CTRL2 0x08
214#define MENELAUS_DCDC_CTRL3 0x09
215#define MENELAUS_LDO_CTRL1 0x0a
216#define MENELAUS_LDO_CTRL2 0x0b
217#define MENELAUS_LDO_CTRL3 0x0c
218#define MENELAUS_LDO_CTRL4 0x0d
219#define MENELAUS_LDO_CTRL5 0x0e
220#define MENELAUS_LDO_CTRL6 0x0f
221#define MENELAUS_LDO_CTRL7 0x10
222#define MENELAUS_LDO_CTRL8 0x11
223#define MENELAUS_SLEEP_CTRL1 0x12
224#define MENELAUS_SLEEP_CTRL2 0x13
225#define MENELAUS_DEVICE_OFF 0x14
226#define MENELAUS_OSC_CTRL 0x15
227#define MENELAUS_DETECT_CTRL 0x16
228#define MENELAUS_INT_MASK1 0x17
229#define MENELAUS_INT_MASK2 0x18
230#define MENELAUS_INT_STATUS1 0x19
231#define MENELAUS_INT_STATUS2 0x1a
232#define MENELAUS_INT_ACK1 0x1b
233#define MENELAUS_INT_ACK2 0x1c
234#define MENELAUS_GPIO_CTRL 0x1d
235#define MENELAUS_GPIO_IN 0x1e
236#define MENELAUS_GPIO_OUT 0x1f
237#define MENELAUS_BBSMS 0x20
238#define MENELAUS_RTC_CTRL 0x21
239#define MENELAUS_RTC_UPDATE 0x22
240#define MENELAUS_RTC_SEC 0x23
241#define MENELAUS_RTC_MIN 0x24
242#define MENELAUS_RTC_HR 0x25
243#define MENELAUS_RTC_DAY 0x26
244#define MENELAUS_RTC_MON 0x27
245#define MENELAUS_RTC_YR 0x28
246#define MENELAUS_RTC_WKDAY 0x29
247#define MENELAUS_RTC_AL_SEC 0x2a
248#define MENELAUS_RTC_AL_MIN 0x2b
249#define MENELAUS_RTC_AL_HR 0x2c
250#define MENELAUS_RTC_AL_DAY 0x2d
251#define MENELAUS_RTC_AL_MON 0x2e
252#define MENELAUS_RTC_AL_YR 0x2f
253#define MENELAUS_RTC_COMP_MSB 0x30
254#define MENELAUS_RTC_COMP_LSB 0x31
255#define MENELAUS_S1_PULL_EN 0x32
256#define MENELAUS_S1_PULL_DIR 0x33
257#define MENELAUS_S2_PULL_EN 0x34
258#define MENELAUS_S2_PULL_DIR 0x35
259#define MENELAUS_MCT_CTRL1 0x36
260#define MENELAUS_MCT_CTRL2 0x37
261#define MENELAUS_MCT_CTRL3 0x38
262#define MENELAUS_MCT_PIN_ST 0x39
263#define MENELAUS_DEBOUNCE1 0x3a
264
265static uint8_t menelaus_read(void *opaque, uint8_t addr)
266{
bc24a225 267 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c
AZ		 268 int reg = 0;
269
270 switch (addr) {
271 case MENELAUS_REV:
272 return 0x22;
273
274 case MENELAUS_VCORE_CTRL5: reg ++;
275 case MENELAUS_VCORE_CTRL4: reg ++;
276 case MENELAUS_VCORE_CTRL3: reg ++;
277 case MENELAUS_VCORE_CTRL2: reg ++;
278 case MENELAUS_VCORE_CTRL1:
279 return s->vcore[reg];
280
281 case MENELAUS_DCDC_CTRL3: reg ++;
282 case MENELAUS_DCDC_CTRL2: reg ++;
283 case MENELAUS_DCDC_CTRL1:
284 return s->dcdc[reg];
285
286 case MENELAUS_LDO_CTRL8: reg ++;
287 case MENELAUS_LDO_CTRL7: reg ++;
288 case MENELAUS_LDO_CTRL6: reg ++;
289 case MENELAUS_LDO_CTRL5: reg ++;
290 case MENELAUS_LDO_CTRL4: reg ++;
291 case MENELAUS_LDO_CTRL3: reg ++;
292 case MENELAUS_LDO_CTRL2: reg ++;
293 case MENELAUS_LDO_CTRL1:
294 return s->ldo[reg];
295
296 case MENELAUS_SLEEP_CTRL2: reg ++;
297 case MENELAUS_SLEEP_CTRL1:
298 return s->sleep[reg];
299
300 case MENELAUS_DEVICE_OFF:
301 return 0;
302
303 case MENELAUS_OSC_CTRL:
304 return s->osc | (1 << 7); /* CLK32K_GOOD */
305
306 case MENELAUS_DETECT_CTRL:
307 return s->detect;
308
309 case MENELAUS_INT_MASK1:
310 return (s->mask >> 0) & 0xff;
311 case MENELAUS_INT_MASK2:
312 return (s->mask >> 8) & 0xff;
313
314 case MENELAUS_INT_STATUS1:
315 return (s->status >> 0) & 0xff;
316 case MENELAUS_INT_STATUS2:
317 return (s->status >> 8) & 0xff;
318
319 case MENELAUS_INT_ACK1:
320 case MENELAUS_INT_ACK2:
321 return 0;
322
323 case MENELAUS_GPIO_CTRL:
324 return s->dir;
325 case MENELAUS_GPIO_IN:
326 return s->inputs | (~s->dir & s->outputs);
327 case MENELAUS_GPIO_OUT:
328 return s->outputs;
329
330 case MENELAUS_BBSMS:
331 return s->bbsms;
332
333 case MENELAUS_RTC_CTRL:
334 return s->rtc.ctrl;
335 case MENELAUS_RTC_UPDATE:
336 return 0x00;
337 case MENELAUS_RTC_SEC:
338 menelaus_rtc_update(s);
339 return to_bcd(s->rtc.tm.tm_sec);
340 case MENELAUS_RTC_MIN:
341 menelaus_rtc_update(s);
342 return to_bcd(s->rtc.tm.tm_min);
343 case MENELAUS_RTC_HR:
344 menelaus_rtc_update(s);
345 if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */
346 return to_bcd((s->rtc.tm.tm_hour % 12) + 1) |
347 (!!(s->rtc.tm.tm_hour >= 12) << 7); /* PM_nAM */
348 else
349 return to_bcd(s->rtc.tm.tm_hour);
350 case MENELAUS_RTC_DAY:
351 menelaus_rtc_update(s);
352 return to_bcd(s->rtc.tm.tm_mday);
353 case MENELAUS_RTC_MON:
354 menelaus_rtc_update(s);
355 return to_bcd(s->rtc.tm.tm_mon + 1);
356 case MENELAUS_RTC_YR:
357 menelaus_rtc_update(s);
358 return to_bcd(s->rtc.tm.tm_year - 2000);
359 case MENELAUS_RTC_WKDAY:
360 menelaus_rtc_update(s);
361 return to_bcd(s->rtc.tm.tm_wday);
362 case MENELAUS_RTC_AL_SEC:
363 return to_bcd(s->rtc.alm.tm_sec);
364 case MENELAUS_RTC_AL_MIN:
365 return to_bcd(s->rtc.alm.tm_min);
366 case MENELAUS_RTC_AL_HR:
367 if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */
368 return to_bcd((s->rtc.alm.tm_hour % 12) + 1) |
369 (!!(s->rtc.alm.tm_hour >= 12) << 7);/* AL_PM_nAM */
370 else
371 return to_bcd(s->rtc.alm.tm_hour);
372 case MENELAUS_RTC_AL_DAY:
373 return to_bcd(s->rtc.alm.tm_mday);
374 case MENELAUS_RTC_AL_MON:
375 return to_bcd(s->rtc.alm.tm_mon + 1);
376 case MENELAUS_RTC_AL_YR:
377 return to_bcd(s->rtc.alm.tm_year - 2000);
378 case MENELAUS_RTC_COMP_MSB:
379 return (s->rtc.comp >> 8) & 0xff;
380 case MENELAUS_RTC_COMP_LSB:
381 return (s->rtc.comp >> 0) & 0xff;
382
383 case MENELAUS_S1_PULL_EN:
384 return s->pull[0];
385 case MENELAUS_S1_PULL_DIR:
386 return s->pull[1];
387 case MENELAUS_S2_PULL_EN:
388 return s->pull[2];
389 case MENELAUS_S2_PULL_DIR:
390 return s->pull[3];
391
392 case MENELAUS_MCT_CTRL3: reg ++;
393 case MENELAUS_MCT_CTRL2: reg ++;
394 case MENELAUS_MCT_CTRL1:
395 return s->mmc_ctrl[reg];
396 case MENELAUS_MCT_PIN_ST:
397 /* TODO: return the real Card Detect */
398 return 0;
399 case MENELAUS_DEBOUNCE1:
400 return s->mmc_debounce;
401
402 default:
403#ifdef VERBOSE
404 printf("%s: unknown register %02x\n", __FUNCTION__, addr);
405#endif
406 break;
407 }
408 return 0;
409}
410
411static void menelaus_write(void *opaque, uint8_t addr, uint8_t value)
412{
bc24a225 413 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c
AZ		 414 int line;
415 int reg = 0;
416 struct tm tm;
417
418 switch (addr) {
419 case MENELAUS_VCORE_CTRL1:
420 s->vcore[0] = (value & 0xe) | MIN(value & 0x1f, 0x12);
421 break;
422 case MENELAUS_VCORE_CTRL2:
423 s->vcore[1] = value;
424 break;
425 case MENELAUS_VCORE_CTRL3:
426 s->vcore[2] = MIN(value & 0x1f, 0x12);
427 break;
428 case MENELAUS_VCORE_CTRL4:
429 s->vcore[3] = MIN(value & 0x1f, 0x12);
430 break;
431 case MENELAUS_VCORE_CTRL5:
432 s->vcore[4] = value & 3;
433 /* XXX
434 * auto set to 3 on M_Active, nRESWARM
435 * auto set to 0 on M_WaitOn, M_Backup
436 */
437 break;
438
439 case MENELAUS_DCDC_CTRL1:
440 s->dcdc[0] = value & 0x3f;
441 break;
442 case MENELAUS_DCDC_CTRL2:
443 s->dcdc[1] = value & 0x07;
444 /* XXX
445 * auto set to 3 on M_Active, nRESWARM
446 * auto set to 0 on M_WaitOn, M_Backup
447 */
448 break;
449 case MENELAUS_DCDC_CTRL3:
450 s->dcdc[2] = value & 0x07;
451 break;
452
453 case MENELAUS_LDO_CTRL1:
454 s->ldo[0] = value;
455 break;
456 case MENELAUS_LDO_CTRL2:
457 s->ldo[1] = value & 0x7f;
458 /* XXX
459 * auto set to 0x7e on M_WaitOn, M_Backup
460 */
461 break;
462 case MENELAUS_LDO_CTRL3:
463 s->ldo[2] = value & 3;
464 /* XXX
465 * auto set to 3 on M_Active, nRESWARM
466 * auto set to 0 on M_WaitOn, M_Backup
467 */
468 break;
469 case MENELAUS_LDO_CTRL4:
470 s->ldo[3] = value & 3;
471 /* XXX
472 * auto set to 3 on M_Active, nRESWARM
473 * auto set to 0 on M_WaitOn, M_Backup
474 */
475 break;
476 case MENELAUS_LDO_CTRL5:
477 s->ldo[4] = value & 3;
478 /* XXX
479 * auto set to 3 on M_Active, nRESWARM
480 * auto set to 0 on M_WaitOn, M_Backup
481 */
482 break;
483 case MENELAUS_LDO_CTRL6:
484 s->ldo[5] = value & 3;
485 break;
486 case MENELAUS_LDO_CTRL7:
487 s->ldo[6] = value & 3;
488 break;
489 case MENELAUS_LDO_CTRL8:
490 s->ldo[7] = value & 3;
491 break;
492
493 case MENELAUS_SLEEP_CTRL2: reg ++;
494 case MENELAUS_SLEEP_CTRL1:
495 s->sleep[reg] = value;
496 break;
497
498 case MENELAUS_DEVICE_OFF:
dd37dfa9
AF		 499 if (value & 1) {
500 menelaus_reset(I2C_SLAVE(s));
501 }
7e7c5e4c
AZ		 502 break;
503
504 case MENELAUS_OSC_CTRL:
505 s->osc = value & 7;
506 break;
507
508 case MENELAUS_DETECT_CTRL:
509 s->detect = value & 0x7f;
510 break;
511
512 case MENELAUS_INT_MASK1:
513 s->mask &= 0xf00;
514 s->mask |= value << 0;
515 menelaus_update(s);
516 break;
517 case MENELAUS_INT_MASK2:
518 s->mask &= 0x0ff;
519 s->mask |= value << 8;
520 menelaus_update(s);
521 break;
522
523 case MENELAUS_INT_ACK1:
524 s->status &= ~(((uint16_t) value) << 0);
525 menelaus_update(s);
526 break;
527 case MENELAUS_INT_ACK2:
528 s->status &= ~(((uint16_t) value) << 8);
529 menelaus_update(s);
530 break;
531
532 case MENELAUS_GPIO_CTRL:
d3356811
PB		 533 for (line = 0; line < 3; line ++) {
534 if (((s->dir ^ value) >> line) & 1) {
535 qemu_set_irq(s->out[line],
536 ((s->outputs & ~s->dir) >> line) & 1);
537 }
538 }
7e7c5e4c
AZ		 539 s->dir = value & 0x67;
540 break;
541 case MENELAUS_GPIO_OUT:
d3356811
PB		 542 for (line = 0; line < 3; line ++) {
543 if ((((s->outputs ^ value) & ~s->dir) >> line) & 1) {
544 qemu_set_irq(s->out[line], (s->outputs >> line) & 1);
545 }
546 }
7e7c5e4c
AZ		 547 s->outputs = value & 0x07;
548 break;
549
550 case MENELAUS_BBSMS:
551 s->bbsms = 0x0d;
552 break;
553
554 case MENELAUS_RTC_CTRL:
555 if ((s->rtc.ctrl ^ value) & 1) { /* RTC_EN */
556 if (value & 1)
557 menelaus_rtc_start(s);
558 else
559 menelaus_rtc_stop(s);
560 }
561 s->rtc.ctrl = value & 0x1f;
562 menelaus_alm_update(s);
563 break;
564 case MENELAUS_RTC_UPDATE:
565 menelaus_rtc_update(s);
566 memcpy(&tm, &s->rtc.tm, sizeof(tm));
567 switch (value & 0xf) {
568 case 0:
569 break;
570 case 1:
571 tm.tm_sec = s->rtc.new.tm_sec;
572 break;
573 case 2:
574 tm.tm_min = s->rtc.new.tm_min;
575 break;
576 case 3:
577 if (s->rtc.new.tm_hour > 23)
578 goto rtc_badness;
579 tm.tm_hour = s->rtc.new.tm_hour;
580 break;
581 case 4:
582 if (s->rtc.new.tm_mday < 1)
583 goto rtc_badness;
584 /* TODO check range */
585 tm.tm_mday = s->rtc.new.tm_mday;
586 break;
587 case 5:
588 if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
589 goto rtc_badness;
590 tm.tm_mon = s->rtc.new.tm_mon;
591 break;
592 case 6:
593 tm.tm_year = s->rtc.new.tm_year;
594 break;
595 case 7:
596 /* TODO set .tm_mday instead */
597 tm.tm_wday = s->rtc.new.tm_wday;
598 break;
599 case 8:
600 if (s->rtc.new.tm_hour > 23)
601 goto rtc_badness;
602 if (s->rtc.new.tm_mday < 1)
603 goto rtc_badness;
604 if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
605 goto rtc_badness;
606 tm.tm_sec = s->rtc.new.tm_sec;
607 tm.tm_min = s->rtc.new.tm_min;
608 tm.tm_hour = s->rtc.new.tm_hour;
609 tm.tm_mday = s->rtc.new.tm_mday;
610 tm.tm_mon = s->rtc.new.tm_mon;
611 tm.tm_year = s->rtc.new.tm_year;
612 break;
613 rtc_badness:
614 default:
615 fprintf(stderr, "%s: bad RTC_UPDATE value %02x\n",
616 __FUNCTION__, value);
617 s->status |= 1 << 10; /* RTCERR */
618 menelaus_update(s);
619 }
aec454d2 620 s->rtc.sec_offset = qemu_timedate_diff(&tm);
7e7c5e4c
AZ		 621 break;
622 case MENELAUS_RTC_SEC:
623 s->rtc.tm.tm_sec = from_bcd(value & 0x7f);
624 break;
625 case MENELAUS_RTC_MIN:
626 s->rtc.tm.tm_min = from_bcd(value & 0x7f);
627 break;
628 case MENELAUS_RTC_HR:
629 s->rtc.tm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */
630 MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
631 from_bcd(value & 0x3f);
632 break;
633 case MENELAUS_RTC_DAY:
634 s->rtc.tm.tm_mday = from_bcd(value);
635 break;
636 case MENELAUS_RTC_MON:
637 s->rtc.tm.tm_mon = MAX(1, from_bcd(value)) - 1;
638 break;
639 case MENELAUS_RTC_YR:
640 s->rtc.tm.tm_year = 2000 + from_bcd(value);
641 break;
642 case MENELAUS_RTC_WKDAY:
643 s->rtc.tm.tm_mday = from_bcd(value);
644 break;
645 case MENELAUS_RTC_AL_SEC:
646 s->rtc.alm.tm_sec = from_bcd(value & 0x7f);
647 menelaus_alm_update(s);
648 break;
649 case MENELAUS_RTC_AL_MIN:
650 s->rtc.alm.tm_min = from_bcd(value & 0x7f);
651 menelaus_alm_update(s);
652 break;
653 case MENELAUS_RTC_AL_HR:
654 s->rtc.alm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */
655 MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
656 from_bcd(value & 0x3f);
657 menelaus_alm_update(s);
658 break;
659 case MENELAUS_RTC_AL_DAY:
660 s->rtc.alm.tm_mday = from_bcd(value);
661 menelaus_alm_update(s);
662 break;
663 case MENELAUS_RTC_AL_MON:
664 s->rtc.alm.tm_mon = MAX(1, from_bcd(value)) - 1;
665 menelaus_alm_update(s);
666 break;
667 case MENELAUS_RTC_AL_YR:
668 s->rtc.alm.tm_year = 2000 + from_bcd(value);
669 menelaus_alm_update(s);
670 break;
671 case MENELAUS_RTC_COMP_MSB:
672 s->rtc.comp &= 0xff;
673 s->rtc.comp |= value << 8;
674 break;
675 case MENELAUS_RTC_COMP_LSB:
676 s->rtc.comp &= 0xff << 8;
677 s->rtc.comp |= value;
678 break;
679
680 case MENELAUS_S1_PULL_EN:
681 s->pull[0] = value;
682 break;
683 case MENELAUS_S1_PULL_DIR:
684 s->pull[1] = value & 0x1f;
685 break;
686 case MENELAUS_S2_PULL_EN:
687 s->pull[2] = value;
688 break;
689 case MENELAUS_S2_PULL_DIR:
690 s->pull[3] = value & 0x1f;
691 break;
692
693 case MENELAUS_MCT_CTRL1:
694 s->mmc_ctrl[0] = value & 0x7f;
695 break;
696 case MENELAUS_MCT_CTRL2:
697 s->mmc_ctrl[1] = value;
698 /* TODO update Card Detect interrupts */
699 break;
700 case MENELAUS_MCT_CTRL3:
701 s->mmc_ctrl[2] = value & 0xf;
702 break;
703 case MENELAUS_DEBOUNCE1:
704 s->mmc_debounce = value & 0x3f;
705 break;
706
707 default:
708#ifdef VERBOSE
709 printf("%s: unknown register %02x\n", __FUNCTION__, addr);
710#endif
711 }
712}
713
9e07bdf8 714static void menelaus_event(I2CSlave *i2c, enum i2c_event event)
7e7c5e4c 715{
dd37dfa9 716 MenelausState *s = TWL92230(i2c);
7e7c5e4c
AZ		 717
718 if (event == I2C_START_SEND)
719 s->firstbyte = 1;
720}
721
9e07bdf8 722static int menelaus_tx(I2CSlave *i2c, uint8_t data)
7e7c5e4c 723{
dd37dfa9
AF		 724 MenelausState *s = TWL92230(i2c);
725
7e7c5e4c
AZ		 726 /* Interpret register address byte */
727 if (s->firstbyte) {
728 s->reg = data;
729 s->firstbyte = 0;
730 } else
731 menelaus_write(s, s->reg ++, data);
732
733 return 0;
734}
735
9e07bdf8 736static int menelaus_rx(I2CSlave *i2c)
7e7c5e4c 737{
dd37dfa9 738 MenelausState *s = TWL92230(i2c);
7e7c5e4c
AZ		 739
740 return menelaus_read(s, s->reg ++);
741}
742
f0495f56
JQ		 743/* Save restore 32 bit int as uint16_t
744 This is a Big hack, but it is how the old state did it.
745 Or we broke compatibility in the state, or we can't use struct tm
746 */
7e7c5e4c 747
f0495f56
JQ		 748static int get_int32_as_uint16(QEMUFile *f, void *pv, size_t size)
749{
750 int *v = pv;
751 *v = qemu_get_be16(f);
752 return 0;
7e7c5e4c
AZ		 753}
754
f0495f56 755static void put_int32_as_uint16(QEMUFile *f, void *pv, size_t size)
7e7c5e4c 756{
f0495f56
JQ		 757 int *v = pv;
758 qemu_put_be16(f, *v);
759}
7e7c5e4c 760
d05ac8fa 761static const VMStateInfo vmstate_hack_int32_as_uint16 = {
f0495f56
JQ		 762 .name = "int32_as_uint16",
763 .get = get_int32_as_uint16,
764 .put = put_int32_as_uint16,
765};
7e7c5e4c 766
f0495f56
JQ		 767#define VMSTATE_UINT16_HACK(_f, _s) \
768 VMSTATE_SINGLE(_f, _s, 0, vmstate_hack_int32_as_uint16, int32_t)
769
770
771static const VMStateDescription vmstate_menelaus_tm = {
772 .name = "menelaus_tm",
773 .version_id = 0,
774 .minimum_version_id = 0,
775 .minimum_version_id_old = 0,
776 .fields = (VMStateField []) {
777 VMSTATE_UINT16_HACK(tm_sec, struct tm),
778 VMSTATE_UINT16_HACK(tm_min, struct tm),
779 VMSTATE_UINT16_HACK(tm_hour, struct tm),
780 VMSTATE_UINT16_HACK(tm_mday, struct tm),
781 VMSTATE_UINT16_HACK(tm_min, struct tm),
782 VMSTATE_UINT16_HACK(tm_year, struct tm),
783 VMSTATE_END_OF_LIST()
784 }
785};
7e7c5e4c 786
f0495f56 787static void menelaus_pre_save(void *opaque)
7e7c5e4c 788{
f0495f56
JQ		 789 MenelausState *s = opaque;
790 /* Should be <= 1000 */
884f17c2 791 s->rtc_next_vmstate = s->rtc.next - qemu_clock_get_ms(rtc_clock);
f0495f56 792}
7e7c5e4c 793
f0495f56
JQ		 794static int menelaus_post_load(void *opaque, int version_id)
795{
796 MenelausState *s = opaque;
7e7c5e4c
AZ		 797
798 if (s->rtc.ctrl & 1) /* RTC_EN */
799 menelaus_rtc_stop(s);
f0495f56
JQ		 800
801 s->rtc.next = s->rtc_next_vmstate;
802
7e7c5e4c
AZ		 803 menelaus_alm_update(s);
804 menelaus_update(s);
805 if (s->rtc.ctrl & 1) /* RTC_EN */
806 menelaus_rtc_start(s);
7e7c5e4c
AZ		 807 return 0;
808}
809
f0495f56
JQ		 810static const VMStateDescription vmstate_menelaus = {
811 .name = "menelaus",
812 .version_id = 0,
813 .minimum_version_id = 0,
814 .minimum_version_id_old = 0,
815 .pre_save = menelaus_pre_save,
816 .post_load = menelaus_post_load,
817 .fields = (VMStateField []) {
818 VMSTATE_INT32(firstbyte, MenelausState),
819 VMSTATE_UINT8(reg, MenelausState),
820 VMSTATE_UINT8_ARRAY(vcore, MenelausState, 5),
821 VMSTATE_UINT8_ARRAY(dcdc, MenelausState, 3),
822 VMSTATE_UINT8_ARRAY(ldo, MenelausState, 8),
823 VMSTATE_UINT8_ARRAY(sleep, MenelausState, 2),
824 VMSTATE_UINT8(osc, MenelausState),
825 VMSTATE_UINT8(detect, MenelausState),
826 VMSTATE_UINT16(mask, MenelausState),
827 VMSTATE_UINT16(status, MenelausState),
828 VMSTATE_UINT8(dir, MenelausState),
829 VMSTATE_UINT8(inputs, MenelausState),
830 VMSTATE_UINT8(outputs, MenelausState),
831 VMSTATE_UINT8(bbsms, MenelausState),
832 VMSTATE_UINT8_ARRAY(pull, MenelausState, 4),
833 VMSTATE_UINT8_ARRAY(mmc_ctrl, MenelausState, 3),
834 VMSTATE_UINT8(mmc_debounce, MenelausState),
835 VMSTATE_UINT8(rtc.ctrl, MenelausState),
836 VMSTATE_UINT16(rtc.comp, MenelausState),
837 VMSTATE_UINT16(rtc_next_vmstate, MenelausState),
838 VMSTATE_STRUCT(rtc.new, MenelausState, 0, vmstate_menelaus_tm,
839 struct tm),
840 VMSTATE_STRUCT(rtc.alm, MenelausState, 0, vmstate_menelaus_tm,
841 struct tm),
842 VMSTATE_UINT8(pwrbtn_state, MenelausState),
dd37dfa9 843 VMSTATE_I2C_SLAVE(parent_obj, MenelausState),
f0495f56
JQ		 844 VMSTATE_END_OF_LIST()
845 }
846};
847
9e07bdf8 848static int twl92230_init(I2CSlave *i2c)
7e7c5e4c 849{
dd37dfa9
AF		 850 DeviceState *dev = DEVICE(i2c);
851 MenelausState *s = TWL92230(i2c);
7e7c5e4c 852
884f17c2 853 s->rtc.hz_tm = timer_new_ms(rtc_clock, menelaus_rtc_hz, s);
d3356811 854 /* Three output pins plus one interrupt pin. */
dd37dfa9 855 qdev_init_gpio_out(dev, s->out, 4);
dd4427a6
PB		 856
857 /* Three input pins plus one power-button pin. */
dd37dfa9 858 qdev_init_gpio_in(dev, menelaus_gpio_set, 4);
7e7c5e4c 859
dd37dfa9 860 menelaus_reset(i2c);
7e7c5e4c 861
81a322d4 862 return 0;
7e7c5e4c
AZ		 863}
864
b5ea9327
AL		 865static void twl92230_class_init(ObjectClass *klass, void *data)
866{
39bffca2 867 DeviceClass *dc = DEVICE_CLASS(klass);
b5ea9327
AL		 868 I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
869
870 sc->init = twl92230_init;
871 sc->event = menelaus_event;
872 sc->recv = menelaus_rx;
873 sc->send = menelaus_tx;
39bffca2 874 dc->vmsd = &vmstate_menelaus;
b5ea9327
AL		 875}
876
8c43a6f0 877static const TypeInfo twl92230_info = {
dd37dfa9 878 .name = TYPE_TWL92230,
39bffca2
AL		 879 .parent = TYPE_I2C_SLAVE,
880 .instance_size = sizeof(MenelausState),
881 .class_init = twl92230_class_init,
d3356811 882};
7e7c5e4c 883
83f7d43a 884static void twl92230_register_types(void)
7e7c5e4c 885{
39bffca2 886 type_register_static(&twl92230_info);
7e7c5e4c 887}
d3356811 888
83f7d43a 889type_init(twl92230_register_types)
Empty description
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