[qemu.git] / hw / arm / fsl-imx25.c

/*
 * Copyright (c) 2013 Jean-Christophe Dubois <[email protected]>
 *
 * i.MX25 SOC emulation.
 *
 * Based on hw/arm/xlnx-zynqmp.c
 *
 * Copyright (C) 2015 Xilinx Inc
 * Written by Peter Crosthwaite <[email protected]>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/arm/fsl-imx25.h"
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
#include "hw/boards.h"
#include "chardev/char.h"

static void fsl_imx25_init(Object *obj)
{
    FslIMX25State *s = FSL_IMX25(obj);
    int i;

    object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU);

    sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
                          TYPE_IMX_AVIC);

    sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM);

    for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
        sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
                              TYPE_IMX_SERIAL);
    }

    for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
        sysbus_init_child_obj(obj, "gpt[*]", &s->gpt[i], sizeof(s->gpt[i]),
                              TYPE_IMX25_GPT);
    }

    for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
        sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
                              TYPE_IMX_EPIT);
    }

    sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC);

    for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
        sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
                              TYPE_IMX_I2C);
    }

    for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
        sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
                              TYPE_IMX_GPIO);
    }
}

static void fsl_imx25_realize(DeviceState *dev, Error **errp)
{
    FslIMX25State *s = FSL_IMX25(dev);
    uint8_t i;
    Error *err = NULL;

    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));

    object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);

    /* Initialize all UARTs */
    for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } serial_table[FSL_IMX25_NUM_UARTS] = {
            { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
            { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
            { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
            { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
            { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
        };

        qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));

        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            serial_table[i].irq));
    }

    /* Initialize all GPT timers */
    for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } gpt_table[FSL_IMX25_NUM_GPTS] = {
            { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
            { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
            { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
            { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
        };

        s->gpt[i].ccm = IMX_CCM(&s->ccm);

        object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            gpt_table[i].irq));
    }

    /* Initialize all EPIT timers */
    for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } epit_table[FSL_IMX25_NUM_EPITS] = {
            { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
            { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
        };

        s->epit[i].ccm = IMX_CCM(&s->ccm);

        object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            epit_table[i].irq));
    }

    qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);

    object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
                       qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));


    /* Initialize all I2C */
    for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } i2c_table[FSL_IMX25_NUM_I2CS] = {
            { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
            { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
            { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
        };

        object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            i2c_table[i].irq));
    }

    /* Initialize all GPIOs */
    for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } gpio_table[FSL_IMX25_NUM_GPIOS] = {
            { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ },
            { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ },
            { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ },
            { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
        };

        object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
        /* Connect GPIO IRQ to PIC */
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            gpio_table[i].irq));
    }

    /* initialize 2 x 16 KB ROM */
    memory_region_init_rom(&s->rom[0], NULL,
                           "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
                                &s->rom[0]);
    memory_region_init_rom(&s->rom[1], NULL,
                           "imx25.rom1", FSL_IMX25_ROM1_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
                                &s->rom[1]);

    /* initialize internal RAM (128 KB) */
    memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
                           &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
                                &s->iram);

    /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
    memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias",
                             &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
                                &s->iram_alias);
}

static void fsl_imx25_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = fsl_imx25_realize;
    dc->desc = "i.MX25 SOC";
    /*
     * Reason: uses serial_hds in realize and the imx25 board does not
     * support multiple CPUs
     */
    dc->user_creatable = false;
}

static const TypeInfo fsl_imx25_type_info = {
    .name = TYPE_FSL_IMX25,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(FslIMX25State),
    .instance_init = fsl_imx25_init,
    .class_init = fsl_imx25_class_init,
};

static void fsl_imx25_register_types(void)
{
    type_register_static(&fsl_imx25_type_info);
}

type_init(fsl_imx25_register_types)
Commit	Line	Data
ee708c99 JCD	1	/*
	2	* Copyright (c) 2013 Jean-Christophe Dubois <[email protected]>
	3	*
	4	* i.MX25 SOC emulation.
	5	*
	6	* Based on hw/arm/xlnx-zynqmp.c
	7	*
	8	* Copyright (C) 2015 Xilinx Inc
	9	* Written by Peter Crosthwaite <[email protected]>
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful, but WITHOUT
	17	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	18	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	19	* for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License along
	22	* with this program; if not, see <http://www.gnu.org/licenses/>.
	23	*/
	24
12b16722	25	#include "qemu/osdep.h"
da34e65c	26	#include "qapi/error.h"
4771d756 PB	27	#include "qemu-common.h"
4771d756 PB	28	#include "cpu.h"
ee708c99 JCD	29	#include "hw/arm/fsl-imx25.h"
	30	#include "sysemu/sysemu.h"
	31	#include "exec/address-spaces.h"
	32	#include "hw/boards.h"
8228e353	33	#include "chardev/char.h"
ee708c99 JCD	34
	35	static void fsl_imx25_init(Object *obj)
	36	{
	37	FslIMX25State *s = FSL_IMX25(obj);
	38	int i;
	39
	40	object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU);
	41
51dd12ac TH	42	sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
51dd12ac TH	43	TYPE_IMX_AVIC);
ee708c99	44
51dd12ac	45	sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM);
ee708c99 JCD	46
ee708c99 JCD	47	for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
51dd12ac TH	48	sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
51dd12ac TH	49	TYPE_IMX_SERIAL);
ee708c99 JCD	50	}
	51
	52	for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
51dd12ac TH	53	sysbus_init_child_obj(obj, "gpt[*]", &s->gpt[i], sizeof(s->gpt[i]),
51dd12ac TH	54	TYPE_IMX25_GPT);
ee708c99 JCD	55	}
	56
	57	for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
51dd12ac TH	58	sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
51dd12ac TH	59	TYPE_IMX_EPIT);
ee708c99 JCD	60	}
ee708c99 JCD	61
51dd12ac	62	sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC);
ee708c99 JCD	63
ee708c99 JCD	64	for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
51dd12ac TH	65	sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
51dd12ac TH	66	TYPE_IMX_I2C);
ee708c99	67	}
6abc7158 JCD	68
6abc7158 JCD	69	for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
51dd12ac TH	70	sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
51dd12ac TH	71	TYPE_IMX_GPIO);
6abc7158	72	}
ee708c99 JCD	73	}
	74
	75	static void fsl_imx25_realize(DeviceState dev, Error *errp)
	76	{
	77	FslIMX25State *s = FSL_IMX25(dev);
	78	uint8_t i;
	79	Error *err = NULL;
	80
	81	object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
	82	if (err) {
	83	error_propagate(errp, err);
	84	return;
	85	}
	86
	87	object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
	88	if (err) {
	89	error_propagate(errp, err);
	90	return;
	91	}
	92	sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
	93	sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
	94	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
	95	sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
	96	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
	97
	98	object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
	99	if (err) {
	100	error_propagate(errp, err);
	101	return;
	102	}
	103	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);
	104
	105	/* Initialize all UARTs */
	106	for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
	107	static const struct {
	108	hwaddr addr;
	109	unsigned int irq;
	110	} serial_table[FSL_IMX25_NUM_UARTS] = {
	111	{ FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
	112	{ FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
	113	{ FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
	114	{ FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
	115	{ FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
	116	};
	117
fc38a112	118	qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
ee708c99 JCD	119
	120	object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
	121	if (err) {
	122	error_propagate(errp, err);
	123	return;
	124	}
	125	sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
	126	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
	127	qdev_get_gpio_in(DEVICE(&s->avic),
	128	serial_table[i].irq));
	129	}
	130
	131	/* Initialize all GPT timers */
	132	for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
	133	static const struct {
	134	hwaddr addr;
	135	unsigned int irq;
	136	} gpt_table[FSL_IMX25_NUM_GPTS] = {
	137	{ FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
	138	{ FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
	139	{ FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
	140	{ FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
	141	};
	142
cb54d868	143	s->gpt[i].ccm = IMX_CCM(&s->ccm);
ee708c99 JCD	144
	145	object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);
	146	if (err) {
	147	error_propagate(errp, err);
	148	return;
	149	}
	150	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
	151	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
	152	qdev_get_gpio_in(DEVICE(&s->avic),
	153	gpt_table[i].irq));
	154	}
	155
	156	/* Initialize all EPIT timers */
	157	for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
	158	static const struct {
	159	hwaddr addr;
	160	unsigned int irq;
	161	} epit_table[FSL_IMX25_NUM_EPITS] = {
	162	{ FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
	163	{ FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
	164	};
	165
cb54d868	166	s->epit[i].ccm = IMX_CCM(&s->ccm);
ee708c99 JCD	167
	168	object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
	169	if (err) {
	170	error_propagate(errp, err);
	171	return;
	172	}
	173	sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
	174	sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
	175	qdev_get_gpio_in(DEVICE(&s->avic),
	176	epit_table[i].irq));
	177	}
	178
	179	qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
a699b410	180
ee708c99 JCD	181	object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);
	182	if (err) {
	183	error_propagate(errp, err);
	184	return;
	185	}
	186	sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
	187	sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
	188	qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
	189
	190
	191	/* Initialize all I2C */
	192	for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
	193	static const struct {
	194	hwaddr addr;
	195	unsigned int irq;
	196	} i2c_table[FSL_IMX25_NUM_I2CS] = {
	197	{ FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
	198	{ FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
	199	{ FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
	200	};
	201
	202	object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
	203	if (err) {
	204	error_propagate(errp, err);
	205	return;
	206	}
	207	sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
	208	sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
	209	qdev_get_gpio_in(DEVICE(&s->avic),
	210	i2c_table[i].irq));
	211	}
	212
6abc7158 JCD	213	/* Initialize all GPIOs */
	214	for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
	215	static const struct {
	216	hwaddr addr;
	217	unsigned int irq;
	218	} gpio_table[FSL_IMX25_NUM_GPIOS] = {
	219	{ FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ },
	220	{ FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ },
	221	{ FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ },
	222	{ FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
	223	};
	224
	225	object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
	226	if (err) {
	227	error_propagate(errp, err);
	228	return;
	229	}
	230	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
	231	/* Connect GPIO IRQ to PIC */
	232	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
	233	qdev_get_gpio_in(DEVICE(&s->avic),
	234	gpio_table[i].irq));
	235	}
	236
ee708c99	237	/* initialize 2 x 16 KB ROM */
eda40cc1	238	memory_region_init_rom(&s->rom[0], NULL,
a7aeb5f7	239	"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
ee708c99 JCD	240	if (err) {
	241	error_propagate(errp, err);
	242	return;
	243	}
	244	memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
	245	&s->rom[0]);
eda40cc1	246	memory_region_init_rom(&s->rom[1], NULL,
a7aeb5f7	247	"imx25.rom1", FSL_IMX25_ROM1_SIZE, &err);
ee708c99 JCD	248	if (err) {
	249	error_propagate(errp, err);
	250	return;
	251	}
	252	memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
	253	&s->rom[1]);
	254
	255	/* initialize internal RAM (128 KB) */
98a99ce0	256	memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
ee708c99 JCD	257	&err);
	258	if (err) {
	259	error_propagate(errp, err);
	260	return;
	261	}
	262	memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
	263	&s->iram);
ee708c99 JCD	264
	265	/* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
	266	memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias",
	267	&s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
	268	memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
	269	&s->iram_alias);
	270	}
	271
	272	static void fsl_imx25_class_init(ObjectClass oc, void data)
	273	{
	274	DeviceClass *dc = DEVICE_CLASS(oc);
	275
	276	dc->realize = fsl_imx25_realize;
eccfa35e	277	dc->desc = "i.MX25 SOC";
5e0c7044 TH	278	/*
	279	* Reason: uses serial_hds in realize and the imx25 board does not
	280	* support multiple CPUs
	281	*/
	282	dc->user_creatable = false;
ee708c99 JCD	283	}
	284
	285	static const TypeInfo fsl_imx25_type_info = {
	286	.name = TYPE_FSL_IMX25,
	287	.parent = TYPE_DEVICE,
	288	.instance_size = sizeof(FslIMX25State),
	289	.instance_init = fsl_imx25_init,
	290	.class_init = fsl_imx25_class_init,
	291	};
	292
	293	static void fsl_imx25_register_types(void)
	294	{
	295	type_register_static(&fsl_imx25_type_info);
	296	}
	297
	298	type_init(fsl_imx25_register_types)