[qemu.git] / softmmu_template.h

/*
 *  Software MMU support
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#define DATA_SIZE (1 << SHIFT)

#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#else
#error unsupported data size
#endif

#ifdef SOFTMMU_CODE_ACCESS
#define READ_ACCESS_TYPE 2
#define ADDR_READ addr_code
#else
#define READ_ACCESS_TYPE 0
#define ADDR_READ addr_read
#endif

static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr, 
                                                        int is_user,
                                                        void *retaddr);
static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr, 
                                              target_ulong tlb_addr)
{
    DATA_TYPE res;
    int index;

    index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
#if SHIFT <= 2
    res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
    res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
#else
    res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
    res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
#endif
#endif /* SHIFT > 2 */
    return res;
}

/* handle all cases except unaligned access which span two pages */
DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                         int is_user)
{
    DATA_TYPE res;
    int index;
    target_ulong tlb_addr;
    target_phys_addr_t physaddr;
    void *retaddr;
    
    /* test if there is match for unaligned or IO access */
    /* XXX: could done more in memory macro in a non portable way */
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[is_user][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        physaddr = addr + env->tlb_table[is_user][index].addend;
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
            /* slow unaligned access (it spans two pages or IO) */
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(addr, READ_ACCESS_TYPE, is_user, retaddr);
#endif
            res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr, 
                                                         is_user, retaddr);
        } else {
            /* unaligned/aligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(addr, READ_ACCESS_TYPE, is_user, retaddr);
            }
#endif
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(addr, READ_ACCESS_TYPE, is_user, retaddr);
#endif
        tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
        goto redo;
    }
    return res;
}

/* handle all unaligned cases */
static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr, 
                                                        int is_user,
                                                        void *retaddr)
{
    DATA_TYPE res, res1, res2;
    int index, shift;
    target_phys_addr_t physaddr;
    target_ulong tlb_addr, addr1, addr2;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[is_user][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        physaddr = addr + env->tlb_table[is_user][index].addend;
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* slow unaligned access (it spans two pages) */
            addr1 = addr & ~(DATA_SIZE - 1);
            addr2 = addr1 + DATA_SIZE;
            res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1, 
                                                          is_user, retaddr);
            res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2, 
                                                          is_user, retaddr);
            shift = (addr & (DATA_SIZE - 1)) * 8;
#ifdef TARGET_WORDS_BIGENDIAN
            res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
#else
            res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
#endif
            res = (DATA_TYPE)res;
        } else {
            /* unaligned/aligned access in the same page */
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
        goto redo;
    }
    return res;
}

#ifndef SOFTMMU_CODE_ACCESS

static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, 
                                                   DATA_TYPE val, 
                                                   int is_user,
                                                   void *retaddr);

static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr, 
                                          DATA_TYPE val,
                                          target_ulong tlb_addr,
                                          void *retaddr)
{
    int index;

    index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
    env->mem_write_vaddr = tlb_addr;
    env->mem_write_pc = (unsigned long)retaddr;
#if SHIFT <= 2
    io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
#else
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
#endif
#endif /* SHIFT > 2 */
}

void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, 
                                                    DATA_TYPE val,
                                                    int is_user)
{
    target_phys_addr_t physaddr;
    target_ulong tlb_addr;
    void *retaddr;
    int index;
    
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[is_user][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        physaddr = addr + env->tlb_table[is_user][index].addend;
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(addr, 1, is_user, retaddr);
#endif
            glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val, 
                                                   is_user, retaddr);
        } else {
            /* aligned/unaligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(addr, 1, is_user, retaddr);
            }
#endif
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(addr, 1, is_user, retaddr);
#endif
        tlb_fill(addr, 1, is_user, retaddr);
        goto redo;
    }
}

/* handles all unaligned cases */
static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, 
                                                   DATA_TYPE val,
                                                   int is_user,
                                                   void *retaddr)
{
    target_phys_addr_t physaddr;
    target_ulong tlb_addr;
    int index, i;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[is_user][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        physaddr = addr + env->tlb_table[is_user][index].addend;
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* XXX: not efficient, but simple */
            for(i = 0;i < DATA_SIZE; i++) {
#ifdef TARGET_WORDS_BIGENDIAN
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)), 
                                          is_user, retaddr);
#else
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8), 
                                          is_user, retaddr);
#endif
            }
        } else {
            /* aligned/unaligned access in the same page */
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, 1, is_user, retaddr);
        goto redo;
    }
}

#endif /* !defined(SOFTMMU_CODE_ACCESS) */

#undef READ_ACCESS_TYPE
#undef SHIFT
#undef DATA_TYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef ADDR_READ
Commit	Line	Data
b92e5a22 FB	1	/*
	2	* Software MMU support
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#define DATA_SIZE (1 << SHIFT)
	21
	22	#if DATA_SIZE == 8
	23	#define SUFFIX q
61382a50	24	#define USUFFIX q
b92e5a22 FB	25	#define DATA_TYPE uint64_t
	26	#elif DATA_SIZE == 4
	27	#define SUFFIX l
61382a50	28	#define USUFFIX l
b92e5a22 FB	29	#define DATA_TYPE uint32_t
	30	#elif DATA_SIZE == 2
	31	#define SUFFIX w
61382a50	32	#define USUFFIX uw
b92e5a22 FB	33	#define DATA_TYPE uint16_t
	34	#elif DATA_SIZE == 1
	35	#define SUFFIX b
61382a50	36	#define USUFFIX ub
b92e5a22 FB	37	#define DATA_TYPE uint8_t
	38	#else
	39	#error unsupported data size
	40	#endif
	41
b769d8fe FB	42	#ifdef SOFTMMU_CODE_ACCESS
b769d8fe FB	43	#define READ_ACCESS_TYPE 2
84b7b8e7	44	#define ADDR_READ addr_code
b769d8fe FB	45	#else
b769d8fe FB	46	#define READ_ACCESS_TYPE 0
84b7b8e7	47	#define ADDR_READ addr_read
b769d8fe FB	48	#endif
b769d8fe FB	49
c27004ec	50	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50 FB	51	int is_user,
61382a50 FB	52	void *retaddr);
108c49b8	53	static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
c27004ec	54	target_ulong tlb_addr)
b92e5a22 FB	55	{
	56	DATA_TYPE res;
	57	int index;
	58
	59	index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
	60	#if SHIFT <= 2
a4193c8a	61	res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
b92e5a22 FB	62	#else
b92e5a22 FB	63	#ifdef TARGET_WORDS_BIGENDIAN
a4193c8a FB	64	res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
a4193c8a FB	65	res \|= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
b92e5a22	66	#else
a4193c8a FB	67	res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
a4193c8a FB	68	res \|= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
b92e5a22 FB	69	#endif
	70	#endif /* SHIFT > 2 */
	71	return res;
	72	}
	73
b92e5a22	74	/* handle all cases except unaligned access which span two pages */
c27004ec	75	DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50	76	int is_user)
b92e5a22 FB	77	{
b92e5a22 FB	78	DATA_TYPE res;
61382a50	79	int index;
c27004ec	80	target_ulong tlb_addr;
108c49b8	81	target_phys_addr_t physaddr;
b92e5a22 FB	82	void *retaddr;
	83
	84	/* test if there is match for unaligned or IO access */
	85	/* XXX: could done more in memory macro in a non portable way */
b92e5a22 FB	86	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	87	redo:
84b7b8e7	88	tlb_addr = env->tlb_table[is_user][index].ADDR_READ;
b92e5a22	89	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
84b7b8e7	90	physaddr = addr + env->tlb_table[is_user][index].addend;
b92e5a22 FB	91	if (tlb_addr & ~TARGET_PAGE_MASK) {
	92	/* IO access */
	93	if ((addr & (DATA_SIZE - 1)) != 0)
	94	goto do_unaligned_access;
	95	res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
98699967	96	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	97	/* slow unaligned access (it spans two pages or IO) */
b92e5a22 FB	98	do_unaligned_access:
61382a50	99	retaddr = GETPC();
a64d4718 FB	100	#ifdef ALIGNED_ONLY
	101	do_unaligned_access(addr, READ_ACCESS_TYPE, is_user, retaddr);
	102	#endif
61382a50 FB	103	res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
61382a50 FB	104	is_user, retaddr);
b92e5a22	105	} else {
a64d4718 FB	106	/* unaligned/aligned access in the same page */
	107	#ifdef ALIGNED_ONLY
	108	if ((addr & (DATA_SIZE - 1)) != 0) {
	109	retaddr = GETPC();
	110	do_unaligned_access(addr, READ_ACCESS_TYPE, is_user, retaddr);
	111	}
	112	#endif
108c49b8	113	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
b92e5a22 FB	114	}
	115	} else {
	116	/* the page is not in the TLB : fill it */
61382a50	117	retaddr = GETPC();
a64d4718 FB	118	#ifdef ALIGNED_ONLY
	119	if ((addr & (DATA_SIZE - 1)) != 0)
	120	do_unaligned_access(addr, READ_ACCESS_TYPE, is_user, retaddr);
	121	#endif
b769d8fe	122	tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
b92e5a22 FB	123	goto redo;
	124	}
	125	return res;
	126	}
	127
	128	/* handle all unaligned cases */
c27004ec	129	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50 FB	130	int is_user,
61382a50 FB	131	void *retaddr)
b92e5a22 FB	132	{
b92e5a22 FB	133	DATA_TYPE res, res1, res2;
61382a50	134	int index, shift;
108c49b8	135	target_phys_addr_t physaddr;
c27004ec	136	target_ulong tlb_addr, addr1, addr2;
b92e5a22	137
b92e5a22 FB	138	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	139	redo:
84b7b8e7	140	tlb_addr = env->tlb_table[is_user][index].ADDR_READ;
b92e5a22	141	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
84b7b8e7	142	physaddr = addr + env->tlb_table[is_user][index].addend;
b92e5a22 FB	143	if (tlb_addr & ~TARGET_PAGE_MASK) {
	144	/* IO access */
	145	if ((addr & (DATA_SIZE - 1)) != 0)
	146	goto do_unaligned_access;
	147	res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
98699967	148	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	149	do_unaligned_access:
	150	/* slow unaligned access (it spans two pages) */
	151	addr1 = addr & ~(DATA_SIZE - 1);
	152	addr2 = addr1 + DATA_SIZE;
61382a50 FB	153	res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
	154	is_user, retaddr);
	155	res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
	156	is_user, retaddr);
b92e5a22 FB	157	shift = (addr & (DATA_SIZE - 1)) * 8;
	158	#ifdef TARGET_WORDS_BIGENDIAN
	159	res = (res1 << shift) \| (res2 >> ((DATA_SIZE * 8) - shift));
	160	#else
	161	res = (res1 >> shift) \| (res2 << ((DATA_SIZE * 8) - shift));
	162	#endif
6986f88c	163	res = (DATA_TYPE)res;
b92e5a22 FB	164	} else {
b92e5a22 FB	165	/* unaligned/aligned access in the same page */
108c49b8	166	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
b92e5a22 FB	167	}
	168	} else {
	169	/* the page is not in the TLB : fill it */
b769d8fe	170	tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
b92e5a22 FB	171	goto redo;
	172	}
	173	return res;
	174	}
	175
b769d8fe FB	176	#ifndef SOFTMMU_CODE_ACCESS
b769d8fe FB	177
c27004ec	178	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
b769d8fe FB	179	DATA_TYPE val,
	180	int is_user,
	181	void *retaddr);
	182
108c49b8	183	static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
b769d8fe	184	DATA_TYPE val,
c27004ec	185	target_ulong tlb_addr,
b769d8fe FB	186	void *retaddr)
	187	{
	188	int index;
	189
	190	index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
	191	env->mem_write_vaddr = tlb_addr;
	192	env->mem_write_pc = (unsigned long)retaddr;
	193	#if SHIFT <= 2
	194	io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
	195	#else
	196	#ifdef TARGET_WORDS_BIGENDIAN
	197	io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
	198	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
	199	#else
	200	io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
	201	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
	202	#endif
	203	#endif /* SHIFT > 2 */
	204	}
b92e5a22	205
c27004ec	206	void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50 FB	207	DATA_TYPE val,
61382a50 FB	208	int is_user)
b92e5a22	209	{
108c49b8	210	target_phys_addr_t physaddr;
c27004ec	211	target_ulong tlb_addr;
b92e5a22	212	void *retaddr;
61382a50	213	int index;
b92e5a22	214
b92e5a22 FB	215	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	216	redo:
84b7b8e7	217	tlb_addr = env->tlb_table[is_user][index].addr_write;
b92e5a22	218	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
84b7b8e7	219	physaddr = addr + env->tlb_table[is_user][index].addend;
b92e5a22 FB	220	if (tlb_addr & ~TARGET_PAGE_MASK) {
	221	/* IO access */
	222	if ((addr & (DATA_SIZE - 1)) != 0)
	223	goto do_unaligned_access;
d720b93d FB	224	retaddr = GETPC();
d720b93d FB	225	glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
98699967	226	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22	227	do_unaligned_access:
61382a50	228	retaddr = GETPC();
a64d4718 FB	229	#ifdef ALIGNED_ONLY
	230	do_unaligned_access(addr, 1, is_user, retaddr);
	231	#endif
61382a50 FB	232	glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
61382a50 FB	233	is_user, retaddr);
b92e5a22 FB	234	} else {
b92e5a22 FB	235	/* aligned/unaligned access in the same page */
a64d4718 FB	236	#ifdef ALIGNED_ONLY
	237	if ((addr & (DATA_SIZE - 1)) != 0) {
	238	retaddr = GETPC();
	239	do_unaligned_access(addr, 1, is_user, retaddr);
	240	}
	241	#endif
108c49b8	242	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
b92e5a22 FB	243	}
	244	} else {
	245	/* the page is not in the TLB : fill it */
61382a50	246	retaddr = GETPC();
a64d4718 FB	247	#ifdef ALIGNED_ONLY
	248	if ((addr & (DATA_SIZE - 1)) != 0)
	249	do_unaligned_access(addr, 1, is_user, retaddr);
	250	#endif
61382a50	251	tlb_fill(addr, 1, is_user, retaddr);
b92e5a22 FB	252	goto redo;
	253	}
	254	}
	255
	256	/* handles all unaligned cases */
c27004ec	257	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50 FB	258	DATA_TYPE val,
	259	int is_user,
	260	void *retaddr)
b92e5a22	261	{
108c49b8	262	target_phys_addr_t physaddr;
c27004ec	263	target_ulong tlb_addr;
61382a50	264	int index, i;
b92e5a22	265
b92e5a22 FB	266	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	267	redo:
84b7b8e7	268	tlb_addr = env->tlb_table[is_user][index].addr_write;
b92e5a22	269	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
84b7b8e7	270	physaddr = addr + env->tlb_table[is_user][index].addend;
b92e5a22 FB	271	if (tlb_addr & ~TARGET_PAGE_MASK) {
	272	/* IO access */
	273	if ((addr & (DATA_SIZE - 1)) != 0)
	274	goto do_unaligned_access;
d720b93d	275	glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
98699967	276	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	277	do_unaligned_access:
	278	/* XXX: not efficient, but simple */
	279	for(i = 0;i < DATA_SIZE; i++) {
	280	#ifdef TARGET_WORDS_BIGENDIAN
61382a50 FB	281	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
61382a50 FB	282	is_user, retaddr);
b92e5a22	283	#else
61382a50 FB	284	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
61382a50 FB	285	is_user, retaddr);
b92e5a22 FB	286	#endif
	287	}
	288	} else {
	289	/* aligned/unaligned access in the same page */
108c49b8	290	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
b92e5a22 FB	291	}
	292	} else {
	293	/* the page is not in the TLB : fill it */
61382a50	294	tlb_fill(addr, 1, is_user, retaddr);
b92e5a22 FB	295	goto redo;
	296	}
	297	}
	298
b769d8fe FB	299	#endif /* !defined(SOFTMMU_CODE_ACCESS) */
	300
	301	#undef READ_ACCESS_TYPE
b92e5a22 FB	302	#undef SHIFT
	303	#undef DATA_TYPE
	304	#undef SUFFIX
61382a50	305	#undef USUFFIX
b92e5a22	306	#undef DATA_SIZE
84b7b8e7	307	#undef ADDR_READ