[qemu.git] / target-unicore32 / helper.c

/*
 * Copyright (C) 2010-2011 GUAN Xue-tao
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Contributions from 2012-04-01 on are considered under GPL version 2,
 * or (at your option) any later version.
 */

#include "cpu.h"
#include "gdbstub.h"
#include "helper.h"
#include "host-utils.h"

CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
{
    UniCore32CPU *cpu;
    CPUUniCore32State *env;
    static int inited = 1;

    if (object_class_by_name(cpu_model) == NULL) {
        return NULL;
    }
    cpu = UNICORE32_CPU(object_new(cpu_model));
    env = &cpu->env;

    if (inited) {
        inited = 0;
        uc32_translate_init();
    }

    qemu_init_vcpu(env);
    return env;
}

uint32_t HELPER(clo)(uint32_t x)
{
    return clo32(x);
}

uint32_t HELPER(clz)(uint32_t x)
{
    return clz32(x);
}

void do_interrupt(CPUUniCore32State *env)
{
    env->exception_index = -1;
}

int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
                              int mmu_idx)
{
    env->exception_index = UC32_EXCP_TRAP;
    env->cp0.c4_faultaddr = address;
    return 1;
}

/* These should probably raise undefined insn exceptions.  */
void HELPER(set_cp)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
{
    int op1 = (insn >> 8) & 0xf;
    cpu_abort(env, "cp%i insn %08x\n", op1, insn);
    return;
}

uint32_t HELPER(get_cp)(CPUUniCore32State *env, uint32_t insn)
{
    int op1 = (insn >> 8) & 0xf;
    cpu_abort(env, "cp%i insn %08x\n", op1, insn);
    return 0;
}

void HELPER(set_cp0)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
{
    cpu_abort(env, "cp0 insn %08x\n", insn);
}

uint32_t HELPER(get_cp0)(CPUUniCore32State *env, uint32_t insn)
{
    cpu_abort(env, "cp0 insn %08x\n", insn);
    return 0;
}

void switch_mode(CPUUniCore32State *env, int mode)
{
    if (mode != ASR_MODE_USER) {
        cpu_abort(env, "Tried to switch out of user mode\n");
    }
}

void HELPER(set_r29_banked)(CPUUniCore32State *env, uint32_t mode, uint32_t val)
{
    cpu_abort(env, "banked r29 write\n");
}

uint32_t HELPER(get_r29_banked)(CPUUniCore32State *env, uint32_t mode)
{
    cpu_abort(env, "banked r29 read\n");
    return 0;
}

/* UniCore-F64 support.  We follow the convention used for F64 instrunctions:
   Single precition routines have a "s" suffix, double precision a
   "d" suffix.  */

/* Convert host exception flags to f64 form.  */
static inline int ucf64_exceptbits_from_host(int host_bits)
{
    int target_bits = 0;

    if (host_bits & float_flag_invalid) {
        target_bits |= UCF64_FPSCR_FLAG_INVALID;
    }
    if (host_bits & float_flag_divbyzero) {
        target_bits |= UCF64_FPSCR_FLAG_DIVZERO;
    }
    if (host_bits & float_flag_overflow) {
        target_bits |= UCF64_FPSCR_FLAG_OVERFLOW;
    }
    if (host_bits & float_flag_underflow) {
        target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW;
    }
    if (host_bits & float_flag_inexact) {
        target_bits |= UCF64_FPSCR_FLAG_INEXACT;
    }
    return target_bits;
}

uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
{
    int i;
    uint32_t fpscr;

    fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
    i = get_float_exception_flags(&env->ucf64.fp_status);
    fpscr |= ucf64_exceptbits_from_host(i);
    return fpscr;
}

/* Convert ucf64 exception flags to target form.  */
static inline int ucf64_exceptbits_to_host(int target_bits)
{
    int host_bits = 0;

    if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
        host_bits |= float_flag_invalid;
    }
    if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
        host_bits |= float_flag_divbyzero;
    }
    if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
        host_bits |= float_flag_overflow;
    }
    if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
        host_bits |= float_flag_underflow;
    }
    if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
        host_bits |= float_flag_inexact;
    }
    return host_bits;
}

void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
{
    int i;
    uint32_t changed;

    changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
    env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);

    changed ^= val;
    if (changed & (UCF64_FPSCR_RND_MASK)) {
        i = UCF64_FPSCR_RND(val);
        switch (i) {
        case 0:
            i = float_round_nearest_even;
            break;
        case 1:
            i = float_round_to_zero;
            break;
        case 2:
            i = float_round_up;
            break;
        case 3:
            i = float_round_down;
            break;
        default: /* 100 and 101 not implement */
            cpu_abort(env, "Unsupported UniCore-F64 round mode");
        }
        set_float_rounding_mode(i, &env->ucf64.fp_status);
    }

    i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
    set_float_exception_flags(i, &env->ucf64.fp_status);
}

float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
{
    return float32_add(a, b, &env->ucf64.fp_status);
}

float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
{
    return float64_add(a, b, &env->ucf64.fp_status);
}

float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
{
    return float32_sub(a, b, &env->ucf64.fp_status);
}

float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
{
    return float64_sub(a, b, &env->ucf64.fp_status);
}

float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
{
    return float32_mul(a, b, &env->ucf64.fp_status);
}

float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
{
    return float64_mul(a, b, &env->ucf64.fp_status);
}

float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
{
    return float32_div(a, b, &env->ucf64.fp_status);
}

float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUniCore32State *env)
{
    return float64_div(a, b, &env->ucf64.fp_status);
}

float32 HELPER(ucf64_negs)(float32 a)
{
    return float32_chs(a);
}

float64 HELPER(ucf64_negd)(float64 a)
{
    return float64_chs(a);
}

float32 HELPER(ucf64_abss)(float32 a)
{
    return float32_abs(a);
}

float64 HELPER(ucf64_absd)(float64 a)
{
    return float64_abs(a);
}

/* XXX: check quiet/signaling case */
void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUUniCore32State *env)
{
    int flag;
    flag = float32_compare_quiet(a, b, &env->ucf64.fp_status);
    env->CF = 0;
    switch (c & 0x7) {
    case 0: /* F */
        break;
    case 1: /* UN */
        if (flag == 2) {
            env->CF = 1;
        }
        break;
    case 2: /* EQ */
        if (flag == 0) {
            env->CF = 1;
        }
        break;
    case 3: /* UEQ */
        if ((flag == 0) || (flag == 2)) {
            env->CF = 1;
        }
        break;
    case 4: /* OLT */
        if (flag == -1) {
            env->CF = 1;
        }
        break;
    case 5: /* ULT */
        if ((flag == -1) || (flag == 2)) {
            env->CF = 1;
        }
        break;
    case 6: /* OLE */
        if ((flag == -1) || (flag == 0)) {
            env->CF = 1;
        }
        break;
    case 7: /* ULE */
        if (flag != 1) {
            env->CF = 1;
        }
        break;
    }
    env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
                    | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
}

void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c, CPUUniCore32State *env)
{
    int flag;
    flag = float64_compare_quiet(a, b, &env->ucf64.fp_status);
    env->CF = 0;
    switch (c & 0x7) {
    case 0: /* F */
        break;
    case 1: /* UN */
        if (flag == 2) {
            env->CF = 1;
        }
        break;
    case 2: /* EQ */
        if (flag == 0) {
            env->CF = 1;
        }
        break;
    case 3: /* UEQ */
        if ((flag == 0) || (flag == 2)) {
            env->CF = 1;
        }
        break;
    case 4: /* OLT */
        if (flag == -1) {
            env->CF = 1;
        }
        break;
    case 5: /* ULT */
        if ((flag == -1) || (flag == 2)) {
            env->CF = 1;
        }
        break;
    case 6: /* OLE */
        if ((flag == -1) || (flag == 0)) {
            env->CF = 1;
        }
        break;
    case 7: /* ULE */
        if (flag != 1) {
            env->CF = 1;
        }
        break;
    }
    env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
                    | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
}

/* Helper routines to perform bitwise copies between float and int.  */
static inline float32 ucf64_itos(uint32_t i)
{
    union {
        uint32_t i;
        float32 s;
    } v;

    v.i = i;
    return v.s;
}

static inline uint32_t ucf64_stoi(float32 s)
{
    union {
        uint32_t i;
        float32 s;
    } v;

    v.s = s;
    return v.i;
}

static inline float64 ucf64_itod(uint64_t i)
{
    union {
        uint64_t i;
        float64 d;
    } v;

    v.i = i;
    return v.d;
}

static inline uint64_t ucf64_dtoi(float64 d)
{
    union {
        uint64_t i;
        float64 d;
    } v;

    v.d = d;
    return v.i;
}

/* Integer to float conversion.  */
float32 HELPER(ucf64_si2sf)(float32 x, CPUUniCore32State *env)
{
    return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status);
}

float64 HELPER(ucf64_si2df)(float32 x, CPUUniCore32State *env)
{
    return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status);
}

/* Float to integer conversion.  */
float32 HELPER(ucf64_sf2si)(float32 x, CPUUniCore32State *env)
{
    return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status));
}

float32 HELPER(ucf64_df2si)(float64 x, CPUUniCore32State *env)
{
    return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));
}

/* floating point conversion */
float64 HELPER(ucf64_sf2df)(float32 x, CPUUniCore32State *env)
{
    return float32_to_float64(x, &env->ucf64.fp_status);
}

float32 HELPER(ucf64_df2sf)(float64 x, CPUUniCore32State *env)
{
    return float64_to_float32(x, &env->ucf64.fp_status);
}
Commit	Line	Data
6e64da3c GX	1	/*
	2	* Copyright (C) 2010-2011 GUAN Xue-tao
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
c3a8baa9 AF	7	*
	8	* Contributions from 2012-04-01 on are considered under GPL version 2,
	9	* or (at your option) any later version.
6e64da3c	10	*/
6e64da3c GX	11
6e64da3c GX	12	#include "cpu.h"
6e64da3c GX	13	#include "gdbstub.h"
6e64da3c GX	14	#include "helper.h"
6e64da3c GX	15	#include "host-utils.h"
6e64da3c GX	16
eb23b556	17	CPUUniCore32State uc32_cpu_init(const char cpu_model)
6e64da3c	18	{
ae0f5e9e	19	UniCore32CPU *cpu;
eb23b556	20	CPUUniCore32State *env;
6e64da3c GX	21	static int inited = 1;
6e64da3c GX	22
ae0f5e9e AF	23	if (object_class_by_name(cpu_model) == NULL) {
	24	return NULL;
	25	}
	26	cpu = UNICORE32_CPU(object_new(cpu_model));
	27	env = &cpu->env;
6e64da3c	28
6e64da3c GX	29	if (inited) {
	30	inited = 0;
	31	uc32_translate_init();
	32	}
	33
6e64da3c GX	34	qemu_init_vcpu(env);
	35	return env;
	36	}
	37
	38	uint32_t HELPER(clo)(uint32_t x)
	39	{
	40	return clo32(x);
	41	}
	42
	43	uint32_t HELPER(clz)(uint32_t x)
	44	{
	45	return clz32(x);
	46	}
	47
eb23b556	48	void do_interrupt(CPUUniCore32State *env)
6e64da3c GX	49	{
	50	env->exception_index = -1;
	51	}
	52
eb23b556	53	int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
97b348e7	54	int mmu_idx)
6e64da3c GX	55	{
	56	env->exception_index = UC32_EXCP_TRAP;
	57	env->cp0.c4_faultaddr = address;
	58	return 1;
	59	}
	60
	61	/* These should probably raise undefined insn exceptions. */
eb23b556	62	void HELPER(set_cp)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
6e64da3c GX	63	{
	64	int op1 = (insn >> 8) & 0xf;
	65	cpu_abort(env, "cp%i insn %08x\n", op1, insn);
	66	return;
	67	}
	68
eb23b556	69	uint32_t HELPER(get_cp)(CPUUniCore32State *env, uint32_t insn)
6e64da3c GX	70	{
	71	int op1 = (insn >> 8) & 0xf;
	72	cpu_abort(env, "cp%i insn %08x\n", op1, insn);
	73	return 0;
	74	}
	75
eb23b556	76	void HELPER(set_cp0)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
6e64da3c GX	77	{
	78	cpu_abort(env, "cp0 insn %08x\n", insn);
	79	}
	80
eb23b556	81	uint32_t HELPER(get_cp0)(CPUUniCore32State *env, uint32_t insn)
6e64da3c GX	82	{
	83	cpu_abort(env, "cp0 insn %08x\n", insn);
	84	return 0;
	85	}
	86
eb23b556	87	void switch_mode(CPUUniCore32State *env, int mode)
6e64da3c GX	88	{
	89	if (mode != ASR_MODE_USER) {
	90	cpu_abort(env, "Tried to switch out of user mode\n");
	91	}
	92	}
	93
eb23b556	94	void HELPER(set_r29_banked)(CPUUniCore32State *env, uint32_t mode, uint32_t val)
6e64da3c GX	95	{
	96	cpu_abort(env, "banked r29 write\n");
	97	}
	98
eb23b556	99	uint32_t HELPER(get_r29_banked)(CPUUniCore32State *env, uint32_t mode)
6e64da3c GX	100	{
	101	cpu_abort(env, "banked r29 read\n");
	102	return 0;
	103	}
	104
	105	/* UniCore-F64 support. We follow the convention used for F64 instrunctions:
	106	Single precition routines have a "s" suffix, double precision a
	107	"d" suffix. */
	108
	109	/* Convert host exception flags to f64 form. */
	110	static inline int ucf64_exceptbits_from_host(int host_bits)
	111	{
	112	int target_bits = 0;
	113
	114	if (host_bits & float_flag_invalid) {
	115	target_bits \|= UCF64_FPSCR_FLAG_INVALID;
	116	}
	117	if (host_bits & float_flag_divbyzero) {
	118	target_bits \|= UCF64_FPSCR_FLAG_DIVZERO;
	119	}
	120	if (host_bits & float_flag_overflow) {
	121	target_bits \|= UCF64_FPSCR_FLAG_OVERFLOW;
	122	}
	123	if (host_bits & float_flag_underflow) {
	124	target_bits \|= UCF64_FPSCR_FLAG_UNDERFLOW;
	125	}
	126	if (host_bits & float_flag_inexact) {
	127	target_bits \|= UCF64_FPSCR_FLAG_INEXACT;
	128	}
	129	return target_bits;
	130	}
	131
eb23b556	132	uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
6e64da3c GX	133	{
	134	int i;
	135	uint32_t fpscr;
	136
	137	fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
	138	i = get_float_exception_flags(&env->ucf64.fp_status);
	139	fpscr \|= ucf64_exceptbits_from_host(i);
	140	return fpscr;
	141	}
	142
	143	/* Convert ucf64 exception flags to target form. */
	144	static inline int ucf64_exceptbits_to_host(int target_bits)
	145	{
	146	int host_bits = 0;
	147
	148	if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
	149	host_bits \|= float_flag_invalid;
	150	}
	151	if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
	152	host_bits \|= float_flag_divbyzero;
	153	}
	154	if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
	155	host_bits \|= float_flag_overflow;
	156	}
	157	if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
	158	host_bits \|= float_flag_underflow;
	159	}
	160	if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
	161	host_bits \|= float_flag_inexact;
	162	}
	163	return host_bits;
	164	}
	165
eb23b556	166	void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
6e64da3c GX	167	{
	168	int i;
	169	uint32_t changed;
	170
	171	changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
	172	env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);
	173
	174	changed ^= val;
	175	if (changed & (UCF64_FPSCR_RND_MASK)) {
	176	i = UCF64_FPSCR_RND(val);
	177	switch (i) {
	178	case 0:
	179	i = float_round_nearest_even;
	180	break;
	181	case 1:
	182	i = float_round_to_zero;
	183	break;
	184	case 2:
	185	i = float_round_up;
	186	break;
	187	case 3:
	188	i = float_round_down;
	189	break;
	190	default: /* 100 and 101 not implement */
	191	cpu_abort(env, "Unsupported UniCore-F64 round mode");
	192	}
	193	set_float_rounding_mode(i, &env->ucf64.fp_status);
	194	}
	195
	196	i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
	197	set_float_exception_flags(i, &env->ucf64.fp_status);
	198	}
	199
eb23b556	200	float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
6e64da3c GX	201	{
	202	return float32_add(a, b, &env->ucf64.fp_status);
	203	}
	204
eb23b556	205	float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
6e64da3c GX	206	{
	207	return float64_add(a, b, &env->ucf64.fp_status);
	208	}
	209
eb23b556	210	float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
6e64da3c GX	211	{
	212	return float32_sub(a, b, &env->ucf64.fp_status);
	213	}
	214
eb23b556	215	float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
6e64da3c GX	216	{
	217	return float64_sub(a, b, &env->ucf64.fp_status);
	218	}
	219
eb23b556	220	float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
6e64da3c GX	221	{
	222	return float32_mul(a, b, &env->ucf64.fp_status);
	223	}
	224
eb23b556	225	float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
6e64da3c GX	226	{
	227	return float64_mul(a, b, &env->ucf64.fp_status);
	228	}
	229
eb23b556	230	float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
6e64da3c GX	231	{
	232	return float32_div(a, b, &env->ucf64.fp_status);
	233	}
	234
eb23b556	235	float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUniCore32State *env)
6e64da3c GX	236	{
	237	return float64_div(a, b, &env->ucf64.fp_status);
	238	}
	239
	240	float32 HELPER(ucf64_negs)(float32 a)
	241	{
	242	return float32_chs(a);
	243	}
	244
	245	float64 HELPER(ucf64_negd)(float64 a)
	246	{
	247	return float64_chs(a);
	248	}
	249
	250	float32 HELPER(ucf64_abss)(float32 a)
	251	{
	252	return float32_abs(a);
	253	}
	254
	255	float64 HELPER(ucf64_absd)(float64 a)
	256	{
	257	return float64_abs(a);
	258	}
	259
	260	/* XXX: check quiet/signaling case */
eb23b556	261	void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUUniCore32State *env)
6e64da3c GX	262	{
	263	int flag;
	264	flag = float32_compare_quiet(a, b, &env->ucf64.fp_status);
	265	env->CF = 0;
	266	switch (c & 0x7) {
	267	case 0: /* F */
	268	break;
	269	case 1: /* UN */
	270	if (flag == 2) {
	271	env->CF = 1;
	272	}
	273	break;
	274	case 2: /* EQ */
	275	if (flag == 0) {
	276	env->CF = 1;
	277	}
	278	break;
	279	case 3: /* UEQ */
	280	if ((flag == 0) \|\| (flag == 2)) {
	281	env->CF = 1;
	282	}
	283	break;
	284	case 4: /* OLT */
	285	if (flag == -1) {
	286	env->CF = 1;
	287	}
	288	break;
	289	case 5: /* ULT */
	290	if ((flag == -1) \|\| (flag == 2)) {
	291	env->CF = 1;
	292	}
	293	break;
	294	case 6: /* OLE */
	295	if ((flag == -1) \|\| (flag == 0)) {
	296	env->CF = 1;
	297	}
	298	break;
	299	case 7: /* ULE */
	300	if (flag != 1) {
	301	env->CF = 1;
	302	}
	303	break;
	304	}
	305	env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
	306	\| (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
	307	}
	308
eb23b556	309	void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c, CPUUniCore32State *env)
6e64da3c GX	310	{
	311	int flag;
	312	flag = float64_compare_quiet(a, b, &env->ucf64.fp_status);
	313	env->CF = 0;
	314	switch (c & 0x7) {
	315	case 0: /* F */
	316	break;
	317	case 1: /* UN */
	318	if (flag == 2) {
	319	env->CF = 1;
	320	}
	321	break;
	322	case 2: /* EQ */
	323	if (flag == 0) {
	324	env->CF = 1;
	325	}
	326	break;
	327	case 3: /* UEQ */
	328	if ((flag == 0) \|\| (flag == 2)) {
	329	env->CF = 1;
	330	}
	331	break;
	332	case 4: /* OLT */
	333	if (flag == -1) {
	334	env->CF = 1;
	335	}
	336	break;
	337	case 5: /* ULT */
	338	if ((flag == -1) \|\| (flag == 2)) {
	339	env->CF = 1;
	340	}
	341	break;
	342	case 6: /* OLE */
	343	if ((flag == -1) \|\| (flag == 0)) {
	344	env->CF = 1;
	345	}
	346	break;
	347	case 7: /* ULE */
	348	if (flag != 1) {
	349	env->CF = 1;
	350	}
	351	break;
	352	}
	353	env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
	354	\| (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
	355	}
	356
	357	/* Helper routines to perform bitwise copies between float and int. */
	358	static inline float32 ucf64_itos(uint32_t i)
	359	{
	360	union {
	361	uint32_t i;
	362	float32 s;
	363	} v;
	364
	365	v.i = i;
	366	return v.s;
	367	}
	368
	369	static inline uint32_t ucf64_stoi(float32 s)
	370	{
	371	union {
	372	uint32_t i;
	373	float32 s;
374	} v;
375
376	v.s = s;
377	return v.i;
378	}
379
380	static inline float64 ucf64_itod(uint64_t i)
381	{
382	union {
383	uint64_t i;
384	float64 d;
385	} v;
386
387	v.i = i;
388	return v.d;
389	}
390
391	static inline uint64_t ucf64_dtoi(float64 d)
392	{
393	union {
394	uint64_t i;
395	float64 d;
396	} v;
397
398	v.d = d;
399	return v.i;
400	}
401
402	/* Integer to float conversion. */
eb23b556	403	float32 HELPER(ucf64_si2sf)(float32 x, CPUUniCore32State *env)
6e64da3c GX	404	{
	405	return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status);
	406	}
	407
eb23b556	408	float64 HELPER(ucf64_si2df)(float32 x, CPUUniCore32State *env)
6e64da3c GX	409	{
	410	return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status);
	411	}
	412
	413	/* Float to integer conversion. */
eb23b556	414	float32 HELPER(ucf64_sf2si)(float32 x, CPUUniCore32State *env)
6e64da3c GX	415	{
	416	return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status));
	417	}
	418
eb23b556	419	float32 HELPER(ucf64_df2si)(float64 x, CPUUniCore32State *env)
6e64da3c GX	420	{
	421	return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));
	422	}
	423
	424	/* floating point conversion */
eb23b556	425	float64 HELPER(ucf64_sf2df)(float32 x, CPUUniCore32State *env)
6e64da3c GX	426	{
	427	return float32_to_float64(x, &env->ucf64.fp_status);
	428	}
	429
eb23b556	430	float32 HELPER(ucf64_df2sf)(float64 x, CPUUniCore32State *env)
6e64da3c GX	431	{
	432	return float64_to_float32(x, &env->ucf64.fp_status);
	433	}