]>
Commit | Line | Data |
---|---|---|
823e675a JQ |
1 | /* |
2 | * QEMU PIIX4 PCI Bridge Emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
b6a0aa05 | 25 | #include "qemu/osdep.h" |
83c9f4ca | 26 | #include "hw/hw.h" |
0d09e41a | 27 | #include "hw/i386/pc.h" |
83c9f4ca | 28 | #include "hw/pci/pci.h" |
0d09e41a | 29 | #include "hw/isa/isa.h" |
83c9f4ca | 30 | #include "hw/sysbus.h" |
823e675a JQ |
31 | |
32 | PCIDevice *piix4_dev; | |
33 | ||
1fc7cee0 JQ |
34 | typedef struct PIIX4State { |
35 | PCIDevice dev; | |
36 | } PIIX4State; | |
37 | ||
acff3e48 GA |
38 | #define TYPE_PIIX4_PCI_DEVICE "PIIX4" |
39 | #define PIIX4_PCI_DEVICE(obj) \ | |
40 | OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE) | |
41 | ||
823e675a JQ |
42 | static void piix4_reset(void *opaque) |
43 | { | |
1fc7cee0 JQ |
44 | PIIX4State *d = opaque; |
45 | uint8_t *pci_conf = d->dev.config; | |
823e675a JQ |
46 | |
47 | pci_conf[0x04] = 0x07; // master, memory and I/O | |
48 | pci_conf[0x05] = 0x00; | |
49 | pci_conf[0x06] = 0x00; | |
50 | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium | |
51 | pci_conf[0x4c] = 0x4d; | |
52 | pci_conf[0x4e] = 0x03; | |
53 | pci_conf[0x4f] = 0x00; | |
54 | pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 | |
55 | pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 | |
56 | pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 | |
57 | pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 | |
58 | pci_conf[0x69] = 0x02; | |
59 | pci_conf[0x70] = 0x80; | |
60 | pci_conf[0x76] = 0x0c; | |
61 | pci_conf[0x77] = 0x0c; | |
62 | pci_conf[0x78] = 0x02; | |
63 | pci_conf[0x79] = 0x00; | |
64 | pci_conf[0x80] = 0x00; | |
65 | pci_conf[0x82] = 0x00; | |
66 | pci_conf[0xa0] = 0x08; | |
67 | pci_conf[0xa2] = 0x00; | |
68 | pci_conf[0xa3] = 0x00; | |
69 | pci_conf[0xa4] = 0x00; | |
70 | pci_conf[0xa5] = 0x00; | |
71 | pci_conf[0xa6] = 0x00; | |
72 | pci_conf[0xa7] = 0x00; | |
73 | pci_conf[0xa8] = 0x0f; | |
74 | pci_conf[0xaa] = 0x00; | |
75 | pci_conf[0xab] = 0x00; | |
76 | pci_conf[0xac] = 0x00; | |
77 | pci_conf[0xae] = 0x00; | |
78 | } | |
79 | ||
9039d78e JQ |
80 | static const VMStateDescription vmstate_piix4 = { |
81 | .name = "PIIX4", | |
82 | .version_id = 2, | |
83 | .minimum_version_id = 2, | |
d49805ae | 84 | .fields = (VMStateField[]) { |
9039d78e JQ |
85 | VMSTATE_PCI_DEVICE(dev, PIIX4State), |
86 | VMSTATE_END_OF_LIST() | |
87 | } | |
88 | }; | |
823e675a | 89 | |
9af21dbe | 90 | static void piix4_realize(PCIDevice *dev, Error **errp) |
823e675a | 91 | { |
acff3e48 | 92 | PIIX4State *d = PIIX4_PCI_DEVICE(dev); |
823e675a | 93 | |
d10e5432 MA |
94 | if (!isa_bus_new(DEVICE(d), pci_address_space(dev), |
95 | pci_address_space_io(dev), errp)) { | |
96 | return; | |
97 | } | |
1fc7cee0 | 98 | piix4_dev = &d->dev; |
823e675a | 99 | qemu_register_reset(piix4_reset, d); |
823e675a JQ |
100 | } |
101 | ||
142e9787 | 102 | int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn) |
823e675a JQ |
103 | { |
104 | PCIDevice *d; | |
105 | ||
fecb93c4 | 106 | d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4"); |
2ae0e48d | 107 | *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0")); |
823e675a JQ |
108 | return d->devfn; |
109 | } | |
110 | ||
40021f08 AL |
111 | static void piix4_class_init(ObjectClass *klass, void *data) |
112 | { | |
39bffca2 | 113 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
114 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
115 | ||
9af21dbe | 116 | k->realize = piix4_realize; |
40021f08 AL |
117 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
118 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; | |
119 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
39bffca2 | 120 | dc->desc = "ISA bridge"; |
39bffca2 | 121 | dc->vmsd = &vmstate_piix4; |
81aab2ff MA |
122 | /* |
123 | * Reason: part of PIIX4 southbridge, needs to be wired up, | |
124 | * e.g. by mips_malta_init() | |
125 | */ | |
e90f2a8c | 126 | dc->user_creatable = false; |
2897ae02 | 127 | dc->hotpluggable = false; |
40021f08 AL |
128 | } |
129 | ||
8c43a6f0 | 130 | static const TypeInfo piix4_info = { |
acff3e48 | 131 | .name = TYPE_PIIX4_PCI_DEVICE, |
39bffca2 AL |
132 | .parent = TYPE_PCI_DEVICE, |
133 | .instance_size = sizeof(PIIX4State), | |
134 | .class_init = piix4_class_init, | |
fd3b02c8 EH |
135 | .interfaces = (InterfaceInfo[]) { |
136 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
137 | { }, | |
138 | }, | |
823e675a JQ |
139 | }; |
140 | ||
83f7d43a | 141 | static void piix4_register_types(void) |
823e675a | 142 | { |
39bffca2 | 143 | type_register_static(&piix4_info); |
823e675a | 144 | } |
83f7d43a AF |
145 | |
146 | type_init(piix4_register_types) |