[qemu.git] / hw / dma / pxa2xx_dma.c

/*
 * Intel XScale PXA255/270 DMA controller.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2006 Thorsten Zitterell
 * Written by Andrzej Zaborowski <[email protected]>
 *
 * This code is licensed under the GPL.
 */

#include "hw/hw.h"
#include "hw/arm/pxa.h"
#include "hw/sysbus.h"

#define PXA255_DMA_NUM_CHANNELS 16
#define PXA27X_DMA_NUM_CHANNELS 32

#define PXA2XX_DMA_NUM_REQUESTS 75

typedef struct {
    uint32_t descr;
    uint32_t src;
    uint32_t dest;
    uint32_t cmd;
    uint32_t state;
    int request;
} PXA2xxDMAChannel;

#define TYPE_PXA2XX_DMA "pxa2xx-dma"
#define PXA2XX_DMA(obj) OBJECT_CHECK(PXA2xxDMAState, (obj), TYPE_PXA2XX_DMA)

typedef struct PXA2xxDMAState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    qemu_irq irq;

    uint32_t stopintr;
    uint32_t eorintr;
    uint32_t rasintr;
    uint32_t startintr;
    uint32_t endintr;

    uint32_t align;
    uint32_t pio;

    int channels;
    PXA2xxDMAChannel *chan;

    uint8_t req[PXA2XX_DMA_NUM_REQUESTS];

    /* Flag to avoid recursive DMA invocations.  */
    int running;
} PXA2xxDMAState;

#define DCSR0	0x0000	/* DMA Control / Status register for Channel 0 */
#define DCSR31	0x007c	/* DMA Control / Status register for Channel 31 */
#define DALGN	0x00a0	/* DMA Alignment register */
#define DPCSR	0x00a4	/* DMA Programmed I/O Control Status register */
#define DRQSR0	0x00e0	/* DMA DREQ<0> Status register */
#define DRQSR1	0x00e4	/* DMA DREQ<1> Status register */
#define DRQSR2	0x00e8	/* DMA DREQ<2> Status register */
#define DINT	0x00f0	/* DMA Interrupt register */
#define DRCMR0	0x0100	/* Request to Channel Map register 0 */
#define DRCMR63	0x01fc	/* Request to Channel Map register 63 */
#define D_CH0	0x0200	/* Channel 0 Descriptor start */
#define DRCMR64	0x1100	/* Request to Channel Map register 64 */
#define DRCMR74	0x1128	/* Request to Channel Map register 74 */

/* Per-channel register */
#define DDADR	0x00
#define DSADR	0x01
#define DTADR	0x02
#define DCMD	0x03

/* Bit-field masks */
#define DRCMR_CHLNUM		0x1f
#define DRCMR_MAPVLD		(1 << 7)
#define DDADR_STOP		(1 << 0)
#define DDADR_BREN		(1 << 1)
#define DCMD_LEN		0x1fff
#define DCMD_WIDTH(x)		(1 << ((((x) >> 14) & 3) - 1))
#define DCMD_SIZE(x)		(4 << (((x) >> 16) & 3))
#define DCMD_FLYBYT		(1 << 19)
#define DCMD_FLYBYS		(1 << 20)
#define DCMD_ENDIRQEN		(1 << 21)
#define DCMD_STARTIRQEN		(1 << 22)
#define DCMD_CMPEN		(1 << 25)
#define DCMD_FLOWTRG		(1 << 28)
#define DCMD_FLOWSRC		(1 << 29)
#define DCMD_INCTRGADDR		(1 << 30)
#define DCMD_INCSRCADDR		(1 << 31)
#define DCSR_BUSERRINTR		(1 << 0)
#define DCSR_STARTINTR		(1 << 1)
#define DCSR_ENDINTR		(1 << 2)
#define DCSR_STOPINTR		(1 << 3)
#define DCSR_RASINTR		(1 << 4)
#define DCSR_REQPEND		(1 << 8)
#define DCSR_EORINT		(1 << 9)
#define DCSR_CMPST		(1 << 10)
#define DCSR_MASKRUN		(1 << 22)
#define DCSR_RASIRQEN		(1 << 23)
#define DCSR_CLRCMPST		(1 << 24)
#define DCSR_SETCMPST		(1 << 25)
#define DCSR_EORSTOPEN		(1 << 26)
#define DCSR_EORJMPEN		(1 << 27)
#define DCSR_EORIRQEN		(1 << 28)
#define DCSR_STOPIRQEN		(1 << 29)
#define DCSR_NODESCFETCH	(1 << 30)
#define DCSR_RUN		(1 << 31)

static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch)
{
    if (ch >= 0) {
        if ((s->chan[ch].state & DCSR_STOPIRQEN) &&
                (s->chan[ch].state & DCSR_STOPINTR))
            s->stopintr |= 1 << ch;
        else
            s->stopintr &= ~(1 << ch);

        if ((s->chan[ch].state & DCSR_EORIRQEN) &&
                (s->chan[ch].state & DCSR_EORINT))
            s->eorintr |= 1 << ch;
        else
            s->eorintr &= ~(1 << ch);

        if ((s->chan[ch].state & DCSR_RASIRQEN) &&
                (s->chan[ch].state & DCSR_RASINTR))
            s->rasintr |= 1 << ch;
        else
            s->rasintr &= ~(1 << ch);

        if (s->chan[ch].state & DCSR_STARTINTR)
            s->startintr |= 1 << ch;
        else
            s->startintr &= ~(1 << ch);

        if (s->chan[ch].state & DCSR_ENDINTR)
            s->endintr |= 1 << ch;
        else
            s->endintr &= ~(1 << ch);
    }

    if (s->stopintr | s->eorintr | s->rasintr | s->startintr | s->endintr)
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static inline void pxa2xx_dma_descriptor_fetch(
                PXA2xxDMAState *s, int ch)
{
    uint32_t desc[4];
    hwaddr daddr = s->chan[ch].descr & ~0xf;
    if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
        daddr += 32;

    cpu_physical_memory_read(daddr, desc, 16);
    s->chan[ch].descr = desc[DDADR];
    s->chan[ch].src = desc[DSADR];
    s->chan[ch].dest = desc[DTADR];
    s->chan[ch].cmd = desc[DCMD];

    if (s->chan[ch].cmd & DCMD_FLOWSRC)
        s->chan[ch].src &= ~3;
    if (s->chan[ch].cmd & DCMD_FLOWTRG)
        s->chan[ch].dest &= ~3;

    if (s->chan[ch].cmd & (DCMD_CMPEN | DCMD_FLYBYS | DCMD_FLYBYT))
        printf("%s: unsupported mode in channel %i\n", __FUNCTION__, ch);

    if (s->chan[ch].cmd & DCMD_STARTIRQEN)
        s->chan[ch].state |= DCSR_STARTINTR;
}

static void pxa2xx_dma_run(PXA2xxDMAState *s)
{
    int c, srcinc, destinc;
    uint32_t n, size;
    uint32_t width;
    uint32_t length;
    uint8_t buffer[32];
    PXA2xxDMAChannel *ch;

    if (s->running ++)
        return;

    while (s->running) {
        s->running = 1;
        for (c = 0; c < s->channels; c ++) {
            ch = &s->chan[c];

            while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) {
                /* Test for pending requests */
                if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request)
                    break;

                length = ch->cmd & DCMD_LEN;
                size = DCMD_SIZE(ch->cmd);
                width = DCMD_WIDTH(ch->cmd);

                srcinc = (ch->cmd & DCMD_INCSRCADDR) ? width : 0;
                destinc = (ch->cmd & DCMD_INCTRGADDR) ? width : 0;

                while (length) {
                    size = MIN(length, size);

                    for (n = 0; n < size; n += width) {
                        cpu_physical_memory_read(ch->src, buffer + n, width);
                        ch->src += srcinc;
                    }

                    for (n = 0; n < size; n += width) {
                        cpu_physical_memory_write(ch->dest, buffer + n, width);
                        ch->dest += destinc;
                    }

                    length -= size;

                    if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) &&
                            !ch->request) {
                        ch->state |= DCSR_EORINT;
                        if (ch->state & DCSR_EORSTOPEN)
                            ch->state |= DCSR_STOPINTR;
                        if ((ch->state & DCSR_EORJMPEN) &&
                                        !(ch->state & DCSR_NODESCFETCH))
                            pxa2xx_dma_descriptor_fetch(s, c);
                        break;
		    }
                }

                ch->cmd = (ch->cmd & ~DCMD_LEN) | length;

                /* Is the transfer complete now? */
                if (!length) {
                    if (ch->cmd & DCMD_ENDIRQEN)
                        ch->state |= DCSR_ENDINTR;

                    if ((ch->state & DCSR_NODESCFETCH) ||
                                (ch->descr & DDADR_STOP) ||
                                (ch->state & DCSR_EORSTOPEN)) {
                        ch->state |= DCSR_STOPINTR;
                        ch->state &= ~DCSR_RUN;

                        break;
                    }

                    ch->state |= DCSR_STOPINTR;
                    break;
                }
            }
        }

        s->running --;
    }
}

static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
                                unsigned size)
{
    PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
    unsigned int channel;

    if (size != 4) {
        hw_error("%s: Bad access width\n", __FUNCTION__);
        return 5;
    }

    switch (offset) {
    case DRCMR64 ... DRCMR74:
        offset -= DRCMR64 - DRCMR0 - (64 << 2);
        /* Fall through */
    case DRCMR0 ... DRCMR63:
        channel = (offset - DRCMR0) >> 2;
        return s->req[channel];

    case DRQSR0:
    case DRQSR1:
    case DRQSR2:
        return 0;

    case DCSR0 ... DCSR31:
        channel = offset >> 2;
	if (s->chan[channel].request)
            return s->chan[channel].state | DCSR_REQPEND;
        return s->chan[channel].state;

    case DINT:
        return s->stopintr | s->eorintr | s->rasintr |
                s->startintr | s->endintr;

    case DALGN:
        return s->align;

    case DPCSR:
        return s->pio;
    }

    if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
        channel = (offset - D_CH0) >> 4;
        switch ((offset & 0x0f) >> 2) {
        case DDADR:
            return s->chan[channel].descr;
        case DSADR:
            return s->chan[channel].src;
        case DTADR:
            return s->chan[channel].dest;
        case DCMD:
            return s->chan[channel].cmd;
        }
    }

    hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset);
    return 7;
}

static void pxa2xx_dma_write(void *opaque, hwaddr offset,
                             uint64_t value, unsigned size)
{
    PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
    unsigned int channel;

    if (size != 4) {
        hw_error("%s: Bad access width\n", __FUNCTION__);
        return;
    }

    switch (offset) {
    case DRCMR64 ... DRCMR74:
        offset -= DRCMR64 - DRCMR0 - (64 << 2);
        /* Fall through */
    case DRCMR0 ... DRCMR63:
        channel = (offset - DRCMR0) >> 2;

        if (value & DRCMR_MAPVLD)
            if ((value & DRCMR_CHLNUM) > s->channels)
                hw_error("%s: Bad DMA channel %i\n",
                         __FUNCTION__, (unsigned)value & DRCMR_CHLNUM);

        s->req[channel] = value;
        break;

    case DRQSR0:
    case DRQSR1:
    case DRQSR2:
        /* Nothing to do */
        break;

    case DCSR0 ... DCSR31:
        channel = offset >> 2;
        s->chan[channel].state &= 0x0000071f & ~(value &
                        (DCSR_EORINT | DCSR_ENDINTR |
                         DCSR_STARTINTR | DCSR_BUSERRINTR));
        s->chan[channel].state |= value & 0xfc800000;

        if (s->chan[channel].state & DCSR_STOPIRQEN)
            s->chan[channel].state &= ~DCSR_STOPINTR;

        if (value & DCSR_NODESCFETCH) {
            /* No-descriptor-fetch mode */
            if (value & DCSR_RUN) {
                s->chan[channel].state &= ~DCSR_STOPINTR;
                pxa2xx_dma_run(s);
            }
        } else {
            /* Descriptor-fetch mode */
            if (value & DCSR_RUN) {
                s->chan[channel].state &= ~DCSR_STOPINTR;
                pxa2xx_dma_descriptor_fetch(s, channel);
                pxa2xx_dma_run(s);
            }
        }

        /* Shouldn't matter as our DMA is synchronous.  */
        if (!(value & (DCSR_RUN | DCSR_MASKRUN)))
            s->chan[channel].state |= DCSR_STOPINTR;

        if (value & DCSR_CLRCMPST)
            s->chan[channel].state &= ~DCSR_CMPST;
        if (value & DCSR_SETCMPST)
            s->chan[channel].state |= DCSR_CMPST;

        pxa2xx_dma_update(s, channel);
        break;

    case DALGN:
        s->align = value;
        break;

    case DPCSR:
        s->pio = value & 0x80000001;
        break;

    default:
        if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
            channel = (offset - D_CH0) >> 4;
            switch ((offset & 0x0f) >> 2) {
            case DDADR:
                s->chan[channel].descr = value;
                break;
            case DSADR:
                s->chan[channel].src = value;
                break;
            case DTADR:
                s->chan[channel].dest = value;
                break;
            case DCMD:
                s->chan[channel].cmd = value;
                break;
            default:
                goto fail;
            }

            break;
        }
    fail:
        hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __FUNCTION__, offset);
    }
}

static const MemoryRegionOps pxa2xx_dma_ops = {
    .read = pxa2xx_dma_read,
    .write = pxa2xx_dma_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pxa2xx_dma_request(void *opaque, int req_num, int on)
{
    PXA2xxDMAState *s = opaque;
    int ch;
    if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS)
        hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num);

    if (!(s->req[req_num] & DRCMR_MAPVLD))
        return;
    ch = s->req[req_num] & DRCMR_CHLNUM;

    if (!s->chan[ch].request && on)
        s->chan[ch].state |= DCSR_RASINTR;
    else
        s->chan[ch].state &= ~DCSR_RASINTR;
    if (s->chan[ch].request && !on)
        s->chan[ch].state |= DCSR_EORINT;

    s->chan[ch].request = on;
    if (on) {
        pxa2xx_dma_run(s);
        pxa2xx_dma_update(s, ch);
    }
}

static int pxa2xx_dma_init(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    PXA2xxDMAState *s = PXA2XX_DMA(dev);
    int i;

    if (s->channels <= 0) {
        return -1;
    }

    s->chan = g_malloc0(sizeof(PXA2xxDMAChannel) * s->channels);

    memset(s->chan, 0, sizeof(PXA2xxDMAChannel) * s->channels);
    for (i = 0; i < s->channels; i ++)
        s->chan[i].state = DCSR_STOPINTR;

    memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);

    qdev_init_gpio_in(dev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);

    memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_dma_ops, s,
                          "pxa2xx.dma", 0x00010000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);

    return 0;
}

DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "pxa2xx-dma");
    qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
    qdev_init_nofail(dev);

    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);

    return dev;
}

DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "pxa2xx-dma");
    qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
    qdev_init_nofail(dev);

    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);

    return dev;
}

static bool is_version_0(void *opaque, int version_id)
{
    return version_id == 0;
}

static VMStateDescription vmstate_pxa2xx_dma_chan = {
    .name = "pxa2xx_dma_chan",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(descr, PXA2xxDMAChannel),
        VMSTATE_UINT32(src, PXA2xxDMAChannel),
        VMSTATE_UINT32(dest, PXA2xxDMAChannel),
        VMSTATE_UINT32(cmd, PXA2xxDMAChannel),
        VMSTATE_UINT32(state, PXA2xxDMAChannel),
        VMSTATE_INT32(request, PXA2xxDMAChannel),
        VMSTATE_END_OF_LIST(),
    },
};

static VMStateDescription vmstate_pxa2xx_dma = {
    .name = "pxa2xx_dma",
    .version_id = 1,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UNUSED_TEST(is_version_0, 4),
        VMSTATE_UINT32(stopintr, PXA2xxDMAState),
        VMSTATE_UINT32(eorintr, PXA2xxDMAState),
        VMSTATE_UINT32(rasintr, PXA2xxDMAState),
        VMSTATE_UINT32(startintr, PXA2xxDMAState),
        VMSTATE_UINT32(endintr, PXA2xxDMAState),
        VMSTATE_UINT32(align, PXA2xxDMAState),
        VMSTATE_UINT32(pio, PXA2xxDMAState),
        VMSTATE_BUFFER(req, PXA2xxDMAState),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(chan, PXA2xxDMAState, channels,
                vmstate_pxa2xx_dma_chan, PXA2xxDMAChannel),
        VMSTATE_END_OF_LIST(),
    },
};

static Property pxa2xx_dma_properties[] = {
    DEFINE_PROP_INT32("channels", PXA2xxDMAState, channels, -1),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa2xx_dma_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = pxa2xx_dma_init;
    dc->desc = "PXA2xx DMA controller";
    dc->vmsd = &vmstate_pxa2xx_dma;
    dc->props = pxa2xx_dma_properties;
}

static const TypeInfo pxa2xx_dma_info = {
    .name          = TYPE_PXA2XX_DMA,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxDMAState),
    .class_init    = pxa2xx_dma_class_init,
};

static void pxa2xx_dma_register_types(void)
{
    type_register_static(&pxa2xx_dma_info);
}

type_init(pxa2xx_dma_register_types)
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 DMA controller.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Copyright (c) 2006 Thorsten Zitterell
	6	* Written by Andrzej Zaborowski <[email protected]>
	7	*
8e31bf38	8	* This code is licensed under the GPL.
c1713132 AZ	9	*/
c1713132 AZ	10
83c9f4ca	11	#include "hw/hw.h"
0d09e41a	12	#include "hw/arm/pxa.h"
83c9f4ca	13	#include "hw/sysbus.h"
2115c019 AZ	14
	15	#define PXA255_DMA_NUM_CHANNELS 16
	16	#define PXA27X_DMA_NUM_CHANNELS 32
	17
	18	#define PXA2XX_DMA_NUM_REQUESTS 75
c1713132	19
bc24a225	20	typedef struct {
a10394e1 MI	21	uint32_t descr;
	22	uint32_t src;
	23	uint32_t dest;
c1713132 AZ	24	uint32_t cmd;
	25	uint32_t state;
	26	int request;
bc24a225	27	} PXA2xxDMAChannel;
c1713132	28
358cd7ac AF	29	#define TYPE_PXA2XX_DMA "pxa2xx-dma"
	30	#define PXA2XX_DMA(obj) OBJECT_CHECK(PXA2xxDMAState, (obj), TYPE_PXA2XX_DMA)
	31
2115c019	32	typedef struct PXA2xxDMAState {
358cd7ac AF	33	SysBusDevice parent_obj;
358cd7ac AF	34
00049a12	35	MemoryRegion iomem;
c1713132 AZ	36	qemu_irq irq;
	37
	38	uint32_t stopintr;
	39	uint32_t eorintr;
	40	uint32_t rasintr;
	41	uint32_t startintr;
	42	uint32_t endintr;
	43
	44	uint32_t align;
	45	uint32_t pio;
	46
	47	int channels;
bc24a225	48	PXA2xxDMAChannel *chan;
c1713132	49
2115c019	50	uint8_t req[PXA2XX_DMA_NUM_REQUESTS];
c1713132 AZ	51
	52	/* Flag to avoid recursive DMA invocations. */
	53	int running;
2115c019	54	} PXA2xxDMAState;
c1713132 AZ	55
	56	#define DCSR0 0x0000 /* DMA Control / Status register for Channel 0 */
	57	#define DCSR31 0x007c /* DMA Control / Status register for Channel 31 */
	58	#define DALGN 0x00a0 /* DMA Alignment register */
	59	#define DPCSR 0x00a4 /* DMA Programmed I/O Control Status register */
	60	#define DRQSR0 0x00e0 /* DMA DREQ<0> Status register */
	61	#define DRQSR1 0x00e4 /* DMA DREQ<1> Status register */
	62	#define DRQSR2 0x00e8 /* DMA DREQ<2> Status register */
	63	#define DINT 0x00f0 /* DMA Interrupt register */
	64	#define DRCMR0 0x0100 /* Request to Channel Map register 0 */
	65	#define DRCMR63 0x01fc /* Request to Channel Map register 63 */
	66	#define D_CH0 0x0200 /* Channel 0 Descriptor start */
	67	#define DRCMR64 0x1100 /* Request to Channel Map register 64 */
	68	#define DRCMR74 0x1128 /* Request to Channel Map register 74 */
	69
	70	/* Per-channel register */
	71	#define DDADR 0x00
	72	#define DSADR 0x01
	73	#define DTADR 0x02
	74	#define DCMD 0x03
	75
	76	/* Bit-field masks */
	77	#define DRCMR_CHLNUM 0x1f
	78	#define DRCMR_MAPVLD (1 << 7)
	79	#define DDADR_STOP (1 << 0)
	80	#define DDADR_BREN (1 << 1)
	81	#define DCMD_LEN 0x1fff
	82	#define DCMD_WIDTH(x) (1 << ((((x) >> 14) & 3) - 1))
	83	#define DCMD_SIZE(x) (4 << (((x) >> 16) & 3))
	84	#define DCMD_FLYBYT (1 << 19)
	85	#define DCMD_FLYBYS (1 << 20)
	86	#define DCMD_ENDIRQEN (1 << 21)
	87	#define DCMD_STARTIRQEN (1 << 22)
	88	#define DCMD_CMPEN (1 << 25)
	89	#define DCMD_FLOWTRG (1 << 28)
	90	#define DCMD_FLOWSRC (1 << 29)
	91	#define DCMD_INCTRGADDR (1 << 30)
	92	#define DCMD_INCSRCADDR (1 << 31)
	93	#define DCSR_BUSERRINTR (1 << 0)
	94	#define DCSR_STARTINTR (1 << 1)
	95	#define DCSR_ENDINTR (1 << 2)
	96	#define DCSR_STOPINTR (1 << 3)
	97	#define DCSR_RASINTR (1 << 4)
	98	#define DCSR_REQPEND (1 << 8)
	99	#define DCSR_EORINT (1 << 9)
	100	#define DCSR_CMPST (1 << 10)
	101	#define DCSR_MASKRUN (1 << 22)
	102	#define DCSR_RASIRQEN (1 << 23)
	103	#define DCSR_CLRCMPST (1 << 24)
	104	#define DCSR_SETCMPST (1 << 25)
	105	#define DCSR_EORSTOPEN (1 << 26)
	106	#define DCSR_EORJMPEN (1 << 27)
	107	#define DCSR_EORIRQEN (1 << 28)
	108	#define DCSR_STOPIRQEN (1 << 29)
	109	#define DCSR_NODESCFETCH (1 << 30)
	110	#define DCSR_RUN (1 << 31)
	111
bc24a225	112	static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch)
c1713132 AZ	113	{
	114	if (ch >= 0) {
	115	if ((s->chan[ch].state & DCSR_STOPIRQEN) &&
	116	(s->chan[ch].state & DCSR_STOPINTR))
	117	s->stopintr \|= 1 << ch;
	118	else
	119	s->stopintr &= ~(1 << ch);
	120
	121	if ((s->chan[ch].state & DCSR_EORIRQEN) &&
	122	(s->chan[ch].state & DCSR_EORINT))
	123	s->eorintr \|= 1 << ch;
	124	else
	125	s->eorintr &= ~(1 << ch);
	126
	127	if ((s->chan[ch].state & DCSR_RASIRQEN) &&
	128	(s->chan[ch].state & DCSR_RASINTR))
	129	s->rasintr \|= 1 << ch;
	130	else
	131	s->rasintr &= ~(1 << ch);
	132
	133	if (s->chan[ch].state & DCSR_STARTINTR)
	134	s->startintr \|= 1 << ch;
	135	else
	136	s->startintr &= ~(1 << ch);
	137
	138	if (s->chan[ch].state & DCSR_ENDINTR)
	139	s->endintr \|= 1 << ch;
	140	else
	141	s->endintr &= ~(1 << ch);
	142	}
	143
	144	if (s->stopintr \| s->eorintr \| s->rasintr \| s->startintr \| s->endintr)
	145	qemu_irq_raise(s->irq);
	146	else
	147	qemu_irq_lower(s->irq);
	148	}
	149
	150	static inline void pxa2xx_dma_descriptor_fetch(
bc24a225	151	PXA2xxDMAState *s, int ch)
c1713132 AZ	152	{
c1713132 AZ	153	uint32_t desc[4];
a8170e5e	154	hwaddr daddr = s->chan[ch].descr & ~0xf;
c1713132 AZ	155	if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
	156	daddr += 32;
	157
e1fe50dc	158	cpu_physical_memory_read(daddr, desc, 16);
c1713132 AZ	159	s->chan[ch].descr = desc[DDADR];
	160	s->chan[ch].src = desc[DSADR];
	161	s->chan[ch].dest = desc[DTADR];
	162	s->chan[ch].cmd = desc[DCMD];
	163
	164	if (s->chan[ch].cmd & DCMD_FLOWSRC)
	165	s->chan[ch].src &= ~3;
	166	if (s->chan[ch].cmd & DCMD_FLOWTRG)
	167	s->chan[ch].dest &= ~3;
	168
	169	if (s->chan[ch].cmd & (DCMD_CMPEN \| DCMD_FLYBYS \| DCMD_FLYBYT))
	170	printf("%s: unsupported mode in channel %i\n", __FUNCTION__, ch);
	171
	172	if (s->chan[ch].cmd & DCMD_STARTIRQEN)
	173	s->chan[ch].state \|= DCSR_STARTINTR;
	174	}
	175
bc24a225	176	static void pxa2xx_dma_run(PXA2xxDMAState *s)
c1713132 AZ	177	{
	178	int c, srcinc, destinc;
	179	uint32_t n, size;
	180	uint32_t width;
	181	uint32_t length;
b55266b5	182	uint8_t buffer[32];
bc24a225	183	PXA2xxDMAChannel *ch;
c1713132 AZ	184
	185	if (s->running ++)
	186	return;
	187
	188	while (s->running) {
	189	s->running = 1;
	190	for (c = 0; c < s->channels; c ++) {
	191	ch = &s->chan[c];
	192
	193	while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) {
	194	/* Test for pending requests */
	195	if ((ch->cmd & (DCMD_FLOWSRC \| DCMD_FLOWTRG)) && !ch->request)
	196	break;
	197
	198	length = ch->cmd & DCMD_LEN;
	199	size = DCMD_SIZE(ch->cmd);
	200	width = DCMD_WIDTH(ch->cmd);
	201
	202	srcinc = (ch->cmd & DCMD_INCSRCADDR) ? width : 0;
	203	destinc = (ch->cmd & DCMD_INCTRGADDR) ? width : 0;
	204
	205	while (length) {
	206	size = MIN(length, size);
	207
	208	for (n = 0; n < size; n += width) {
	209	cpu_physical_memory_read(ch->src, buffer + n, width);
	210	ch->src += srcinc;
	211	}
	212
	213	for (n = 0; n < size; n += width) {
	214	cpu_physical_memory_write(ch->dest, buffer + n, width);
	215	ch->dest += destinc;
	216	}
	217
	218	length -= size;
	219
	220	if ((ch->cmd & (DCMD_FLOWSRC \| DCMD_FLOWTRG)) &&
	221	!ch->request) {
	222	ch->state \|= DCSR_EORINT;
	223	if (ch->state & DCSR_EORSTOPEN)
	224	ch->state \|= DCSR_STOPINTR;
	225	if ((ch->state & DCSR_EORJMPEN) &&
	226	!(ch->state & DCSR_NODESCFETCH))
	227	pxa2xx_dma_descriptor_fetch(s, c);
	228	break;
	229	}
	230	}
	231
	232	ch->cmd = (ch->cmd & ~DCMD_LEN) \| length;
	233
	234	/* Is the transfer complete now? */
	235	if (!length) {
	236	if (ch->cmd & DCMD_ENDIRQEN)
	237	ch->state \|= DCSR_ENDINTR;
	238
	239	if ((ch->state & DCSR_NODESCFETCH) \|\|
	240	(ch->descr & DDADR_STOP) \|\|
	241	(ch->state & DCSR_EORSTOPEN)) {
	242	ch->state \|= DCSR_STOPINTR;
	243	ch->state &= ~DCSR_RUN;
	244
	245	break;
	246	}
	247
248	ch->state \|= DCSR_STOPINTR;
249	break;
250	}
251	}
252	}
253
254	s->running --;
255	}
256	}
257
a8170e5e	258	static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
00049a12	259	unsigned size)
c1713132	260	{
bc24a225	261	PXA2xxDMAState s = (PXA2xxDMAState ) opaque;
c1713132	262	unsigned int channel;
c1713132	263
00049a12 AK	264	if (size != 4) {
	265	hw_error("%s: Bad access width\n", __FUNCTION__);
	266	return 5;
	267	}
	268
c1713132 AZ	269	switch (offset) {
	270	case DRCMR64 ... DRCMR74:
	271	offset -= DRCMR64 - DRCMR0 - (64 << 2);
	272	/* Fall through */
	273	case DRCMR0 ... DRCMR63:
	274	channel = (offset - DRCMR0) >> 2;
	275	return s->req[channel];
	276
	277	case DRQSR0:
	278	case DRQSR1:
	279	case DRQSR2:
	280	return 0;
	281
	282	case DCSR0 ... DCSR31:
	283	channel = offset >> 2;
	284	if (s->chan[channel].request)
	285	return s->chan[channel].state \| DCSR_REQPEND;
	286	return s->chan[channel].state;
	287
	288	case DINT:
	289	return s->stopintr \| s->eorintr \| s->rasintr \|
	290	s->startintr \| s->endintr;
	291
	292	case DALGN:
	293	return s->align;
	294
	295	case DPCSR:
	296	return s->pio;
	297	}
	298
	299	if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
	300	channel = (offset - D_CH0) >> 4;
	301	switch ((offset & 0x0f) >> 2) {
	302	case DDADR:
	303	return s->chan[channel].descr;
	304	case DSADR:
	305	return s->chan[channel].src;
	306	case DTADR:
	307	return s->chan[channel].dest;
	308	case DCMD:
	309	return s->chan[channel].cmd;
	310	}
	311	}
	312
2ac71179	313	hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset);
c1713132 AZ	314	return 7;
	315	}
	316
a8170e5e	317	static void pxa2xx_dma_write(void *opaque, hwaddr offset,
00049a12	318	uint64_t value, unsigned size)
c1713132	319	{
bc24a225	320	PXA2xxDMAState s = (PXA2xxDMAState ) opaque;
c1713132	321	unsigned int channel;
c1713132	322
00049a12 AK	323	if (size != 4) {
	324	hw_error("%s: Bad access width\n", __FUNCTION__);
	325	return;
	326	}
	327
c1713132 AZ	328	switch (offset) {
	329	case DRCMR64 ... DRCMR74:
	330	offset -= DRCMR64 - DRCMR0 - (64 << 2);
	331	/* Fall through */
	332	case DRCMR0 ... DRCMR63:
	333	channel = (offset - DRCMR0) >> 2;
	334
	335	if (value & DRCMR_MAPVLD)
	336	if ((value & DRCMR_CHLNUM) > s->channels)
2ac71179	337	hw_error("%s: Bad DMA channel %i\n",
00049a12	338	__FUNCTION__, (unsigned)value & DRCMR_CHLNUM);
c1713132 AZ	339
	340	s->req[channel] = value;
	341	break;
	342
	343	case DRQSR0:
	344	case DRQSR1:
	345	case DRQSR2:
	346	/* Nothing to do */
	347	break;
	348
	349	case DCSR0 ... DCSR31:
	350	channel = offset >> 2;
	351	s->chan[channel].state &= 0x0000071f & ~(value &
	352	(DCSR_EORINT \| DCSR_ENDINTR \|
	353	DCSR_STARTINTR \| DCSR_BUSERRINTR));
	354	s->chan[channel].state \|= value & 0xfc800000;
	355
	356	if (s->chan[channel].state & DCSR_STOPIRQEN)
	357	s->chan[channel].state &= ~DCSR_STOPINTR;
	358
	359	if (value & DCSR_NODESCFETCH) {
	360	/* No-descriptor-fetch mode */
e1dad5a6 AZ	361	if (value & DCSR_RUN) {
e1dad5a6 AZ	362	s->chan[channel].state &= ~DCSR_STOPINTR;
c1713132	363	pxa2xx_dma_run(s);
e1dad5a6	364	}
c1713132 AZ	365	} else {
	366	/* Descriptor-fetch mode */
	367	if (value & DCSR_RUN) {
	368	s->chan[channel].state &= ~DCSR_STOPINTR;
	369	pxa2xx_dma_descriptor_fetch(s, channel);
	370	pxa2xx_dma_run(s);
	371	}
	372	}
	373
	374	/* Shouldn't matter as our DMA is synchronous. */
	375	if (!(value & (DCSR_RUN \| DCSR_MASKRUN)))
	376	s->chan[channel].state \|= DCSR_STOPINTR;
	377
	378	if (value & DCSR_CLRCMPST)
	379	s->chan[channel].state &= ~DCSR_CMPST;
	380	if (value & DCSR_SETCMPST)
	381	s->chan[channel].state \|= DCSR_CMPST;
	382
	383	pxa2xx_dma_update(s, channel);
	384	break;
	385
	386	case DALGN:
	387	s->align = value;
	388	break;
	389
	390	case DPCSR:
	391	s->pio = value & 0x80000001;
	392	break;
	393
	394	default:
	395	if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
	396	channel = (offset - D_CH0) >> 4;
	397	switch ((offset & 0x0f) >> 2) {
	398	case DDADR:
	399	s->chan[channel].descr = value;
	400	break;
	401	case DSADR:
	402	s->chan[channel].src = value;
	403	break;
	404	case DTADR:
	405	s->chan[channel].dest = value;
	406	break;
	407	case DCMD:
	408	s->chan[channel].cmd = value;
	409	break;
	410	default:
	411	goto fail;
	412	}
	413
	414	break;
	415	}
	416	fail:
2ac71179	417	hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __FUNCTION__, offset);
c1713132 AZ	418	}
	419	}
	420
00049a12 AK	421	static const MemoryRegionOps pxa2xx_dma_ops = {
	422	.read = pxa2xx_dma_read,
	423	.write = pxa2xx_dma_write,
	424	.endianness = DEVICE_NATIVE_ENDIAN,
c1713132 AZ	425	};
c1713132 AZ	426
f114c826 AZ	427	static void pxa2xx_dma_request(void *opaque, int req_num, int on)
	428	{
	429	PXA2xxDMAState *s = opaque;
	430	int ch;
	431	if (req_num < 0 \|\| req_num >= PXA2XX_DMA_NUM_REQUESTS)
	432	hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num);
	433
	434	if (!(s->req[req_num] & DRCMR_MAPVLD))
	435	return;
	436	ch = s->req[req_num] & DRCMR_CHLNUM;
	437
	438	if (!s->chan[ch].request && on)
	439	s->chan[ch].state \|= DCSR_RASINTR;
	440	else
	441	s->chan[ch].state &= ~DCSR_RASINTR;
	442	if (s->chan[ch].request && !on)
	443	s->chan[ch].state \|= DCSR_EORINT;
	444
	445	s->chan[ch].request = on;
	446	if (on) {
	447	pxa2xx_dma_run(s);
	448	pxa2xx_dma_update(s, ch);
	449	}
	450	}
aa941b94	451
358cd7ac	452	static int pxa2xx_dma_init(SysBusDevice *sbd)
c1713132	453	{
358cd7ac AF	454	DeviceState *dev = DEVICE(sbd);
358cd7ac AF	455	PXA2xxDMAState *s = PXA2XX_DMA(dev);
00049a12	456	int i;
2115c019 AZ	457
	458	if (s->channels <= 0) {
	459	return -1;
	460	}
c1713132	461
7267c094	462	s->chan = g_malloc0(sizeof(PXA2xxDMAChannel) * s->channels);
c1713132	463
bc24a225	464	memset(s->chan, 0, sizeof(PXA2xxDMAChannel) * s->channels);
c1713132 AZ	465	for (i = 0; i < s->channels; i ++)
	466	s->chan[i].state = DCSR_STOPINTR;
	467
3f582262	468	memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
c1713132	469
358cd7ac	470	qdev_init_gpio_in(dev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);
2115c019	471
3eadad55	472	memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_dma_ops, s,
00049a12	473	"pxa2xx.dma", 0x00010000);
358cd7ac AF	474	sysbus_init_mmio(sbd, &s->iomem);
358cd7ac AF	475	sysbus_init_irq(sbd, &s->irq);
c1713132	476
2115c019	477	return 0;
c1713132 AZ	478	}
c1713132 AZ	479
a8170e5e	480	DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq)
c1713132	481	{
2115c019 AZ	482	DeviceState *dev;
	483
	484	dev = qdev_create(NULL, "pxa2xx-dma");
	485	qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
	486	qdev_init_nofail(dev);
	487
1356b98d AF	488	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1356b98d AF	489	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
2115c019 AZ	490
2115c019 AZ	491	return dev;
c1713132 AZ	492	}
c1713132 AZ	493
a8170e5e	494	DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq)
c1713132	495	{
2115c019 AZ	496	DeviceState *dev;
	497
	498	dev = qdev_create(NULL, "pxa2xx-dma");
	499	qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
	500	qdev_init_nofail(dev);
	501
1356b98d AF	502	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1356b98d AF	503	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
2115c019 AZ	504
2115c019 AZ	505	return dev;
c1713132 AZ	506	}
c1713132 AZ	507
2115c019 AZ	508	static bool is_version_0(void *opaque, int version_id)
	509	{
	510	return version_id == 0;
	511	}
	512
	513	static VMStateDescription vmstate_pxa2xx_dma_chan = {
	514	.name = "pxa2xx_dma_chan",
	515	.version_id = 1,
	516	.minimum_version_id = 1,
2115c019	517	.fields = (VMStateField[]) {
a10394e1 MI	518	VMSTATE_UINT32(descr, PXA2xxDMAChannel),
	519	VMSTATE_UINT32(src, PXA2xxDMAChannel),
	520	VMSTATE_UINT32(dest, PXA2xxDMAChannel),
2115c019 AZ	521	VMSTATE_UINT32(cmd, PXA2xxDMAChannel),
	522	VMSTATE_UINT32(state, PXA2xxDMAChannel),
	523	VMSTATE_INT32(request, PXA2xxDMAChannel),
	524	VMSTATE_END_OF_LIST(),
	525	},
	526	};
	527
	528	static VMStateDescription vmstate_pxa2xx_dma = {
	529	.name = "pxa2xx_dma",
	530	.version_id = 1,
	531	.minimum_version_id = 0,
2115c019 AZ	532	.fields = (VMStateField[]) {
	533	VMSTATE_UNUSED_TEST(is_version_0, 4),
	534	VMSTATE_UINT32(stopintr, PXA2xxDMAState),
	535	VMSTATE_UINT32(eorintr, PXA2xxDMAState),
	536	VMSTATE_UINT32(rasintr, PXA2xxDMAState),
	537	VMSTATE_UINT32(startintr, PXA2xxDMAState),
	538	VMSTATE_UINT32(endintr, PXA2xxDMAState),
	539	VMSTATE_UINT32(align, PXA2xxDMAState),
	540	VMSTATE_UINT32(pio, PXA2xxDMAState),
	541	VMSTATE_BUFFER(req, PXA2xxDMAState),
	542	VMSTATE_STRUCT_VARRAY_POINTER_INT32(chan, PXA2xxDMAState, channels,
	543	vmstate_pxa2xx_dma_chan, PXA2xxDMAChannel),
	544	VMSTATE_END_OF_LIST(),
	545	},
	546	};
	547
999e12bb AL	548	static Property pxa2xx_dma_properties[] = {
	549	DEFINE_PROP_INT32("channels", PXA2xxDMAState, channels, -1),
	550	DEFINE_PROP_END_OF_LIST(),
	551	};
	552
	553	static void pxa2xx_dma_class_init(ObjectClass klass, void data)
	554	{
39bffca2	555	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	556	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	557
	558	k->init = pxa2xx_dma_init;
39bffca2 AL	559	dc->desc = "PXA2xx DMA controller";
	560	dc->vmsd = &vmstate_pxa2xx_dma;
	561	dc->props = pxa2xx_dma_properties;
999e12bb AL	562	}
999e12bb AL	563
8c43a6f0	564	static const TypeInfo pxa2xx_dma_info = {
358cd7ac	565	.name = TYPE_PXA2XX_DMA,
39bffca2 AL	566	.parent = TYPE_SYS_BUS_DEVICE,
	567	.instance_size = sizeof(PXA2xxDMAState),
	568	.class_init = pxa2xx_dma_class_init,
2115c019 AZ	569	};
2115c019 AZ	570
83f7d43a	571	static void pxa2xx_dma_register_types(void)
2115c019	572	{
39bffca2	573	type_register_static(&pxa2xx_dma_info);
2115c019	574	}
83f7d43a AF	575
83f7d43a AF	576	type_init(pxa2xx_dma_register_types)