[qemu.git] / hw / dma / pl080.c

/*
 * Arm PrimeCell PL080/PL081 DMA controller
 *
 * Copyright (c) 2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "hw/sysbus.h"
#include "exec/address-spaces.h"

#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E    0x1
#define PL080_CONF_M1   0x2
#define PL080_CONF_M2   0x4

#define PL080_CCONF_H   0x40000
#define PL080_CCONF_A   0x20000
#define PL080_CCONF_L   0x10000
#define PL080_CCONF_ITC 0x08000
#define PL080_CCONF_IE  0x04000
#define PL080_CCONF_E   0x00001

#define PL080_CCTRL_I   0x80000000
#define PL080_CCTRL_DI  0x08000000
#define PL080_CCTRL_SI  0x04000000
#define PL080_CCTRL_D   0x02000000
#define PL080_CCTRL_S   0x01000000

typedef struct {
    uint32_t src;
    uint32_t dest;
    uint32_t lli;
    uint32_t ctrl;
    uint32_t conf;
} pl080_channel;

#define TYPE_PL080 "pl080"
#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)

typedef struct PL080State {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint8_t tc_int;
    uint8_t tc_mask;
    uint8_t err_int;
    uint8_t err_mask;
    uint32_t conf;
    uint32_t sync;
    uint32_t req_single;
    uint32_t req_burst;
    pl080_channel chan[PL080_MAX_CHANNELS];
    int nchannels;
    /* Flag to avoid recursive DMA invocations.  */
    int running;
    qemu_irq irq;
} PL080State;

static const VMStateDescription vmstate_pl080_channel = {
    .name = "pl080_channel",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(src, pl080_channel),
        VMSTATE_UINT32(dest, pl080_channel),
        VMSTATE_UINT32(lli, pl080_channel),
        VMSTATE_UINT32(ctrl, pl080_channel),
        VMSTATE_UINT32(conf, pl080_channel),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pl080 = {
    .name = "pl080",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_mask, PL080State),
        VMSTATE_UINT8(err_int, PL080State),
        VMSTATE_UINT8(err_mask, PL080State),
        VMSTATE_UINT32(conf, PL080State),
        VMSTATE_UINT32(sync, PL080State),
        VMSTATE_UINT32(req_single, PL080State),
        VMSTATE_UINT32(req_burst, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS,
                             1, vmstate_pl080_channel, pl080_channel),
        VMSTATE_INT32(running, PL080State),
        VMSTATE_END_OF_LIST()
    }
};

static const unsigned char pl080_id[] =
{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static const unsigned char pl081_id[] =
{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static void pl080_update(PL080State *s)
{
    if ((s->tc_int & s->tc_mask)
            || (s->err_int & s->err_mask))
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void pl080_run(PL080State *s)
{
    int c;
    int flow;
    pl080_channel *ch;
    int swidth;
    int dwidth;
    int xsize;
    int n;
    int src_id;
    int dest_id;
    int size;
    uint8_t buff[4];
    uint32_t req;

    s->tc_mask = 0;
    for (c = 0; c < s->nchannels; c++) {
        if (s->chan[c].conf & PL080_CCONF_ITC)
            s->tc_mask |= 1 << c;
        if (s->chan[c].conf & PL080_CCONF_IE)
            s->err_mask |= 1 << c;
    }

    if ((s->conf & PL080_CONF_E) == 0)
        return;

hw_error("DMA active\n");
    /* If we are already in the middle of a DMA operation then indicate that
       there may be new DMA requests and return immediately.  */
    if (s->running) {
        s->running++;
        return;
    }
    s->running = 1;
    while (s->running) {
        for (c = 0; c < s->nchannels; c++) {
            ch = &s->chan[c];
again:
            /* Test if thiws channel has any pending DMA requests.  */
            if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E))
                    != PL080_CCONF_E)
                continue;
            flow = (ch->conf >> 11) & 7;
            if (flow >= 4) {
                hw_error(
                    "pl080_run: Peripheral flow control not implemented\n");
            }
            src_id = (ch->conf >> 1) & 0x1f;
            dest_id = (ch->conf >> 6) & 0x1f;
            size = ch->ctrl & 0xfff;
            req = s->req_single | s->req_burst;
            switch (flow) {
            case 0:
                break;
            case 1:
                if ((req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            case 2:
                if ((req & (1u << src_id)) == 0)
                    size = 0;
                break;
            case 3:
                if ((req & (1u << src_id)) == 0
                        || (req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            }
            if (!size)
                continue;

            /* Transfer one element.  */
            /* ??? Should transfer multiple elements for a burst request.  */
            /* ??? Unclear what the proper behavior is when source and
               destination widths are different.  */
            swidth = 1 << ((ch->ctrl >> 18) & 7);
            dwidth = 1 << ((ch->ctrl >> 21) & 7);
            for (n = 0; n < dwidth; n+= swidth) {
                cpu_physical_memory_read(ch->src, buff + n, swidth);
                if (ch->ctrl & PL080_CCTRL_SI)
                    ch->src += swidth;
            }
            xsize = (dwidth < swidth) ? swidth : dwidth;
            /* ??? This may pad the value incorrectly for dwidth < 32.  */
            for (n = 0; n < xsize; n += dwidth) {
                cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);
                if (ch->ctrl & PL080_CCTRL_DI)
                    ch->dest += swidth;
            }

            size--;
            ch->ctrl = (ch->ctrl & 0xfffff000) | size;
            if (size == 0) {
                /* Transfer complete.  */
                if (ch->lli) {
                    ch->src = ldl_le_phys(&address_space_memory, ch->lli);
                    ch->dest = ldl_le_phys(&address_space_memory, ch->lli + 4);
                    ch->ctrl = ldl_le_phys(&address_space_memory, ch->lli + 12);
                    ch->lli = ldl_le_phys(&address_space_memory, ch->lli + 8);
                } else {
                    ch->conf &= ~PL080_CCONF_E;
                }
                if (ch->ctrl & PL080_CCTRL_I) {
                    s->tc_int |= 1 << c;
                }
            }
            goto again;
        }
        if (--s->running)
            s->running = 1;
    }
}

static uint64_t pl080_read(void *opaque, hwaddr offset,
                           unsigned size)
{
    PL080State *s = (PL080State *)opaque;
    uint32_t i;
    uint32_t mask;

    if (offset >= 0xfe0 && offset < 0x1000) {
        if (s->nchannels == 8) {
            return pl080_id[(offset - 0xfe0) >> 2];
        } else {
            return pl081_id[(offset - 0xfe0) >> 2];
        }
    }
    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch (offset >> 2) {
        case 0: /* SrcAddr */
            return s->chan[i].src;
        case 1: /* DestAddr */
            return s->chan[i].dest;
        case 2: /* LLI */
            return s->chan[i].lli;
        case 3: /* Control */
            return s->chan[i].ctrl;
        case 4: /* Configuration */
            return s->chan[i].conf;
        default:
            goto bad_offset;
        }
    }
    switch (offset >> 2) {
    case 0: /* IntStatus */
        return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask);
    case 1: /* IntTCStatus */
        return (s->tc_int & s->tc_mask);
    case 3: /* IntErrorStatus */
        return (s->err_int & s->err_mask);
    case 5: /* RawIntTCStatus */
        return s->tc_int;
    case 6: /* RawIntErrorStatus */
        return s->err_int;
    case 7: /* EnbldChns */
        mask = 0;
        for (i = 0; i < s->nchannels; i++) {
            if (s->chan[i].conf & PL080_CCONF_E)
                mask |= 1 << i;
        }
        return mask;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these. */
        return 0;
    case 12: /* Configuration */
        return s->conf;
    case 13: /* Sync */
        return s->sync;
    default:
    bad_offset:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl080_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl080_write(void *opaque, hwaddr offset,
                        uint64_t value, unsigned size)
{
    PL080State *s = (PL080State *)opaque;
    int i;

    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch (offset >> 2) {
        case 0: /* SrcAddr */
            s->chan[i].src = value;
            break;
        case 1: /* DestAddr */
            s->chan[i].dest = value;
            break;
        case 2: /* LLI */
            s->chan[i].lli = value;
            break;
        case 3: /* Control */
            s->chan[i].ctrl = value;
            break;
        case 4: /* Configuration */
            s->chan[i].conf = value;
            pl080_run(s);
            break;
        }
    }
    switch (offset >> 2) {
    case 2: /* IntTCClear */
        s->tc_int &= ~value;
        break;
    case 4: /* IntErrorClear */
        s->err_int &= ~value;
        break;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these.  */
        qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n");
        break;
    case 12: /* Configuration */
        s->conf = value;
        if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
            qemu_log_mask(LOG_UNIMP,
                          "pl080_write: Big-endian DMA not implemented\n");
        }
        pl080_run(s);
        break;
    case 13: /* Sync */
        s->sync = value;
        break;
    default:
    bad_offset:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl080_write: Bad offset %x\n", (int)offset);
    }
    pl080_update(s);
}

static const MemoryRegionOps pl080_ops = {
    .read = pl080_read,
    .write = pl080_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pl080_init(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    PL080State *s = PL080(obj);

    memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
    s->nchannels = 8;
}

static void pl081_init(Object *obj)
{
    PL080State *s = PL080(obj);

    s->nchannels = 2;
}

static void pl080_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->vmsd = &vmstate_pl080;
}

static const TypeInfo pl080_info = {
    .name          = TYPE_PL080,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PL080State),
    .instance_init = pl080_init,
    .class_init    = pl080_class_init,
};

static const TypeInfo pl081_info = {
    .name          = "pl081",
    .parent        = TYPE_PL080,
    .instance_init = pl081_init,
};

/* The PL080 and PL081 are the same except for the number of channels
   they implement (8 and 2 respectively).  */
static void pl080_register_types(void)
{
    type_register_static(&pl080_info);
    type_register_static(&pl081_info);
}

type_init(pl080_register_types)
Commit	Line	Data
5fafdf24	1	/*
e69954b9	2	* Arm PrimeCell PL080/PL081 DMA controller
cdbdb648 PB	3	*
	4	* Copyright (c) 2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
cdbdb648 PB	8	*/
cdbdb648 PB	9
83c9f4ca	10	#include "hw/sysbus.h"
fdfba1a2	11	#include "exec/address-spaces.h"
cdbdb648	12
e69954b9	13	#define PL080_MAX_CHANNELS 8
cdbdb648 PB	14	#define PL080_CONF_E 0x1
	15	#define PL080_CONF_M1 0x2
	16	#define PL080_CONF_M2 0x4
	17
	18	#define PL080_CCONF_H 0x40000
	19	#define PL080_CCONF_A 0x20000
	20	#define PL080_CCONF_L 0x10000
	21	#define PL080_CCONF_ITC 0x08000
	22	#define PL080_CCONF_IE 0x04000
	23	#define PL080_CCONF_E 0x00001
	24
	25	#define PL080_CCTRL_I 0x80000000
	26	#define PL080_CCTRL_DI 0x08000000
	27	#define PL080_CCTRL_SI 0x04000000
	28	#define PL080_CCTRL_D 0x02000000
	29	#define PL080_CCTRL_S 0x01000000
	30
	31	typedef struct {
	32	uint32_t src;
	33	uint32_t dest;
	34	uint32_t lli;
	35	uint32_t ctrl;
	36	uint32_t conf;
	37	} pl080_channel;
	38
4f800554 AF	39	#define TYPE_PL080 "pl080"
	40	#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)
	41
d7ba0a62	42	typedef struct PL080State {
4f800554 AF	43	SysBusDevice parent_obj;
4f800554 AF	44
63b02e04	45	MemoryRegion iomem;
cdbdb648 PB	46	uint8_t tc_int;
	47	uint8_t tc_mask;
	48	uint8_t err_int;
	49	uint8_t err_mask;
	50	uint32_t conf;
	51	uint32_t sync;
	52	uint32_t req_single;
	53	uint32_t req_burst;
e69954b9 PB	54	pl080_channel chan[PL080_MAX_CHANNELS];
e69954b9 PB	55	int nchannels;
cdbdb648 PB	56	/* Flag to avoid recursive DMA invocations. */
cdbdb648 PB	57	int running;
d537cf6c	58	qemu_irq irq;
d7ba0a62	59	} PL080State;
cdbdb648	60
ff175853 PM	61	static const VMStateDescription vmstate_pl080_channel = {
	62	.name = "pl080_channel",
	63	.version_id = 1,
	64	.minimum_version_id = 1,
	65	.fields = (VMStateField[]) {
	66	VMSTATE_UINT32(src, pl080_channel),
	67	VMSTATE_UINT32(dest, pl080_channel),
	68	VMSTATE_UINT32(lli, pl080_channel),
	69	VMSTATE_UINT32(ctrl, pl080_channel),
	70	VMSTATE_UINT32(conf, pl080_channel),
	71	VMSTATE_END_OF_LIST()
	72	}
	73	};
	74
	75	static const VMStateDescription vmstate_pl080 = {
	76	.name = "pl080",
	77	.version_id = 1,
	78	.minimum_version_id = 1,
	79	.fields = (VMStateField[]) {
d7ba0a62 AF	80	VMSTATE_UINT8(tc_int, PL080State),
	81	VMSTATE_UINT8(tc_mask, PL080State),
	82	VMSTATE_UINT8(err_int, PL080State),
	83	VMSTATE_UINT8(err_mask, PL080State),
	84	VMSTATE_UINT32(conf, PL080State),
	85	VMSTATE_UINT32(sync, PL080State),
	86	VMSTATE_UINT32(req_single, PL080State),
	87	VMSTATE_UINT32(req_burst, PL080State),
	88	VMSTATE_UINT8(tc_int, PL080State),
	89	VMSTATE_UINT8(tc_int, PL080State),
	90	VMSTATE_UINT8(tc_int, PL080State),
	91	VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS,
ff175853	92	1, vmstate_pl080_channel, pl080_channel),
d7ba0a62	93	VMSTATE_INT32(running, PL080State),
ff175853 PM	94	VMSTATE_END_OF_LIST()
	95	}
	96	};
	97
cdbdb648 PB	98	static const unsigned char pl080_id[] =
	99	{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	100
e69954b9 PB	101	static const unsigned char pl081_id[] =
	102	{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	103
d7ba0a62	104	static void pl080_update(PL080State *s)
cdbdb648 PB	105	{
	106	if ((s->tc_int & s->tc_mask)
	107	\|\| (s->err_int & s->err_mask))
d537cf6c	108	qemu_irq_raise(s->irq);
cdbdb648	109	else
d537cf6c	110	qemu_irq_lower(s->irq);
cdbdb648 PB	111	}
cdbdb648 PB	112
d7ba0a62	113	static void pl080_run(PL080State *s)
cdbdb648 PB	114	{
	115	int c;
	116	int flow;
	117	pl080_channel *ch;
	118	int swidth;
	119	int dwidth;
	120	int xsize;
	121	int n;
	122	int src_id;
	123	int dest_id;
	124	int size;
b55266b5	125	uint8_t buff[4];
cdbdb648 PB	126	uint32_t req;
	127
	128	s->tc_mask = 0;
e69954b9	129	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	130	if (s->chan[c].conf & PL080_CCONF_ITC)
	131	s->tc_mask \|= 1 << c;
	132	if (s->chan[c].conf & PL080_CCONF_IE)
	133	s->err_mask \|= 1 << c;
	134	}
	135
	136	if ((s->conf & PL080_CONF_E) == 0)
	137	return;
	138
2ac71179	139	hw_error("DMA active\n");
cdbdb648 PB	140	/* If we are already in the middle of a DMA operation then indicate that
	141	there may be new DMA requests and return immediately. */
	142	if (s->running) {
	143	s->running++;
	144	return;
	145	}
	146	s->running = 1;
	147	while (s->running) {
e69954b9	148	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	149	ch = &s->chan[c];
	150	again:
	151	/* Test if thiws channel has any pending DMA requests. */
	152	if ((ch->conf & (PL080_CCONF_H \| PL080_CCONF_E))
	153	!= PL080_CCONF_E)
	154	continue;
	155	flow = (ch->conf >> 11) & 7;
	156	if (flow >= 4) {
2ac71179	157	hw_error(
cdbdb648 PB	158	"pl080_run: Peripheral flow control not implemented\n");
	159	}
	160	src_id = (ch->conf >> 1) & 0x1f;
	161	dest_id = (ch->conf >> 6) & 0x1f;
	162	size = ch->ctrl & 0xfff;
	163	req = s->req_single \| s->req_burst;
	164	switch (flow) {
	165	case 0:
	166	break;
	167	case 1:
	168	if ((req & (1u << dest_id)) == 0)
	169	size = 0;
	170	break;
	171	case 2:
	172	if ((req & (1u << src_id)) == 0)
	173	size = 0;
	174	break;
	175	case 3:
	176	if ((req & (1u << src_id)) == 0
	177	\|\| (req & (1u << dest_id)) == 0)
	178	size = 0;
	179	break;
	180	}
	181	if (!size)
	182	continue;
	183
	184	/* Transfer one element. */
	185	/* ??? Should transfer multiple elements for a burst request. */
	186	/* ??? Unclear what the proper behavior is when source and
	187	destination widths are different. */
	188	swidth = 1 << ((ch->ctrl >> 18) & 7);
	189	dwidth = 1 << ((ch->ctrl >> 21) & 7);
	190	for (n = 0; n < dwidth; n+= swidth) {
	191	cpu_physical_memory_read(ch->src, buff + n, swidth);
	192	if (ch->ctrl & PL080_CCTRL_SI)
	193	ch->src += swidth;
	194	}
	195	xsize = (dwidth < swidth) ? swidth : dwidth;
	196	/* ??? This may pad the value incorrectly for dwidth < 32. */
	197	for (n = 0; n < xsize; n += dwidth) {
	198	cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);
	199	if (ch->ctrl & PL080_CCTRL_DI)
	200	ch->dest += swidth;
	201	}
	202
	203	size--;
	204	ch->ctrl = (ch->ctrl & 0xfffff000) \| size;
	205	if (size == 0) {
	206	/* Transfer complete. */
	207	if (ch->lli) {
fdfba1a2 EI	208	ch->src = ldl_le_phys(&address_space_memory, ch->lli);
	209	ch->dest = ldl_le_phys(&address_space_memory, ch->lli + 4);
	210	ch->ctrl = ldl_le_phys(&address_space_memory, ch->lli + 12);
	211	ch->lli = ldl_le_phys(&address_space_memory, ch->lli + 8);
cdbdb648 PB	212	} else {
	213	ch->conf &= ~PL080_CCONF_E;
	214	}
	215	if (ch->ctrl & PL080_CCTRL_I) {
	216	s->tc_int \|= 1 << c;
	217	}
	218	}
	219	goto again;
	220	}
	221	if (--s->running)
	222	s->running = 1;
	223	}
	224	}
	225
a8170e5e	226	static uint64_t pl080_read(void *opaque, hwaddr offset,
63b02e04	227	unsigned size)
cdbdb648	228	{
d7ba0a62	229	PL080State s = (PL080State )opaque;
cdbdb648 PB	230	uint32_t i;
	231	uint32_t mask;
	232
cdbdb648	233	if (offset >= 0xfe0 && offset < 0x1000) {
e69954b9 PB	234	if (s->nchannels == 8) {
	235	return pl080_id[(offset - 0xfe0) >> 2];
	236	} else {
	237	return pl081_id[(offset - 0xfe0) >> 2];
	238	}
cdbdb648 PB	239	}
	240	if (offset >= 0x100 && offset < 0x200) {
	241	i = (offset & 0xe0) >> 5;
e69954b9 PB	242	if (i >= s->nchannels)
e69954b9 PB	243	goto bad_offset;
cdbdb648 PB	244	switch (offset >> 2) {
	245	case 0: /* SrcAddr */
	246	return s->chan[i].src;
	247	case 1: /* DestAddr */
	248	return s->chan[i].dest;
	249	case 2: /* LLI */
	250	return s->chan[i].lli;
	251	case 3: /* Control */
	252	return s->chan[i].ctrl;
	253	case 4: /* Configuration */
	254	return s->chan[i].conf;
	255	default:
	256	goto bad_offset;
	257	}
	258	}
	259	switch (offset >> 2) {
	260	case 0: /* IntStatus */
	261	return (s->tc_int & s->tc_mask) \| (s->err_int & s->err_mask);
	262	case 1: /* IntTCStatus */
	263	return (s->tc_int & s->tc_mask);
	264	case 3: /* IntErrorStatus */
	265	return (s->err_int & s->err_mask);
	266	case 5: /* RawIntTCStatus */
	267	return s->tc_int;
	268	case 6: /* RawIntErrorStatus */
	269	return s->err_int;
	270	case 7: /* EnbldChns */
	271	mask = 0;
e69954b9	272	for (i = 0; i < s->nchannels; i++) {
cdbdb648 PB	273	if (s->chan[i].conf & PL080_CCONF_E)
	274	mask \|= 1 << i;
	275	}
	276	return mask;
	277	case 8: /* SoftBReq */
	278	case 9: /* SoftSReq */
	279	case 10: /* SoftLBReq */
	280	case 11: /* SoftLSReq */
	281	/* ??? Implement these. */
	282	return 0;
	283	case 12: /* Configuration */
	284	return s->conf;
	285	case 13: /* Sync */
	286	return s->sync;
	287	default:
	288	bad_offset:
df374162 PM	289	qemu_log_mask(LOG_GUEST_ERROR,
df374162 PM	290	"pl080_read: Bad offset %x\n", (int)offset);
cdbdb648 PB	291	return 0;
	292	}
	293	}
	294
a8170e5e	295	static void pl080_write(void *opaque, hwaddr offset,
63b02e04	296	uint64_t value, unsigned size)
cdbdb648	297	{
d7ba0a62	298	PL080State s = (PL080State )opaque;
cdbdb648 PB	299	int i;
cdbdb648 PB	300
cdbdb648 PB	301	if (offset >= 0x100 && offset < 0x200) {
cdbdb648 PB	302	i = (offset & 0xe0) >> 5;
e69954b9 PB	303	if (i >= s->nchannels)
e69954b9 PB	304	goto bad_offset;
cdbdb648 PB	305	switch (offset >> 2) {
	306	case 0: /* SrcAddr */
	307	s->chan[i].src = value;
	308	break;
	309	case 1: /* DestAddr */
	310	s->chan[i].dest = value;
	311	break;
	312	case 2: /* LLI */
	313	s->chan[i].lli = value;
	314	break;
	315	case 3: /* Control */
	316	s->chan[i].ctrl = value;
	317	break;
	318	case 4: /* Configuration */
	319	s->chan[i].conf = value;
	320	pl080_run(s);
	321	break;
	322	}
	323	}
	324	switch (offset >> 2) {
	325	case 2: /* IntTCClear */
	326	s->tc_int &= ~value;
	327	break;
	328	case 4: /* IntErrorClear */
	329	s->err_int &= ~value;
	330	break;
	331	case 8: /* SoftBReq */
	332	case 9: /* SoftSReq */
	333	case 10: /* SoftLBReq */
	334	case 11: /* SoftLSReq */
	335	/* ??? Implement these. */
df374162	336	qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n");
cdbdb648 PB	337	break;
	338	case 12: /* Configuration */
	339	s->conf = value;
	340	if (s->conf & (PL080_CONF_M1 \| PL080_CONF_M1)) {
df374162 PM	341	qemu_log_mask(LOG_UNIMP,
df374162 PM	342	"pl080_write: Big-endian DMA not implemented\n");
cdbdb648 PB	343	}
	344	pl080_run(s);
	345	break;
	346	case 13: /* Sync */
	347	s->sync = value;
	348	break;
	349	default:
e69954b9	350	bad_offset:
df374162 PM	351	qemu_log_mask(LOG_GUEST_ERROR,
df374162 PM	352	"pl080_write: Bad offset %x\n", (int)offset);
cdbdb648 PB	353	}
	354	pl080_update(s);
	355	}
	356
63b02e04 AK	357	static const MemoryRegionOps pl080_ops = {
	358	.read = pl080_read,
	359	.write = pl080_write,
	360	.endianness = DEVICE_NATIVE_ENDIAN,
cdbdb648 PB	361	};
cdbdb648 PB	362
4f800554	363	static void pl080_init(Object *obj)
cdbdb648	364	{
4f800554 AF	365	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
4f800554 AF	366	PL080State *s = PL080(obj);
cdbdb648	367
3eadad55	368	memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
4f800554 AF	369	sysbus_init_mmio(sbd, &s->iomem);
	370	sysbus_init_irq(sbd, &s->irq);
	371	s->nchannels = 8;
cdbdb648	372	}
b4496b13	373
4f800554	374	static void pl081_init(Object *obj)
b4496b13	375	{
4f800554	376	PL080State *s = PL080(obj);
b4496b13	377
4f800554	378	s->nchannels = 2;
b4496b13 PB	379	}
b4496b13 PB	380
4f800554	381	static void pl080_class_init(ObjectClass oc, void data)
999e12bb	382	{
4f800554	383	DeviceClass *dc = DEVICE_CLASS(oc);
999e12bb	384
39bffca2	385	dc->vmsd = &vmstate_pl080;
999e12bb AL	386	}
999e12bb AL	387
8c43a6f0	388	static const TypeInfo pl080_info = {
4f800554	389	.name = TYPE_PL080,
39bffca2	390	.parent = TYPE_SYS_BUS_DEVICE,
d7ba0a62	391	.instance_size = sizeof(PL080State),
4f800554	392	.instance_init = pl080_init,
39bffca2	393	.class_init = pl080_class_init,
ff175853 PM	394	};
ff175853 PM	395
8c43a6f0	396	static const TypeInfo pl081_info = {
39bffca2	397	.name = "pl081",
4f800554 AF	398	.parent = TYPE_PL080,
4f800554 AF	399	.instance_init = pl081_init,
ff175853 PM	400	};
ff175853 PM	401
b4496b13 PB	402	/* The PL080 and PL081 are the same except for the number of channels
b4496b13 PB	403	they implement (8 and 2 respectively). */
83f7d43a	404	static void pl080_register_types(void)
b4496b13	405	{
39bffca2 AL	406	type_register_static(&pl080_info);
39bffca2 AL	407	type_register_static(&pl081_info);
b4496b13 PB	408	}
b4496b13 PB	409
83f7d43a	410	type_init(pl080_register_types)