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d537cf6c PB |
1 | /* |
2 | * QEMU IRQ/GPIO common code. | |
5fafdf24 | 3 | * |
d537cf6c | 4 | * Copyright (c) 2007 CodeSourcery. |
5fafdf24 | 5 | * |
d537cf6c PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
18c86e2b | 24 | #include "qemu/osdep.h" |
8d04fb55 | 25 | #include "qemu/main-loop.h" |
87ecb68b | 26 | #include "qemu-common.h" |
83c9f4ca | 27 | #include "hw/irq.h" |
615c4895 AF |
28 | #include "qom/object.h" |
29 | ||
30 | #define IRQ(obj) OBJECT_CHECK(struct IRQState, (obj), TYPE_IRQ) | |
d537cf6c PB |
31 | |
32 | struct IRQState { | |
615c4895 AF |
33 | Object parent_obj; |
34 | ||
d537cf6c PB |
35 | qemu_irq_handler handler; |
36 | void *opaque; | |
37 | int n; | |
38 | }; | |
39 | ||
40 | void qemu_set_irq(qemu_irq irq, int level) | |
41 | { | |
42 | if (!irq) | |
43 | return; | |
44 | ||
45 | irq->handler(irq->opaque, irq->n, level); | |
46 | } | |
47 | ||
1e5b31e6 PC |
48 | qemu_irq *qemu_extend_irqs(qemu_irq *old, int n_old, qemu_irq_handler handler, |
49 | void *opaque, int n) | |
d537cf6c PB |
50 | { |
51 | qemu_irq *s; | |
d537cf6c PB |
52 | int i; |
53 | ||
1e5b31e6 PC |
54 | if (!old) { |
55 | n_old = 0; | |
56 | } | |
57 | s = old ? g_renew(qemu_irq, old, n + n_old) : g_new(qemu_irq, n); | |
f173d57a PC |
58 | for (i = n_old; i < n + n_old; i++) { |
59 | s[i] = qemu_allocate_irq(handler, opaque, i); | |
d537cf6c PB |
60 | } |
61 | return s; | |
62 | } | |
63 | ||
1e5b31e6 PC |
64 | qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n) |
65 | { | |
66 | return qemu_extend_irqs(NULL, 0, handler, opaque, n); | |
67 | } | |
68 | ||
a8a9d30b MA |
69 | qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n) |
70 | { | |
71 | struct IRQState *irq; | |
72 | ||
615c4895 | 73 | irq = IRQ(object_new(TYPE_IRQ)); |
a8a9d30b MA |
74 | irq->handler = handler; |
75 | irq->opaque = opaque; | |
76 | irq->n = n; | |
77 | ||
78 | return irq; | |
79 | } | |
1e5b31e6 | 80 | |
f173d57a | 81 | void qemu_free_irqs(qemu_irq *s, int n) |
51bf9e7e | 82 | { |
f173d57a PC |
83 | int i; |
84 | for (i = 0; i < n; i++) { | |
85 | qemu_free_irq(s[i]); | |
86 | } | |
7267c094 | 87 | g_free(s); |
51bf9e7e AL |
88 | } |
89 | ||
a8a9d30b MA |
90 | void qemu_free_irq(qemu_irq irq) |
91 | { | |
615c4895 | 92 | object_unref(OBJECT(irq)); |
a8a9d30b MA |
93 | } |
94 | ||
b50a6563 AZ |
95 | static void qemu_notirq(void *opaque, int line, int level) |
96 | { | |
97 | struct IRQState *irq = opaque; | |
98 | ||
99 | irq->handler(irq->opaque, irq->n, !level); | |
100 | } | |
101 | ||
102 | qemu_irq qemu_irq_invert(qemu_irq irq) | |
103 | { | |
cf0dbb21 PB |
104 | /* The default state for IRQs is low, so raise the output now. */ |
105 | qemu_irq_raise(irq); | |
f3c7d038 | 106 | return qemu_allocate_irq(qemu_notirq, irq, 0); |
b50a6563 | 107 | } |
9793212b PM |
108 | |
109 | static void qemu_splitirq(void *opaque, int line, int level) | |
110 | { | |
111 | struct IRQState **irq = opaque; | |
112 | irq[0]->handler(irq[0]->opaque, irq[0]->n, level); | |
113 | irq[1]->handler(irq[1]->opaque, irq[1]->n, level); | |
114 | } | |
115 | ||
116 | qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2) | |
117 | { | |
7267c094 | 118 | qemu_irq *s = g_malloc0(2 * sizeof(qemu_irq)); |
9793212b PM |
119 | s[0] = irq1; |
120 | s[1] = irq2; | |
f3c7d038 | 121 | return qemu_allocate_irq(qemu_splitirq, s, 0); |
9793212b | 122 | } |
22ec3283 AK |
123 | |
124 | static void proxy_irq_handler(void *opaque, int n, int level) | |
125 | { | |
126 | qemu_irq **target = opaque; | |
127 | ||
128 | if (*target) { | |
129 | qemu_set_irq((*target)[n], level); | |
130 | } | |
131 | } | |
132 | ||
133 | qemu_irq *qemu_irq_proxy(qemu_irq **target, int n) | |
134 | { | |
135 | return qemu_allocate_irqs(proxy_irq_handler, target, n); | |
136 | } | |
20288345 PB |
137 | |
138 | void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n) | |
139 | { | |
140 | int i; | |
141 | qemu_irq *old_irqs = qemu_allocate_irqs(NULL, NULL, n); | |
142 | for (i = 0; i < n; i++) { | |
143 | *old_irqs[i] = *gpio_in[i]; | |
144 | gpio_in[i]->handler = handler; | |
60a79016 | 145 | gpio_in[i]->opaque = &old_irqs[i]; |
20288345 PB |
146 | } |
147 | } | |
148 | ||
615c4895 AF |
149 | static const TypeInfo irq_type_info = { |
150 | .name = TYPE_IRQ, | |
151 | .parent = TYPE_OBJECT, | |
152 | .instance_size = sizeof(struct IRQState), | |
153 | }; | |
154 | ||
155 | static void irq_register_types(void) | |
156 | { | |
157 | type_register_static(&irq_type_info); | |
158 | } | |
159 | ||
160 | type_init(irq_register_types) |