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Commit | Line | Data |
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6af0bf9c FB |
1 | #if !defined (__MIPS_CPU_H__) |
2 | #define __MIPS_CPU_H__ | |
3 | ||
4ad40f36 FB |
4 | #define TARGET_HAS_ICE 1 |
5 | ||
9042c0e2 TS |
6 | #define ELF_MACHINE EM_MIPS |
7 | ||
c5d6edc3 | 8 | #include "config.h" |
6af0bf9c FB |
9 | #include "mips-defs.h" |
10 | #include "cpu-defs.h" | |
6af0bf9c FB |
11 | #include "softfloat.h" |
12 | ||
fdbb4691 FB |
13 | // uint_fast8_t and uint_fast16_t not in <sys/int_types.h> |
14 | // XXX: move that elsewhere | |
36bb244b | 15 | #if defined(HOST_SOLARIS) && HOST_SOLARIS < 10 |
fdbb4691 FB |
16 | typedef unsigned char uint_fast8_t; |
17 | typedef unsigned int uint_fast16_t; | |
18 | #endif | |
19 | ||
ead9360e | 20 | struct CPUMIPSState; |
6af0bf9c | 21 | |
29929e34 TS |
22 | typedef struct r4k_tlb_t r4k_tlb_t; |
23 | struct r4k_tlb_t { | |
6af0bf9c | 24 | target_ulong VPN; |
9c2149c8 | 25 | uint32_t PageMask; |
98c1b82b PB |
26 | uint_fast8_t ASID; |
27 | uint_fast16_t G:1; | |
28 | uint_fast16_t C0:3; | |
29 | uint_fast16_t C1:3; | |
30 | uint_fast16_t V0:1; | |
31 | uint_fast16_t V1:1; | |
32 | uint_fast16_t D0:1; | |
33 | uint_fast16_t D1:1; | |
6af0bf9c FB |
34 | target_ulong PFN[2]; |
35 | }; | |
6af0bf9c | 36 | |
ead9360e TS |
37 | typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; |
38 | struct CPUMIPSTLBContext { | |
39 | uint32_t nb_tlb; | |
40 | uint32_t tlb_in_use; | |
41 | int (*map_address) (struct CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type); | |
42 | void (*do_tlbwi) (void); | |
43 | void (*do_tlbwr) (void); | |
44 | void (*do_tlbp) (void); | |
45 | void (*do_tlbr) (void); | |
46 | union { | |
47 | struct { | |
48 | r4k_tlb_t tlb[MIPS_TLB_MAX]; | |
49 | } r4k; | |
50 | } mmu; | |
51 | }; | |
51b2772f | 52 | |
ead9360e TS |
53 | typedef union fpr_t fpr_t; |
54 | union fpr_t { | |
55 | float64 fd; /* ieee double precision */ | |
56 | float32 fs[2];/* ieee single precision */ | |
57 | uint64_t d; /* binary double fixed-point */ | |
58 | uint32_t w[2]; /* binary single fixed-point */ | |
59 | }; | |
60 | /* define FP_ENDIAN_IDX to access the same location | |
61 | * in the fpr_t union regardless of the host endianess | |
62 | */ | |
63 | #if defined(WORDS_BIGENDIAN) | |
64 | # define FP_ENDIAN_IDX 1 | |
65 | #else | |
66 | # define FP_ENDIAN_IDX 0 | |
c570fd16 | 67 | #endif |
ead9360e TS |
68 | |
69 | typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; | |
70 | struct CPUMIPSFPUContext { | |
6af0bf9c | 71 | /* Floating point registers */ |
f7cfb2a1 | 72 | fpr_t fpr[32]; |
6ea83fed | 73 | float_status fp_status; |
5a5012ec | 74 | /* fpu implementation/revision register (fir) */ |
6af0bf9c | 75 | uint32_t fcr0; |
5a5012ec TS |
76 | #define FCR0_F64 22 |
77 | #define FCR0_L 21 | |
78 | #define FCR0_W 20 | |
79 | #define FCR0_3D 19 | |
80 | #define FCR0_PS 18 | |
81 | #define FCR0_D 17 | |
82 | #define FCR0_S 16 | |
83 | #define FCR0_PRID 8 | |
84 | #define FCR0_REV 0 | |
6ea83fed FB |
85 | /* fcsr */ |
86 | uint32_t fcr31; | |
fd4a04eb TS |
87 | #define SET_FP_COND(num,env) do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
88 | #define CLEAR_FP_COND(num,env) do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) | |
89 | #define GET_FP_COND(env) ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1)) | |
5a5012ec TS |
90 | #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
91 | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) | |
92 | #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) | |
93 | #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) | |
94 | #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) | |
95 | #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) | |
96 | #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) | |
6ea83fed FB |
97 | #define FP_INEXACT 1 |
98 | #define FP_UNDERFLOW 2 | |
99 | #define FP_OVERFLOW 4 | |
100 | #define FP_DIV0 8 | |
101 | #define FP_INVALID 16 | |
102 | #define FP_UNIMPLEMENTED 32 | |
ead9360e TS |
103 | }; |
104 | ||
623a930e | 105 | #define NB_MMU_MODES 3 |
6ebbf390 | 106 | |
ead9360e TS |
107 | typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; |
108 | struct CPUMIPSMVPContext { | |
109 | int32_t CP0_MVPControl; | |
110 | #define CP0MVPCo_CPA 3 | |
111 | #define CP0MVPCo_STLB 2 | |
112 | #define CP0MVPCo_VPC 1 | |
113 | #define CP0MVPCo_EVP 0 | |
114 | int32_t CP0_MVPConf0; | |
115 | #define CP0MVPC0_M 31 | |
116 | #define CP0MVPC0_TLBS 29 | |
117 | #define CP0MVPC0_GS 28 | |
118 | #define CP0MVPC0_PCP 27 | |
119 | #define CP0MVPC0_PTLBE 16 | |
120 | #define CP0MVPC0_TCA 15 | |
121 | #define CP0MVPC0_PVPE 10 | |
122 | #define CP0MVPC0_PTC 0 | |
123 | int32_t CP0_MVPConf1; | |
124 | #define CP0MVPC1_CIM 31 | |
125 | #define CP0MVPC1_CIF 30 | |
126 | #define CP0MVPC1_PCX 20 | |
127 | #define CP0MVPC1_PCP2 10 | |
128 | #define CP0MVPC1_PCP1 0 | |
129 | }; | |
130 | ||
131 | typedef struct mips_def_t mips_def_t; | |
132 | ||
133 | #define MIPS_SHADOW_SET_MAX 16 | |
134 | #define MIPS_TC_MAX 5 | |
135 | #define MIPS_DSP_ACC 4 | |
136 | ||
137 | typedef struct CPUMIPSState CPUMIPSState; | |
138 | struct CPUMIPSState { | |
139 | /* General integer registers */ | |
d0dc7dc3 | 140 | target_ulong gpr[MIPS_SHADOW_SET_MAX][32]; |
ead9360e TS |
141 | /* Special registers */ |
142 | target_ulong PC[MIPS_TC_MAX]; | |
764dfc3f TS |
143 | /* temporary hack for FP globals */ |
144 | #ifndef USE_HOST_FLOAT_REGS | |
145 | fpr_t ft0; | |
146 | fpr_t ft1; | |
147 | fpr_t ft2; | |
ead9360e | 148 | #endif |
d0dc7dc3 TS |
149 | target_ulong HI[MIPS_TC_MAX][MIPS_DSP_ACC]; |
150 | target_ulong LO[MIPS_TC_MAX][MIPS_DSP_ACC]; | |
151 | target_ulong ACX[MIPS_TC_MAX][MIPS_DSP_ACC]; | |
ead9360e TS |
152 | target_ulong DSPControl[MIPS_TC_MAX]; |
153 | ||
154 | CPUMIPSMVPContext *mvp; | |
155 | CPUMIPSTLBContext *tlb; | |
156 | CPUMIPSFPUContext *fpu; | |
157 | uint32_t current_tc; | |
958fb4a9 | 158 | target_ulong *current_tc_gprs; |
893f9865 | 159 | target_ulong *current_tc_hi; |
36d23958 | 160 | |
e034e2c3 TS |
161 | uint32_t SEGBITS; |
162 | target_ulong SEGMask; | |
6d35524c TS |
163 | uint32_t PABITS; |
164 | target_ulong PAMask; | |
29929e34 | 165 | |
9c2149c8 | 166 | int32_t CP0_Index; |
ead9360e | 167 | /* CP0_MVP* are per MVP registers. */ |
9c2149c8 | 168 | int32_t CP0_Random; |
ead9360e TS |
169 | int32_t CP0_VPEControl; |
170 | #define CP0VPECo_YSI 21 | |
171 | #define CP0VPECo_GSI 20 | |
172 | #define CP0VPECo_EXCPT 16 | |
173 | #define CP0VPECo_TE 15 | |
174 | #define CP0VPECo_TargTC 0 | |
175 | int32_t CP0_VPEConf0; | |
176 | #define CP0VPEC0_M 31 | |
177 | #define CP0VPEC0_XTC 21 | |
178 | #define CP0VPEC0_TCS 19 | |
179 | #define CP0VPEC0_SCS 18 | |
180 | #define CP0VPEC0_DSC 17 | |
181 | #define CP0VPEC0_ICS 16 | |
182 | #define CP0VPEC0_MVP 1 | |
183 | #define CP0VPEC0_VPA 0 | |
184 | int32_t CP0_VPEConf1; | |
185 | #define CP0VPEC1_NCX 20 | |
186 | #define CP0VPEC1_NCP2 10 | |
187 | #define CP0VPEC1_NCP1 0 | |
188 | target_ulong CP0_YQMask; | |
189 | target_ulong CP0_VPESchedule; | |
190 | target_ulong CP0_VPEScheFBack; | |
191 | int32_t CP0_VPEOpt; | |
192 | #define CP0VPEOpt_IWX7 15 | |
193 | #define CP0VPEOpt_IWX6 14 | |
194 | #define CP0VPEOpt_IWX5 13 | |
195 | #define CP0VPEOpt_IWX4 12 | |
196 | #define CP0VPEOpt_IWX3 11 | |
197 | #define CP0VPEOpt_IWX2 10 | |
198 | #define CP0VPEOpt_IWX1 9 | |
199 | #define CP0VPEOpt_IWX0 8 | |
200 | #define CP0VPEOpt_DWX7 7 | |
201 | #define CP0VPEOpt_DWX6 6 | |
202 | #define CP0VPEOpt_DWX5 5 | |
203 | #define CP0VPEOpt_DWX4 4 | |
204 | #define CP0VPEOpt_DWX3 3 | |
205 | #define CP0VPEOpt_DWX2 2 | |
206 | #define CP0VPEOpt_DWX1 1 | |
207 | #define CP0VPEOpt_DWX0 0 | |
9c2149c8 | 208 | target_ulong CP0_EntryLo0; |
ead9360e TS |
209 | int32_t CP0_TCStatus[MIPS_TC_MAX]; |
210 | #define CP0TCSt_TCU3 31 | |
211 | #define CP0TCSt_TCU2 30 | |
212 | #define CP0TCSt_TCU1 29 | |
213 | #define CP0TCSt_TCU0 28 | |
214 | #define CP0TCSt_TMX 27 | |
215 | #define CP0TCSt_RNST 23 | |
216 | #define CP0TCSt_TDS 21 | |
217 | #define CP0TCSt_DT 20 | |
218 | #define CP0TCSt_DA 15 | |
219 | #define CP0TCSt_A 13 | |
220 | #define CP0TCSt_TKSU 11 | |
221 | #define CP0TCSt_IXMT 10 | |
222 | #define CP0TCSt_TASID 0 | |
223 | int32_t CP0_TCBind[MIPS_TC_MAX]; | |
224 | #define CP0TCBd_CurTC 21 | |
225 | #define CP0TCBd_TBE 17 | |
226 | #define CP0TCBd_CurVPE 0 | |
227 | target_ulong CP0_TCHalt[MIPS_TC_MAX]; | |
228 | target_ulong CP0_TCContext[MIPS_TC_MAX]; | |
229 | target_ulong CP0_TCSchedule[MIPS_TC_MAX]; | |
230 | target_ulong CP0_TCScheFBack[MIPS_TC_MAX]; | |
9c2149c8 TS |
231 | target_ulong CP0_EntryLo1; |
232 | target_ulong CP0_Context; | |
233 | int32_t CP0_PageMask; | |
234 | int32_t CP0_PageGrain; | |
235 | int32_t CP0_Wired; | |
ead9360e TS |
236 | int32_t CP0_SRSConf0_rw_bitmask; |
237 | int32_t CP0_SRSConf0; | |
238 | #define CP0SRSC0_M 31 | |
239 | #define CP0SRSC0_SRS3 20 | |
240 | #define CP0SRSC0_SRS2 10 | |
241 | #define CP0SRSC0_SRS1 0 | |
242 | int32_t CP0_SRSConf1_rw_bitmask; | |
243 | int32_t CP0_SRSConf1; | |
244 | #define CP0SRSC1_M 31 | |
245 | #define CP0SRSC1_SRS6 20 | |
246 | #define CP0SRSC1_SRS5 10 | |
247 | #define CP0SRSC1_SRS4 0 | |
248 | int32_t CP0_SRSConf2_rw_bitmask; | |
249 | int32_t CP0_SRSConf2; | |
250 | #define CP0SRSC2_M 31 | |
251 | #define CP0SRSC2_SRS9 20 | |
252 | #define CP0SRSC2_SRS8 10 | |
253 | #define CP0SRSC2_SRS7 0 | |
254 | int32_t CP0_SRSConf3_rw_bitmask; | |
255 | int32_t CP0_SRSConf3; | |
256 | #define CP0SRSC3_M 31 | |
257 | #define CP0SRSC3_SRS12 20 | |
258 | #define CP0SRSC3_SRS11 10 | |
259 | #define CP0SRSC3_SRS10 0 | |
260 | int32_t CP0_SRSConf4_rw_bitmask; | |
261 | int32_t CP0_SRSConf4; | |
262 | #define CP0SRSC4_SRS15 20 | |
263 | #define CP0SRSC4_SRS14 10 | |
264 | #define CP0SRSC4_SRS13 0 | |
9c2149c8 | 265 | int32_t CP0_HWREna; |
c570fd16 | 266 | target_ulong CP0_BadVAddr; |
9c2149c8 TS |
267 | int32_t CP0_Count; |
268 | target_ulong CP0_EntryHi; | |
269 | int32_t CP0_Compare; | |
270 | int32_t CP0_Status; | |
6af0bf9c FB |
271 | #define CP0St_CU3 31 |
272 | #define CP0St_CU2 30 | |
273 | #define CP0St_CU1 29 | |
274 | #define CP0St_CU0 28 | |
275 | #define CP0St_RP 27 | |
6ea83fed | 276 | #define CP0St_FR 26 |
6af0bf9c | 277 | #define CP0St_RE 25 |
7a387fff TS |
278 | #define CP0St_MX 24 |
279 | #define CP0St_PX 23 | |
6af0bf9c FB |
280 | #define CP0St_BEV 22 |
281 | #define CP0St_TS 21 | |
282 | #define CP0St_SR 20 | |
283 | #define CP0St_NMI 19 | |
284 | #define CP0St_IM 8 | |
7a387fff TS |
285 | #define CP0St_KX 7 |
286 | #define CP0St_SX 6 | |
287 | #define CP0St_UX 5 | |
623a930e | 288 | #define CP0St_KSU 3 |
6af0bf9c FB |
289 | #define CP0St_ERL 2 |
290 | #define CP0St_EXL 1 | |
291 | #define CP0St_IE 0 | |
9c2149c8 | 292 | int32_t CP0_IntCtl; |
ead9360e TS |
293 | #define CP0IntCtl_IPTI 29 |
294 | #define CP0IntCtl_IPPC1 26 | |
295 | #define CP0IntCtl_VS 5 | |
9c2149c8 | 296 | int32_t CP0_SRSCtl; |
ead9360e TS |
297 | #define CP0SRSCtl_HSS 26 |
298 | #define CP0SRSCtl_EICSS 18 | |
299 | #define CP0SRSCtl_ESS 12 | |
300 | #define CP0SRSCtl_PSS 6 | |
301 | #define CP0SRSCtl_CSS 0 | |
9c2149c8 | 302 | int32_t CP0_SRSMap; |
ead9360e TS |
303 | #define CP0SRSMap_SSV7 28 |
304 | #define CP0SRSMap_SSV6 24 | |
305 | #define CP0SRSMap_SSV5 20 | |
306 | #define CP0SRSMap_SSV4 16 | |
307 | #define CP0SRSMap_SSV3 12 | |
308 | #define CP0SRSMap_SSV2 8 | |
309 | #define CP0SRSMap_SSV1 4 | |
310 | #define CP0SRSMap_SSV0 0 | |
9c2149c8 | 311 | int32_t CP0_Cause; |
7a387fff TS |
312 | #define CP0Ca_BD 31 |
313 | #define CP0Ca_TI 30 | |
314 | #define CP0Ca_CE 28 | |
315 | #define CP0Ca_DC 27 | |
316 | #define CP0Ca_PCI 26 | |
6af0bf9c | 317 | #define CP0Ca_IV 23 |
7a387fff TS |
318 | #define CP0Ca_WP 22 |
319 | #define CP0Ca_IP 8 | |
4de9b249 | 320 | #define CP0Ca_IP_mask 0x0000FF00 |
7a387fff | 321 | #define CP0Ca_EC 2 |
c570fd16 | 322 | target_ulong CP0_EPC; |
9c2149c8 | 323 | int32_t CP0_PRid; |
b29a0341 | 324 | int32_t CP0_EBase; |
9c2149c8 | 325 | int32_t CP0_Config0; |
6af0bf9c FB |
326 | #define CP0C0_M 31 |
327 | #define CP0C0_K23 28 | |
328 | #define CP0C0_KU 25 | |
329 | #define CP0C0_MDU 20 | |
330 | #define CP0C0_MM 17 | |
331 | #define CP0C0_BM 16 | |
332 | #define CP0C0_BE 15 | |
333 | #define CP0C0_AT 13 | |
334 | #define CP0C0_AR 10 | |
335 | #define CP0C0_MT 7 | |
7a387fff | 336 | #define CP0C0_VI 3 |
6af0bf9c | 337 | #define CP0C0_K0 0 |
9c2149c8 | 338 | int32_t CP0_Config1; |
7a387fff | 339 | #define CP0C1_M 31 |
6af0bf9c FB |
340 | #define CP0C1_MMU 25 |
341 | #define CP0C1_IS 22 | |
342 | #define CP0C1_IL 19 | |
343 | #define CP0C1_IA 16 | |
344 | #define CP0C1_DS 13 | |
345 | #define CP0C1_DL 10 | |
346 | #define CP0C1_DA 7 | |
7a387fff TS |
347 | #define CP0C1_C2 6 |
348 | #define CP0C1_MD 5 | |
6af0bf9c FB |
349 | #define CP0C1_PC 4 |
350 | #define CP0C1_WR 3 | |
351 | #define CP0C1_CA 2 | |
352 | #define CP0C1_EP 1 | |
353 | #define CP0C1_FP 0 | |
9c2149c8 | 354 | int32_t CP0_Config2; |
7a387fff TS |
355 | #define CP0C2_M 31 |
356 | #define CP0C2_TU 28 | |
357 | #define CP0C2_TS 24 | |
358 | #define CP0C2_TL 20 | |
359 | #define CP0C2_TA 16 | |
360 | #define CP0C2_SU 12 | |
361 | #define CP0C2_SS 8 | |
362 | #define CP0C2_SL 4 | |
363 | #define CP0C2_SA 0 | |
9c2149c8 | 364 | int32_t CP0_Config3; |
7a387fff TS |
365 | #define CP0C3_M 31 |
366 | #define CP0C3_DSPP 10 | |
367 | #define CP0C3_LPA 7 | |
368 | #define CP0C3_VEIC 6 | |
369 | #define CP0C3_VInt 5 | |
370 | #define CP0C3_SP 4 | |
371 | #define CP0C3_MT 2 | |
372 | #define CP0C3_SM 1 | |
373 | #define CP0C3_TL 0 | |
e397ee33 TS |
374 | int32_t CP0_Config6; |
375 | int32_t CP0_Config7; | |
ead9360e | 376 | /* XXX: Maybe make LLAddr per-TC? */ |
c570fd16 | 377 | target_ulong CP0_LLAddr; |
fd88b6ab TS |
378 | target_ulong CP0_WatchLo[8]; |
379 | int32_t CP0_WatchHi[8]; | |
9c2149c8 TS |
380 | target_ulong CP0_XContext; |
381 | int32_t CP0_Framemask; | |
382 | int32_t CP0_Debug; | |
ead9360e | 383 | #define CP0DB_DBD 31 |
6af0bf9c FB |
384 | #define CP0DB_DM 30 |
385 | #define CP0DB_LSNM 28 | |
386 | #define CP0DB_Doze 27 | |
387 | #define CP0DB_Halt 26 | |
388 | #define CP0DB_CNT 25 | |
389 | #define CP0DB_IBEP 24 | |
390 | #define CP0DB_DBEP 21 | |
391 | #define CP0DB_IEXI 20 | |
392 | #define CP0DB_VER 15 | |
393 | #define CP0DB_DEC 10 | |
394 | #define CP0DB_SSt 8 | |
395 | #define CP0DB_DINT 5 | |
396 | #define CP0DB_DIB 4 | |
397 | #define CP0DB_DDBS 3 | |
398 | #define CP0DB_DDBL 2 | |
399 | #define CP0DB_DBp 1 | |
400 | #define CP0DB_DSS 0 | |
ead9360e | 401 | int32_t CP0_Debug_tcstatus[MIPS_TC_MAX]; |
c570fd16 | 402 | target_ulong CP0_DEPC; |
9c2149c8 TS |
403 | int32_t CP0_Performance0; |
404 | int32_t CP0_TagLo; | |
405 | int32_t CP0_DataLo; | |
406 | int32_t CP0_TagHi; | |
407 | int32_t CP0_DataHi; | |
c570fd16 | 408 | target_ulong CP0_ErrorEPC; |
9c2149c8 | 409 | int32_t CP0_DESAVE; |
6af0bf9c | 410 | /* Qemu */ |
6af0bf9c | 411 | int interrupt_request; |
6af0bf9c FB |
412 | int error_code; |
413 | int user_mode_only; /* user mode only simulation */ | |
414 | uint32_t hflags; /* CPU State */ | |
415 | /* TMASK defines different execution modes */ | |
b8aa4598 | 416 | #define MIPS_HFLAG_TMASK 0x01FF |
78749ba8 | 417 | #define MIPS_HFLAG_MODE 0x0007 /* execution modes */ |
623a930e TS |
418 | /* The KSU flags must be the lowest bits in hflags. The flag order |
419 | must be the same as defined for CP0 Status. This allows to use | |
420 | the bits as the value of mmu_idx. */ | |
421 | #define MIPS_HFLAG_KSU 0x0003 /* kernel/supervisor/user mode mask */ | |
422 | #define MIPS_HFLAG_UM 0x0002 /* user mode flag */ | |
423 | #define MIPS_HFLAG_SM 0x0001 /* supervisor mode flag */ | |
424 | #define MIPS_HFLAG_KM 0x0000 /* kernel mode flag */ | |
425 | #define MIPS_HFLAG_DM 0x0004 /* Debug mode */ | |
5e755519 | 426 | #define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */ |
387a8fe5 TS |
427 | #define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */ |
428 | #define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */ | |
429 | #define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */ | |
b8aa4598 TS |
430 | /* True if the MIPS IV COP1X instructions can be used. This also |
431 | controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S | |
432 | and RSQRT.D. */ | |
433 | #define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */ | |
434 | #define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */ | |
4ad40f36 FB |
435 | /* If translation is interrupted between the branch instruction and |
436 | * the delay slot, record what type of branch it is so that we can | |
437 | * resume translation properly. It might be possible to reduce | |
438 | * this from three bits to two. */ | |
b8aa4598 TS |
439 | #define MIPS_HFLAG_BMASK 0x0e00 |
440 | #define MIPS_HFLAG_B 0x0200 /* Unconditional branch */ | |
441 | #define MIPS_HFLAG_BC 0x0400 /* Conditional branch */ | |
442 | #define MIPS_HFLAG_BL 0x0600 /* Likely branch */ | |
443 | #define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */ | |
6af0bf9c FB |
444 | target_ulong btarget; /* Jump / branch target */ |
445 | int bcond; /* Branch condition (if needed) */ | |
a316d335 | 446 | |
7a387fff TS |
447 | int SYNCI_Step; /* Address step size for SYNCI */ |
448 | int CCRes; /* Cycle count resolution/divisor */ | |
ead9360e TS |
449 | uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ |
450 | uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ | |
e189e748 | 451 | int insn_flags; /* Supported instruction set */ |
7a387fff | 452 | |
33ac7f16 | 453 | #ifdef CONFIG_USER_ONLY |
6f5b89a0 TS |
454 | target_ulong tls_value; |
455 | #endif | |
456 | ||
a316d335 | 457 | CPU_COMMON |
6ae81775 | 458 | |
aaed909a | 459 | const mips_def_t *cpu_model; |
33ac7f16 TS |
460 | #ifndef CONFIG_USER_ONLY |
461 | void *irq[8]; | |
462 | #endif | |
51b2772f | 463 | |
6ae81775 | 464 | struct QEMUTimer *timer; /* Internal timer */ |
6af0bf9c FB |
465 | }; |
466 | ||
29929e34 TS |
467 | int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot, |
468 | target_ulong address, int rw, int access_type); | |
469 | int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot, | |
470 | target_ulong address, int rw, int access_type); | |
471 | int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot, | |
472 | target_ulong address, int rw, int access_type); | |
473 | void r4k_do_tlbwi (void); | |
474 | void r4k_do_tlbwr (void); | |
475 | void r4k_do_tlbp (void); | |
476 | void r4k_do_tlbr (void); | |
33d68b5f | 477 | void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
33d68b5f | 478 | |
647de6ca TS |
479 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
480 | int unused); | |
481 | ||
9467d44c TS |
482 | #define CPUState CPUMIPSState |
483 | #define cpu_init cpu_mips_init | |
484 | #define cpu_exec cpu_mips_exec | |
485 | #define cpu_gen_code cpu_mips_gen_code | |
486 | #define cpu_signal_handler cpu_mips_signal_handler | |
c732abe2 | 487 | #define cpu_list mips_cpu_list |
9467d44c | 488 | |
623a930e TS |
489 | /* MMU modes definitions. We carefully match the indices with our |
490 | hflags layout. */ | |
6ebbf390 | 491 | #define MMU_MODE0_SUFFIX _kernel |
623a930e TS |
492 | #define MMU_MODE1_SUFFIX _super |
493 | #define MMU_MODE2_SUFFIX _user | |
494 | #define MMU_USER_IDX 2 | |
6ebbf390 JM |
495 | static inline int cpu_mmu_index (CPUState *env) |
496 | { | |
623a930e | 497 | return env->hflags & MIPS_HFLAG_KSU; |
6ebbf390 JM |
498 | } |
499 | ||
6e68e076 PB |
500 | #if defined(CONFIG_USER_ONLY) |
501 | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) | |
502 | { | |
f8ed7070 | 503 | if (newsp) |
6e68e076 PB |
504 | env->gpr[env->current_tc][29] = newsp; |
505 | env->gpr[env->current_tc][7] = 0; | |
506 | env->gpr[env->current_tc][2] = 0; | |
507 | } | |
508 | #endif | |
509 | ||
6af0bf9c FB |
510 | #include "cpu-all.h" |
511 | ||
512 | /* Memory access type : | |
513 | * may be needed for precise access rights control and precise exceptions. | |
514 | */ | |
515 | enum { | |
516 | /* 1 bit to define user level / supervisor access */ | |
517 | ACCESS_USER = 0x00, | |
518 | ACCESS_SUPER = 0x01, | |
519 | /* 1 bit to indicate direction */ | |
520 | ACCESS_STORE = 0x02, | |
521 | /* Type of instruction that generated the access */ | |
522 | ACCESS_CODE = 0x10, /* Code fetch access */ | |
523 | ACCESS_INT = 0x20, /* Integer load/store access */ | |
524 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ | |
525 | }; | |
526 | ||
527 | /* Exceptions */ | |
528 | enum { | |
529 | EXCP_NONE = -1, | |
530 | EXCP_RESET = 0, | |
531 | EXCP_SRESET, | |
532 | EXCP_DSS, | |
533 | EXCP_DINT, | |
14e51cc7 TS |
534 | EXCP_DDBL, |
535 | EXCP_DDBS, | |
6af0bf9c FB |
536 | EXCP_NMI, |
537 | EXCP_MCHECK, | |
14e51cc7 | 538 | EXCP_EXT_INTERRUPT, /* 8 */ |
6af0bf9c | 539 | EXCP_DFWATCH, |
14e51cc7 | 540 | EXCP_DIB, |
6af0bf9c FB |
541 | EXCP_IWATCH, |
542 | EXCP_AdEL, | |
543 | EXCP_AdES, | |
544 | EXCP_TLBF, | |
545 | EXCP_IBE, | |
14e51cc7 | 546 | EXCP_DBp, /* 16 */ |
6af0bf9c | 547 | EXCP_SYSCALL, |
14e51cc7 | 548 | EXCP_BREAK, |
4ad40f36 | 549 | EXCP_CpU, |
6af0bf9c FB |
550 | EXCP_RI, |
551 | EXCP_OVERFLOW, | |
552 | EXCP_TRAP, | |
5a5012ec | 553 | EXCP_FPE, |
14e51cc7 | 554 | EXCP_DWATCH, /* 24 */ |
6af0bf9c FB |
555 | EXCP_LTLBL, |
556 | EXCP_TLBL, | |
557 | EXCP_TLBS, | |
558 | EXCP_DBE, | |
ead9360e | 559 | EXCP_THREAD, |
14e51cc7 TS |
560 | EXCP_MDMX, |
561 | EXCP_C2E, | |
562 | EXCP_CACHE, /* 32 */ | |
563 | ||
564 | EXCP_LAST = EXCP_CACHE, | |
6af0bf9c FB |
565 | }; |
566 | ||
6af0bf9c | 567 | int cpu_mips_exec(CPUMIPSState *s); |
aaed909a | 568 | CPUMIPSState *cpu_mips_init(const char *cpu_model); |
6af0bf9c | 569 | uint32_t cpu_mips_get_clock (void); |
388bb21a | 570 | int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); |
6af0bf9c FB |
571 | |
572 | #endif /* !defined (__MIPS_CPU_H__) */ |