[qemu.git] / hw / i82378.c

/*
 * QEMU Intel i82378 emulation (PCI to ISA bridge)
 *
 * Copyright (c) 2010-2011 Hervé Poussineau
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "pci/pci.h"
#include "pc.h"
#include "i8254.h"
#include "pcspk.h"

//#define DEBUG_I82378

#ifdef DEBUG_I82378
#define DPRINTF(fmt, ...) \
do { fprintf(stderr, "i82378: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) \
do {} while (0)
#endif

#define BADF(fmt, ...) \
do { fprintf(stderr, "i82378 ERROR: " fmt , ## __VA_ARGS__); } while (0)

typedef struct I82378State {
    qemu_irq out[2];
    qemu_irq *i8259;
    MemoryRegion io;
    MemoryRegion mem;
} I82378State;

typedef struct PCIi82378State {
    PCIDevice pci_dev;
    uint32_t isa_io_base;
    uint32_t isa_mem_base;
    I82378State state;
} PCIi82378State;

static const VMStateDescription vmstate_pci_i82378 = {
    .name = "pci-i82378",
    .version_id = 0,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(pci_dev, PCIi82378State),
        VMSTATE_END_OF_LIST()
    },
};

static void i82378_io_write(void *opaque, hwaddr addr,
                            uint64_t value, unsigned int size)
{
    switch (size) {
    case 1:
        DPRINTF("%s: " TARGET_FMT_plx "=%02" PRIx64 "\n", __func__,
                addr, value);
        cpu_outb(addr, value);
        break;
    case 2:
        DPRINTF("%s: " TARGET_FMT_plx "=%04" PRIx64 "\n", __func__,
                addr, value);
        cpu_outw(addr, value);
        break;
    case 4:
        DPRINTF("%s: " TARGET_FMT_plx "=%08" PRIx64 "\n", __func__,
                addr, value);
        cpu_outl(addr, value);
        break;
    default:
        abort();
    }
}

static uint64_t i82378_io_read(void *opaque, hwaddr addr,
                               unsigned int size)
{
    DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
    switch (size) {
    case 1:
        return cpu_inb(addr);
    case 2:
        return cpu_inw(addr);
    case 4:
        return cpu_inl(addr);
    default:
        abort();
    }
}

static const MemoryRegionOps i82378_io_ops = {
    .read = i82378_io_read,
    .write = i82378_io_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void i82378_mem_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned int size)
{
    switch (size) {
    case 1:
        DPRINTF("%s: " TARGET_FMT_plx "=%02" PRIx64 "\n", __func__,
                addr, value);
        cpu_outb(addr, value);
        break;
    case 2:
        DPRINTF("%s: " TARGET_FMT_plx "=%04" PRIx64 "\n", __func__,
                addr, value);
        cpu_outw(addr, value);
        break;
    case 4:
        DPRINTF("%s: " TARGET_FMT_plx "=%08" PRIx64 "\n", __func__,
                addr, value);
        cpu_outl(addr, value);
        break;
    default:
        abort();
    }
}

static uint64_t i82378_mem_read(void *opaque, hwaddr addr,
                                unsigned int size)
{
    DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
    switch (size) {
    case 1:
        return cpu_inb(addr);
    case 2:
        return cpu_inw(addr);
    case 4:
        return cpu_inl(addr);
    default:
        abort();
    }
}

static const MemoryRegionOps i82378_mem_ops = {
    .read = i82378_mem_read,
    .write = i82378_mem_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void i82378_request_out0_irq(void *opaque, int irq, int level)
{
    I82378State *s = opaque;
    qemu_set_irq(s->out[0], level);
}

static void i82378_request_pic_irq(void *opaque, int irq, int level)
{
    DeviceState *dev = opaque;
    PCIDevice *pci = DO_UPCAST(PCIDevice, qdev, dev);
    PCIi82378State *s = DO_UPCAST(PCIi82378State, pci_dev, pci);

    qemu_set_irq(s->state.i8259[irq], level);
}

static void i82378_init(DeviceState *dev, I82378State *s)
{
    ISABus *isabus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(dev, "isa.0"));
    ISADevice *pit;
    ISADevice *isa;
    qemu_irq *out0_irq;

    /* This device has:
       2 82C59 (irq)
       1 82C54 (pit)
       2 82C37 (dma)
       NMI
       Utility Bus Support Registers

       All devices accept byte access only, except timer
     */

    qdev_init_gpio_out(dev, s->out, 2);
    qdev_init_gpio_in(dev, i82378_request_pic_irq, 16);

    /* Workaround the fact that i8259 is not qdev'ified... */
    out0_irq = qemu_allocate_irqs(i82378_request_out0_irq, s, 1);

    /* 2 82C59 (irq) */
    s->i8259 = i8259_init(isabus, *out0_irq);
    isa_bus_irqs(isabus, s->i8259);

    /* 1 82C54 (pit) */
    pit = pit_init(isabus, 0x40, 0, NULL);

    /* speaker */
    pcspk_init(isabus, pit);

    /* 2 82C37 (dma) */
    isa = isa_create_simple(isabus, "i82374");
    qdev_connect_gpio_out(&isa->qdev, 0, s->out[1]);

    /* timer */
    isa_create_simple(isabus, "mc146818rtc");
}

static int pci_i82378_init(PCIDevice *dev)
{
    PCIi82378State *pci = DO_UPCAST(PCIi82378State, pci_dev, dev);
    I82378State *s = &pci->state;
    uint8_t *pci_conf;

    pci_conf = dev->config;
    pci_set_word(pci_conf + PCI_COMMAND,
                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
    pci_set_word(pci_conf + PCI_STATUS,
                 PCI_STATUS_DEVSEL_MEDIUM);

    pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */

    memory_region_init_io(&s->io, &i82378_io_ops, s, "i82378-io", 0x00010000);
    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io);

    memory_region_init_io(&s->mem, &i82378_mem_ops, s, "i82378-mem", 0x01000000);
    pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);

    /* Make I/O address read only */
    pci_set_word(dev->wmask + PCI_COMMAND, PCI_COMMAND_SPECIAL);
    pci_set_long(dev->wmask + PCI_BASE_ADDRESS_0, 0);
    pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, pci->isa_io_base);

    isa_mem_base = pci->isa_mem_base;
    isa_bus_new(&dev->qdev, pci_address_space_io(dev));

    i82378_init(&dev->qdev, s);

    return 0;
}

static Property i82378_properties[] = {
    DEFINE_PROP_HEX32("iobase", PCIi82378State, isa_io_base, 0x80000000),
    DEFINE_PROP_HEX32("membase", PCIi82378State, isa_mem_base, 0xc0000000),
    DEFINE_PROP_END_OF_LIST()
};

static void pci_i82378_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->init = pci_i82378_init;
    k->vendor_id = PCI_VENDOR_ID_INTEL;
    k->device_id = PCI_DEVICE_ID_INTEL_82378;
    k->revision = 0x03;
    k->class_id = PCI_CLASS_BRIDGE_ISA;
    k->subsystem_vendor_id = 0x0;
    k->subsystem_id = 0x0;
    dc->vmsd = &vmstate_pci_i82378;
    dc->props = i82378_properties;
}

static TypeInfo pci_i82378_info = {
    .name = "i82378",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIi82378State),
    .class_init = pci_i82378_class_init,
};

static void i82378_register_types(void)
{
    type_register_static(&pci_i82378_info);
}

type_init(i82378_register_types)
Commit	Line	Data
a04ff940 AF	1	/*
	2	* QEMU Intel i82378 emulation (PCI to ISA bridge)
	3	*
	4	* Copyright (c) 2010-2011 Hervé Poussineau
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
a2cb15b0	20	#include "pci/pci.h"
a04ff940	21	#include "pc.h"
b1277b03	22	#include "i8254.h"
302fe51b	23	#include "pcspk.h"
a04ff940 AF	24
	25	//#define DEBUG_I82378
	26
	27	#ifdef DEBUG_I82378
	28	#define DPRINTF(fmt, ...) \
	29	do { fprintf(stderr, "i82378: " fmt , ## __VA_ARGS__); } while (0)
	30	#else
	31	#define DPRINTF(fmt, ...) \
	32	do {} while (0)
	33	#endif
	34
	35	#define BADF(fmt, ...) \
	36	do { fprintf(stderr, "i82378 ERROR: " fmt , ## __VA_ARGS__); } while (0)
	37
	38	typedef struct I82378State {
	39	qemu_irq out[2];
	40	qemu_irq *i8259;
	41	MemoryRegion io;
	42	MemoryRegion mem;
	43	} I82378State;
	44
	45	typedef struct PCIi82378State {
	46	PCIDevice pci_dev;
	47	uint32_t isa_io_base;
	48	uint32_t isa_mem_base;
	49	I82378State state;
	50	} PCIi82378State;
	51
	52	static const VMStateDescription vmstate_pci_i82378 = {
	53	.name = "pci-i82378",
	54	.version_id = 0,
	55	.minimum_version_id = 0,
	56	.fields = (VMStateField[]) {
	57	VMSTATE_PCI_DEVICE(pci_dev, PCIi82378State),
	58	VMSTATE_END_OF_LIST()
	59	},
	60	};
	61
a8170e5e	62	static void i82378_io_write(void *opaque, hwaddr addr,
a04ff940 AF	63	uint64_t value, unsigned int size)
	64	{
	65	switch (size) {
	66	case 1:
	67	DPRINTF("%s: " TARGET_FMT_plx "=%02" PRIx64 "\n", __func__,
	68	addr, value);
	69	cpu_outb(addr, value);
	70	break;
	71	case 2:
	72	DPRINTF("%s: " TARGET_FMT_plx "=%04" PRIx64 "\n", __func__,
	73	addr, value);
	74	cpu_outw(addr, value);
	75	break;
	76	case 4:
	77	DPRINTF("%s: " TARGET_FMT_plx "=%08" PRIx64 "\n", __func__,
	78	addr, value);
	79	cpu_outl(addr, value);
	80	break;
	81	default:
	82	abort();
	83	}
	84	}
	85
a8170e5e	86	static uint64_t i82378_io_read(void *opaque, hwaddr addr,
a04ff940 AF	87	unsigned int size)
	88	{
	89	DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
	90	switch (size) {
	91	case 1:
	92	return cpu_inb(addr);
	93	case 2:
	94	return cpu_inw(addr);
	95	case 4:
	96	return cpu_inl(addr);
	97	default:
	98	abort();
	99	}
	100	}
	101
	102	static const MemoryRegionOps i82378_io_ops = {
	103	.read = i82378_io_read,
	104	.write = i82378_io_write,
	105	.endianness = DEVICE_LITTLE_ENDIAN,
	106	};
	107
a8170e5e	108	static void i82378_mem_write(void *opaque, hwaddr addr,
a04ff940 AF	109	uint64_t value, unsigned int size)
	110	{
	111	switch (size) {
	112	case 1:
	113	DPRINTF("%s: " TARGET_FMT_plx "=%02" PRIx64 "\n", __func__,
	114	addr, value);
	115	cpu_outb(addr, value);
	116	break;
	117	case 2:
	118	DPRINTF("%s: " TARGET_FMT_plx "=%04" PRIx64 "\n", __func__,
	119	addr, value);
	120	cpu_outw(addr, value);
	121	break;
	122	case 4:
	123	DPRINTF("%s: " TARGET_FMT_plx "=%08" PRIx64 "\n", __func__,
	124	addr, value);
	125	cpu_outl(addr, value);
	126	break;
	127	default:
	128	abort();
	129	}
	130	}
	131
a8170e5e	132	static uint64_t i82378_mem_read(void *opaque, hwaddr addr,
a04ff940 AF	133	unsigned int size)
	134	{
	135	DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
	136	switch (size) {
	137	case 1:
	138	return cpu_inb(addr);
	139	case 2:
	140	return cpu_inw(addr);
	141	case 4:
	142	return cpu_inl(addr);
	143	default:
	144	abort();
	145	}
	146	}
	147
	148	static const MemoryRegionOps i82378_mem_ops = {
	149	.read = i82378_mem_read,
	150	.write = i82378_mem_write,
	151	.endianness = DEVICE_LITTLE_ENDIAN,
	152	};
	153
	154	static void i82378_request_out0_irq(void *opaque, int irq, int level)
	155	{
	156	I82378State *s = opaque;
	157	qemu_set_irq(s->out[0], level);
	158	}
	159
	160	static void i82378_request_pic_irq(void *opaque, int irq, int level)
	161	{
	162	DeviceState *dev = opaque;
	163	PCIDevice *pci = DO_UPCAST(PCIDevice, qdev, dev);
	164	PCIi82378State *s = DO_UPCAST(PCIi82378State, pci_dev, pci);
	165
	166	qemu_set_irq(s->state.i8259[irq], level);
	167	}
	168
	169	static void i82378_init(DeviceState dev, I82378State s)
	170	{
	171	ISABus *isabus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(dev, "isa.0"));
	172	ISADevice *pit;
049a9f7b	173	ISADevice *isa;
a04ff940 AF	174	qemu_irq *out0_irq;
	175
	176	/* This device has:
	177	2 82C59 (irq)
	178	1 82C54 (pit)
	179	2 82C37 (dma)
	180	NMI
	181	Utility Bus Support Registers
	182
	183	All devices accept byte access only, except timer
	184	*/
	185
	186	qdev_init_gpio_out(dev, s->out, 2);
	187	qdev_init_gpio_in(dev, i82378_request_pic_irq, 16);
	188
	189	/* Workaround the fact that i8259 is not qdev'ified... */
	190	out0_irq = qemu_allocate_irqs(i82378_request_out0_irq, s, 1);
	191
	192	/* 2 82C59 (irq) */
	193	s->i8259 = i8259_init(isabus, *out0_irq);
	194	isa_bus_irqs(isabus, s->i8259);
	195
	196	/* 1 82C54 (pit) */
319ba9f5	197	pit = pit_init(isabus, 0x40, 0, NULL);
a04ff940 AF	198
a04ff940 AF	199	/* speaker */
302fe51b	200	pcspk_init(isabus, pit);
a04ff940 AF	201
a04ff940 AF	202	/* 2 82C37 (dma) */
049a9f7b HP	203	isa = isa_create_simple(isabus, "i82374");
049a9f7b HP	204	qdev_connect_gpio_out(&isa->qdev, 0, s->out[1]);
a04ff940 AF	205
	206	/* timer */
	207	isa_create_simple(isabus, "mc146818rtc");
	208	}
	209
	210	static int pci_i82378_init(PCIDevice *dev)
	211	{
	212	PCIi82378State *pci = DO_UPCAST(PCIi82378State, pci_dev, dev);
	213	I82378State *s = &pci->state;
	214	uint8_t *pci_conf;
	215
	216	pci_conf = dev->config;
	217	pci_set_word(pci_conf + PCI_COMMAND,
	218	PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
	219	pci_set_word(pci_conf + PCI_STATUS,
	220	PCI_STATUS_DEVSEL_MEDIUM);
	221
	222	pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
	223
	224	memory_region_init_io(&s->io, &i82378_io_ops, s, "i82378-io", 0x00010000);
	225	pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io);
	226
	227	memory_region_init_io(&s->mem, &i82378_mem_ops, s, "i82378-mem", 0x01000000);
a04ff940 AF	228	pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
	229
	230	/* Make I/O address read only */
	231	pci_set_word(dev->wmask + PCI_COMMAND, PCI_COMMAND_SPECIAL);
	232	pci_set_long(dev->wmask + PCI_BASE_ADDRESS_0, 0);
	233	pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, pci->isa_io_base);
	234
	235	isa_mem_base = pci->isa_mem_base;
	236	isa_bus_new(&dev->qdev, pci_address_space_io(dev));
	237
	238	i82378_init(&dev->qdev, s);
	239
	240	return 0;
	241	}
	242
39bffca2 AL	243	static Property i82378_properties[] = {
	244	DEFINE_PROP_HEX32("iobase", PCIi82378State, isa_io_base, 0x80000000),
	245	DEFINE_PROP_HEX32("membase", PCIi82378State, isa_mem_base, 0xc0000000),
	246	DEFINE_PROP_END_OF_LIST()
	247	};
	248
40021f08 AL	249	static void pci_i82378_class_init(ObjectClass klass, void data)
	250	{
	251	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
39bffca2	252	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	253
	254	k->init = pci_i82378_init;
	255	k->vendor_id = PCI_VENDOR_ID_INTEL;
	256	k->device_id = PCI_DEVICE_ID_INTEL_82378;
	257	k->revision = 0x03;
	258	k->class_id = PCI_CLASS_BRIDGE_ISA;
	259	k->subsystem_vendor_id = 0x0;
	260	k->subsystem_id = 0x0;
39bffca2 AL	261	dc->vmsd = &vmstate_pci_i82378;
39bffca2 AL	262	dc->props = i82378_properties;
40021f08 AL	263	}
40021f08 AL	264
39bffca2	265	static TypeInfo pci_i82378_info = {
40021f08	266	.name = "i82378",
39bffca2 AL	267	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	268	.instance_size = sizeof(PCIi82378State),
40021f08	269	.class_init = pci_i82378_class_init,
a04ff940 AF	270	};
a04ff940 AF	271
83f7d43a	272	static void i82378_register_types(void)
a04ff940	273	{
39bffca2	274	type_register_static(&pci_i82378_info);
a04ff940 AF	275	}
a04ff940 AF	276
83f7d43a	277	type_init(i82378_register_types)