[qemu.git] / hw / sd / omap_mmc.c

/*
 * OMAP on-chip MMC/SD host emulation.
 *
 * Copyright (C) 2006-2007 Andrzej Zaborowski  <[email protected]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 or
 * (at your option) version 3 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */
#include "hw/hw.h"
#include "hw/arm/omap.h"
#include "hw/sd.h"

struct omap_mmc_s {
    qemu_irq irq;
    qemu_irq *dma;
    qemu_irq coverswitch;
    MemoryRegion iomem;
    omap_clk clk;
    SDState *card;
    uint16_t last_cmd;
    uint16_t sdio;
    uint16_t rsp[8];
    uint32_t arg;
    int lines;
    int dw;
    int mode;
    int enable;
    int be;
    int rev;
    uint16_t status;
    uint16_t mask;
    uint8_t cto;
    uint16_t dto;
    int clkdiv;
    uint16_t fifo[32];
    int fifo_start;
    int fifo_len;
    uint16_t blen;
    uint16_t blen_counter;
    uint16_t nblk;
    uint16_t nblk_counter;
    int tx_dma;
    int rx_dma;
    int af_level;
    int ae_level;

    int ddir;
    int transfer;

    int cdet_wakeup;
    int cdet_enable;
    int cdet_state;
    qemu_irq cdet;
};

static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
{
    qemu_set_irq(s->irq, !!(s->status & s->mask));
}

static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
{
    if (!host->transfer && !host->fifo_len) {
        host->status &= 0xf3ff;
        return;
    }

    if (host->fifo_len > host->af_level && host->ddir) {
        if (host->rx_dma) {
            host->status &= 0xfbff;
            qemu_irq_raise(host->dma[1]);
        } else
            host->status |= 0x0400;
    } else {
        host->status &= 0xfbff;
        qemu_irq_lower(host->dma[1]);
    }

    if (host->fifo_len < host->ae_level && !host->ddir) {
        if (host->tx_dma) {
            host->status &= 0xf7ff;
            qemu_irq_raise(host->dma[0]);
        } else
            host->status |= 0x0800;
    } else {
        qemu_irq_lower(host->dma[0]);
        host->status &= 0xf7ff;
    }
}

typedef enum {
    sd_nore = 0,	/* no response */
    sd_r1,		/* normal response command */
    sd_r2,		/* CID, CSD registers */
    sd_r3,		/* OCR register */
    sd_r6 = 6,		/* Published RCA response */
    sd_r1b = -1,
} sd_rsp_type_t;

static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
                sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
{
    uint32_t rspstatus, mask;
    int rsplen, timeout;
    SDRequest request;
    uint8_t response[16];

    if (init && cmd == 0) {
        host->status |= 0x0001;
        return;
    }

    if (resptype == sd_r1 && busy)
        resptype = sd_r1b;

    if (type == sd_adtc) {
        host->fifo_start = 0;
        host->fifo_len = 0;
        host->transfer = 1;
        host->ddir = dir;
    } else
        host->transfer = 0;
    timeout = 0;
    mask = 0;
    rspstatus = 0;

    request.cmd = cmd;
    request.arg = host->arg;
    request.crc = 0; /* FIXME */

    rsplen = sd_do_command(host->card, &request, response);

    /* TODO: validate CRCs */
    switch (resptype) {
    case sd_nore:
        rsplen = 0;
        break;

    case sd_r1:
    case sd_r1b:
        if (rsplen < 4) {
            timeout = 1;
            break;
        }
        rsplen = 4;

        mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR |
                ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION |
                LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND |
                CARD_ECC_FAILED | CC_ERROR | SD_ERROR |
                CID_CSD_OVERWRITE;
        if (host->sdio & (1 << 13))
            mask |= AKE_SEQ_ERROR;
        rspstatus = (response[0] << 24) | (response[1] << 16) |
                (response[2] << 8) | (response[3] << 0);
        break;

    case sd_r2:
        if (rsplen < 16) {
            timeout = 1;
            break;
        }
        rsplen = 16;
        break;

    case sd_r3:
        if (rsplen < 4) {
            timeout = 1;
            break;
        }
        rsplen = 4;

        rspstatus = (response[0] << 24) | (response[1] << 16) |
                (response[2] << 8) | (response[3] << 0);
        if (rspstatus & 0x80000000)
            host->status &= 0xe000;
        else
            host->status |= 0x1000;
        break;

    case sd_r6:
        if (rsplen < 4) {
            timeout = 1;
            break;
        }
        rsplen = 4;

        mask = 0xe000 | AKE_SEQ_ERROR;
        rspstatus = (response[2] << 8) | (response[3] << 0);
    }

    if (rspstatus & mask)
        host->status |= 0x4000;
    else
        host->status &= 0xb000;

    if (rsplen)
        for (rsplen = 0; rsplen < 8; rsplen ++)
            host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] |
                    (response[(rsplen << 1) | 0] << 8);

    if (timeout)
        host->status |= 0x0080;
    else if (cmd == 12)
        host->status |= 0x0005;	/* Makes it more real */
    else
        host->status |= 0x0001;
}

static void omap_mmc_transfer(struct omap_mmc_s *host)
{
    uint8_t value;

    if (!host->transfer)
        return;

    while (1) {
        if (host->ddir) {
            if (host->fifo_len > host->af_level)
                break;

            value = sd_read_data(host->card);
            host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
            if (-- host->blen_counter) {
                value = sd_read_data(host->card);
                host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
                        value << 8;
                host->blen_counter --;
            }

            host->fifo_len ++;
        } else {
            if (!host->fifo_len)
                break;

            value = host->fifo[host->fifo_start] & 0xff;
            sd_write_data(host->card, value);
            if (-- host->blen_counter) {
                value = host->fifo[host->fifo_start] >> 8;
                sd_write_data(host->card, value);
                host->blen_counter --;
            }

            host->fifo_start ++;
            host->fifo_len --;
            host->fifo_start &= 31;
        }

        if (host->blen_counter == 0) {
            host->nblk_counter --;
            host->blen_counter = host->blen;

            if (host->nblk_counter == 0) {
                host->nblk_counter = host->nblk;
                host->transfer = 0;
                host->status |= 0x0008;
                break;
            }
        }
    }
}

static void omap_mmc_update(void *opaque)
{
    struct omap_mmc_s *s = opaque;
    omap_mmc_transfer(s);
    omap_mmc_fifolevel_update(s);
    omap_mmc_interrupts_update(s);
}

void omap_mmc_reset(struct omap_mmc_s *host)
{
    host->last_cmd = 0;
    memset(host->rsp, 0, sizeof(host->rsp));
    host->arg = 0;
    host->dw = 0;
    host->mode = 0;
    host->enable = 0;
    host->status = 0;
    host->mask = 0;
    host->cto = 0;
    host->dto = 0;
    host->fifo_len = 0;
    host->blen = 0;
    host->blen_counter = 0;
    host->nblk = 0;
    host->nblk_counter = 0;
    host->tx_dma = 0;
    host->rx_dma = 0;
    host->ae_level = 0x00;
    host->af_level = 0x1f;
    host->transfer = 0;
    host->cdet_wakeup = 0;
    host->cdet_enable = 0;
    qemu_set_irq(host->coverswitch, host->cdet_state);
    host->clkdiv = 0;
}

static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
                              unsigned size)
{
    uint16_t i;
    struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;

    if (size != 2) {
        return omap_badwidth_read16(opaque, offset);
    }

    switch (offset) {
    case 0x00:	/* MMC_CMD */
        return s->last_cmd;

    case 0x04:	/* MMC_ARGL */
        return s->arg & 0x0000ffff;

    case 0x08:	/* MMC_ARGH */
        return s->arg >> 16;

    case 0x0c:	/* MMC_CON */
        return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) | 
                (s->be << 10) | s->clkdiv;

    case 0x10:	/* MMC_STAT */
        return s->status;

    case 0x14:	/* MMC_IE */
        return s->mask;

    case 0x18:	/* MMC_CTO */
        return s->cto;

    case 0x1c:	/* MMC_DTO */
        return s->dto;

    case 0x20:	/* MMC_DATA */
        /* TODO: support 8-bit access */
        i = s->fifo[s->fifo_start];
        if (s->fifo_len == 0) {
            printf("MMC: FIFO underrun\n");
            return i;
        }
        s->fifo_start ++;
        s->fifo_len --;
        s->fifo_start &= 31;
        omap_mmc_transfer(s);
        omap_mmc_fifolevel_update(s);
        omap_mmc_interrupts_update(s);
        return i;

    case 0x24:	/* MMC_BLEN */
        return s->blen_counter;

    case 0x28:	/* MMC_NBLK */
        return s->nblk_counter;

    case 0x2c:	/* MMC_BUF */
        return (s->rx_dma << 15) | (s->af_level << 8) |
            (s->tx_dma << 7) | s->ae_level;

    case 0x30:	/* MMC_SPI */
        return 0x0000;
    case 0x34:	/* MMC_SDIO */
        return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio;
    case 0x38:	/* MMC_SYST */
        return 0x0000;

    case 0x3c:	/* MMC_REV */
        return s->rev;

    case 0x40:	/* MMC_RSP0 */
    case 0x44:	/* MMC_RSP1 */
    case 0x48:	/* MMC_RSP2 */
    case 0x4c:	/* MMC_RSP3 */
    case 0x50:	/* MMC_RSP4 */
    case 0x54:	/* MMC_RSP5 */
    case 0x58:	/* MMC_RSP6 */
    case 0x5c:	/* MMC_RSP7 */
        return s->rsp[(offset - 0x40) >> 2];

    /* OMAP2-specific */
    case 0x60:	/* MMC_IOSR */
    case 0x64:	/* MMC_SYSC */
        return 0;
    case 0x68:	/* MMC_SYSS */
        return 1;						/* RSTD */
    }

    OMAP_BAD_REG(offset);
    return 0;
}

static void omap_mmc_write(void *opaque, hwaddr offset,
                           uint64_t value, unsigned size)
{
    int i;
    struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;

    if (size != 2) {
        omap_badwidth_write16(opaque, offset, value);
        return;
    }

    switch (offset) {
    case 0x00:	/* MMC_CMD */
        if (!s->enable)
            break;

        s->last_cmd = value;
        for (i = 0; i < 8; i ++)
            s->rsp[i] = 0x0000;
        omap_mmc_command(s, value & 63, (value >> 15) & 1,
                (sd_cmd_type_t) ((value >> 12) & 3),
                (value >> 11) & 1,
                (sd_rsp_type_t) ((value >> 8) & 7),
                (value >> 7) & 1);
        omap_mmc_update(s);
        break;

    case 0x04:	/* MMC_ARGL */
        s->arg &= 0xffff0000;
        s->arg |= 0x0000ffff & value;
        break;

    case 0x08:	/* MMC_ARGH */
        s->arg &= 0x0000ffff;
        s->arg |= value << 16;
        break;

    case 0x0c:	/* MMC_CON */
        s->dw = (value >> 15) & 1;
        s->mode = (value >> 12) & 3;
        s->enable = (value >> 11) & 1;
        s->be = (value >> 10) & 1;
        s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff);
        if (s->mode != 0)
            printf("SD mode %i unimplemented!\n", s->mode);
        if (s->be != 0)
            printf("SD FIFO byte sex unimplemented!\n");
        if (s->dw != 0 && s->lines < 4)
            printf("4-bit SD bus enabled\n");
        if (!s->enable)
            omap_mmc_reset(s);
        break;

    case 0x10:	/* MMC_STAT */
        s->status &= ~value;
        omap_mmc_interrupts_update(s);
        break;

    case 0x14:	/* MMC_IE */
        s->mask = value & 0x7fff;
        omap_mmc_interrupts_update(s);
        break;

    case 0x18:	/* MMC_CTO */
        s->cto = value & 0xff;
        if (s->cto > 0xfd && s->rev <= 1)
            printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
        break;

    case 0x1c:	/* MMC_DTO */
        s->dto = value & 0xffff;
        break;

    case 0x20:	/* MMC_DATA */
        /* TODO: support 8-bit access */
        if (s->fifo_len == 32)
            break;
        s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
        s->fifo_len ++;
        omap_mmc_transfer(s);
        omap_mmc_fifolevel_update(s);
        omap_mmc_interrupts_update(s);
        break;

    case 0x24:	/* MMC_BLEN */
        s->blen = (value & 0x07ff) + 1;
        s->blen_counter = s->blen;
        break;

    case 0x28:	/* MMC_NBLK */
        s->nblk = (value & 0x07ff) + 1;
        s->nblk_counter = s->nblk;
        s->blen_counter = s->blen;
        break;

    case 0x2c:	/* MMC_BUF */
        s->rx_dma = (value >> 15) & 1;
        s->af_level = (value >> 8) & 0x1f;
        s->tx_dma = (value >> 7) & 1;
        s->ae_level = value & 0x1f;

        if (s->rx_dma)
            s->status &= 0xfbff;
        if (s->tx_dma)
            s->status &= 0xf7ff;
        omap_mmc_fifolevel_update(s);
        omap_mmc_interrupts_update(s);
        break;

    /* SPI, SDIO and TEST modes unimplemented */
    case 0x30:	/* MMC_SPI (OMAP1 only) */
        break;
    case 0x34:	/* MMC_SDIO */
        s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020);
        s->cdet_wakeup = (value >> 9) & 1;
        s->cdet_enable = (value >> 2) & 1;
        break;
    case 0x38:	/* MMC_SYST */
        break;

    case 0x3c:	/* MMC_REV */
    case 0x40:	/* MMC_RSP0 */
    case 0x44:	/* MMC_RSP1 */
    case 0x48:	/* MMC_RSP2 */
    case 0x4c:	/* MMC_RSP3 */
    case 0x50:	/* MMC_RSP4 */
    case 0x54:	/* MMC_RSP5 */
    case 0x58:	/* MMC_RSP6 */
    case 0x5c:	/* MMC_RSP7 */
        OMAP_RO_REG(offset);
        break;

    /* OMAP2-specific */
    case 0x60:	/* MMC_IOSR */
        if (value & 0xf)
            printf("MMC: SDIO bits used!\n");
        break;
    case 0x64:	/* MMC_SYSC */
        if (value & (1 << 2))					/* SRTS */
            omap_mmc_reset(s);
        break;
    case 0x68:	/* MMC_SYSS */
        OMAP_RO_REG(offset);
        break;

    default:
        OMAP_BAD_REG(offset);
    }
}

static const MemoryRegionOps omap_mmc_ops = {
    .read = omap_mmc_read,
    .write = omap_mmc_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void omap_mmc_cover_cb(void *opaque, int line, int level)
{
    struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;

    if (!host->cdet_state && level) {
        host->status |= 0x0002;
        omap_mmc_interrupts_update(host);
        if (host->cdet_wakeup) {
            /* TODO: Assert wake-up */
        }
    }

    if (host->cdet_state != level) {
        qemu_set_irq(host->coverswitch, level);
        host->cdet_state = level;
    }
}

struct omap_mmc_s *omap_mmc_init(hwaddr base,
                MemoryRegion *sysmem,
                BlockBackend *blk,
                qemu_irq irq, qemu_irq dma[], omap_clk clk)
{
    struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);

    s->irq = irq;
    s->dma = dma;
    s->clk = clk;
    s->lines = 1;	/* TODO: needs to be settable per-board */
    s->rev = 1;

    omap_mmc_reset(s);

    memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800);
    memory_region_add_subregion(sysmem, base, &s->iomem);

    /* Instantiate the storage */
    s->card = sd_init(blk, false);
    if (s->card == NULL) {
        exit(1);
    }

    return s;
}

struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
                BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
                omap_clk fclk, omap_clk iclk)
{
    struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);

    s->irq = irq;
    s->dma = dma;
    s->clk = fclk;
    s->lines = 4;
    s->rev = 2;

    omap_mmc_reset(s);

    memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc",
                          omap_l4_region_size(ta, 0));
    omap_l4_attach(ta, 0, &s->iomem);

    /* Instantiate the storage */
    s->card = sd_init(blk, false);
    if (s->card == NULL) {
        exit(1);
    }

    s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0);
    sd_set_cb(s->card, NULL, s->cdet);

    return s;
}

void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
{
    if (s->cdet) {
        sd_set_cb(s->card, ro, s->cdet);
        s->coverswitch = cover;
        qemu_set_irq(cover, s->cdet_state);
    } else
        sd_set_cb(s->card, ro, cover);
}

void omap_mmc_enable(struct omap_mmc_s *s, int enable)
{
    sd_enable(s->card, enable);
}
Commit	Line	Data
b30bb3a2 AZ	1	/*
	2	* OMAP on-chip MMC/SD host emulation.
	3	*
	4	* Copyright (C) 2006-2007 Andrzej Zaborowski <[email protected]>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
827df9f3 AZ	8	* published by the Free Software Foundation; either version 2 or
827df9f3 AZ	9	* (at your option) version 3 of the License.
b30bb3a2 AZ	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
fad6cb1a	16	* You should have received a copy of the GNU General Public License along
8167ee88	17	* with this program; if not, see <http://www.gnu.org/licenses/>.
b30bb3a2	18	*/
83c9f4ca	19	#include "hw/hw.h"
0d09e41a	20	#include "hw/arm/omap.h"
83c9f4ca	21	#include "hw/sd.h"
b30bb3a2 AZ	22
b30bb3a2 AZ	23	struct omap_mmc_s {
b30bb3a2 AZ	24	qemu_irq irq;
b30bb3a2 AZ	25	qemu_irq *dma;
827df9f3	26	qemu_irq coverswitch;
c304fed7	27	MemoryRegion iomem;
b30bb3a2 AZ	28	omap_clk clk;
	29	SDState *card;
	30	uint16_t last_cmd;
	31	uint16_t sdio;
	32	uint16_t rsp[8];
	33	uint32_t arg;
827df9f3	34	int lines;
b30bb3a2 AZ	35	int dw;
	36	int mode;
	37	int enable;
827df9f3 AZ	38	int be;
827df9f3 AZ	39	int rev;
b30bb3a2 AZ	40	uint16_t status;
	41	uint16_t mask;
	42	uint8_t cto;
	43	uint16_t dto;
827df9f3	44	int clkdiv;
b30bb3a2 AZ	45	uint16_t fifo[32];
	46	int fifo_start;
	47	int fifo_len;
	48	uint16_t blen;
	49	uint16_t blen_counter;
	50	uint16_t nblk;
	51	uint16_t nblk_counter;
	52	int tx_dma;
	53	int rx_dma;
	54	int af_level;
	55	int ae_level;
	56
	57	int ddir;
	58	int transfer;
827df9f3 AZ	59
	60	int cdet_wakeup;
	61	int cdet_enable;
	62	int cdet_state;
	63	qemu_irq cdet;
b30bb3a2 AZ	64	};
	65
	66	static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
	67	{
	68	qemu_set_irq(s->irq, !!(s->status & s->mask));
	69	}
	70
	71	static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
	72	{
	73	if (!host->transfer && !host->fifo_len) {
	74	host->status &= 0xf3ff;
	75	return;
	76	}
	77
	78	if (host->fifo_len > host->af_level && host->ddir) {
	79	if (host->rx_dma) {
	80	host->status &= 0xfbff;
	81	qemu_irq_raise(host->dma[1]);
	82	} else
	83	host->status \|= 0x0400;
	84	} else {
	85	host->status &= 0xfbff;
	86	qemu_irq_lower(host->dma[1]);
	87	}
	88
	89	if (host->fifo_len < host->ae_level && !host->ddir) {
	90	if (host->tx_dma) {
	91	host->status &= 0xf7ff;
	92	qemu_irq_raise(host->dma[0]);
	93	} else
	94	host->status \|= 0x0800;
	95	} else {
	96	qemu_irq_lower(host->dma[0]);
	97	host->status &= 0xf7ff;
	98	}
	99	}
	100
	101	typedef enum {
	102	sd_nore = 0, /* no response */
	103	sd_r1, /* normal response command */
	104	sd_r2, /* CID, CSD registers */
	105	sd_r3, /* OCR register */
	106	sd_r6 = 6, /* Published RCA response */
	107	sd_r1b = -1,
c227f099	108	} sd_rsp_type_t;
b30bb3a2 AZ	109
b30bb3a2 AZ	110	static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
c227f099	111	sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
b30bb3a2 AZ	112	{
	113	uint32_t rspstatus, mask;
	114	int rsplen, timeout;
bc24a225	115	SDRequest request;
b30bb3a2 AZ	116	uint8_t response[16];
b30bb3a2 AZ	117
827df9f3 AZ	118	if (init && cmd == 0) {
	119	host->status \|= 0x0001;
	120	return;
	121	}
	122
b30bb3a2 AZ	123	if (resptype == sd_r1 && busy)
	124	resptype = sd_r1b;
	125
	126	if (type == sd_adtc) {
	127	host->fifo_start = 0;
	128	host->fifo_len = 0;
	129	host->transfer = 1;
	130	host->ddir = dir;
	131	} else
	132	host->transfer = 0;
	133	timeout = 0;
	134	mask = 0;
	135	rspstatus = 0;
	136
	137	request.cmd = cmd;
	138	request.arg = host->arg;
	139	request.crc = 0; /* FIXME */
	140
	141	rsplen = sd_do_command(host->card, &request, response);
	142
	143	/* TODO: validate CRCs */
	144	switch (resptype) {
	145	case sd_nore:
	146	rsplen = 0;
	147	break;
	148
	149	case sd_r1:
	150	case sd_r1b:
	151	if (rsplen < 4) {
	152	timeout = 1;
	153	break;
	154	}
	155	rsplen = 4;
	156
	157	mask = OUT_OF_RANGE \| ADDRESS_ERROR \| BLOCK_LEN_ERROR \|
	158	ERASE_SEQ_ERROR \| ERASE_PARAM \| WP_VIOLATION \|
	159	LOCK_UNLOCK_FAILED \| COM_CRC_ERROR \| ILLEGAL_COMMAND \|
	160	CARD_ECC_FAILED \| CC_ERROR \| SD_ERROR \|
	161	CID_CSD_OVERWRITE;
	162	if (host->sdio & (1 << 13))
	163	mask \|= AKE_SEQ_ERROR;
	164	rspstatus = (response[0] << 24) \| (response[1] << 16) \|
	165	(response[2] << 8) \| (response[3] << 0);
	166	break;
	167
	168	case sd_r2:
	169	if (rsplen < 16) {
	170	timeout = 1;
	171	break;
	172	}
	173	rsplen = 16;
	174	break;
	175
	176	case sd_r3:
	177	if (rsplen < 4) {
	178	timeout = 1;
	179	break;
	180	}
	181	rsplen = 4;
	182
	183	rspstatus = (response[0] << 24) \| (response[1] << 16) \|
	184	(response[2] << 8) \| (response[3] << 0);
	185	if (rspstatus & 0x80000000)
	186	host->status &= 0xe000;
187	else
188	host->status \|= 0x1000;
189	break;
190
191	case sd_r6:
192	if (rsplen < 4) {
193	timeout = 1;
194	break;
195	}
196	rsplen = 4;
197
198	mask = 0xe000 \| AKE_SEQ_ERROR;
199	rspstatus = (response[2] << 8) \| (response[3] << 0);
200	}
201
202	if (rspstatus & mask)
203	host->status \|= 0x4000;
204	else
205	host->status &= 0xb000;
206
207	if (rsplen)
208	for (rsplen = 0; rsplen < 8; rsplen ++)
209	host->rsp[~rsplen & 7] = response[(rsplen << 1) \| 1] \|
210	(response[(rsplen << 1) \| 0] << 8);
211
212	if (timeout)
213	host->status \|= 0x0080;
214	else if (cmd == 12)
215	host->status \|= 0x0005; /* Makes it more real */
216	else
217	host->status \|= 0x0001;
218	}
219
220	static void omap_mmc_transfer(struct omap_mmc_s *host)
221	{
222	uint8_t value;
223
224	if (!host->transfer)
225	return;
226
227	while (1) {
228	if (host->ddir) {
229	if (host->fifo_len > host->af_level)
230	break;
231
232	value = sd_read_data(host->card);
233	host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
234	if (-- host->blen_counter) {
235	value = sd_read_data(host->card);
236	host->fifo[(host->fifo_start + host->fifo_len) & 31] \|=
237	value << 8;
238	host->blen_counter --;
239	}
240
241	host->fifo_len ++;
242	} else {
243	if (!host->fifo_len)
244	break;
245
246	value = host->fifo[host->fifo_start] & 0xff;
247	sd_write_data(host->card, value);
248	if (-- host->blen_counter) {
249	value = host->fifo[host->fifo_start] >> 8;
250	sd_write_data(host->card, value);
251	host->blen_counter --;
252	}
253
254	host->fifo_start ++;
255	host->fifo_len --;
256	host->fifo_start &= 31;
257	}
258
259	if (host->blen_counter == 0) {
260	host->nblk_counter --;
261	host->blen_counter = host->blen;
262
263	if (host->nblk_counter == 0) {
264	host->nblk_counter = host->nblk;
265	host->transfer = 0;
266	host->status \|= 0x0008;
267	break;
268	}
269	}
270	}
271	}
272
273	static void omap_mmc_update(void *opaque)
274	{
275	struct omap_mmc_s *s = opaque;
276	omap_mmc_transfer(s);
277	omap_mmc_fifolevel_update(s);
278	omap_mmc_interrupts_update(s);
279	}
280
827df9f3 AZ	281	void omap_mmc_reset(struct omap_mmc_s *host)
	282	{
	283	host->last_cmd = 0;
	284	memset(host->rsp, 0, sizeof(host->rsp));
	285	host->arg = 0;
	286	host->dw = 0;
	287	host->mode = 0;
	288	host->enable = 0;
	289	host->status = 0;
	290	host->mask = 0;
	291	host->cto = 0;
	292	host->dto = 0;
	293	host->fifo_len = 0;
	294	host->blen = 0;
	295	host->blen_counter = 0;
	296	host->nblk = 0;
	297	host->nblk_counter = 0;
	298	host->tx_dma = 0;
	299	host->rx_dma = 0;
	300	host->ae_level = 0x00;
	301	host->af_level = 0x1f;
	302	host->transfer = 0;
	303	host->cdet_wakeup = 0;
	304	host->cdet_enable = 0;
	305	qemu_set_irq(host->coverswitch, host->cdet_state);
	306	host->clkdiv = 0;
	307	}
	308
a8170e5e	309	static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
c304fed7	310	unsigned size)
b30bb3a2 AZ	311	{
	312	uint16_t i;
	313	struct omap_mmc_s s = (struct omap_mmc_s ) opaque;
c304fed7 AK	314
	315	if (size != 2) {
	316	return omap_badwidth_read16(opaque, offset);
	317	}
b30bb3a2 AZ	318
	319	switch (offset) {
	320	case 0x00: /* MMC_CMD */
	321	return s->last_cmd;
	322
	323	case 0x04: /* MMC_ARGL */
	324	return s->arg & 0x0000ffff;
	325
	326	case 0x08: /* MMC_ARGH */
	327	return s->arg >> 16;
	328
	329	case 0x0c: /* MMC_CON */
827df9f3 AZ	330	return (s->dw << 15) \| (s->mode << 12) \| (s->enable << 11) \|
827df9f3 AZ	331	(s->be << 10) \| s->clkdiv;
b30bb3a2 AZ	332
	333	case 0x10: /* MMC_STAT */
	334	return s->status;
	335
	336	case 0x14: /* MMC_IE */
	337	return s->mask;
	338
	339	case 0x18: /* MMC_CTO */
	340	return s->cto;
	341
	342	case 0x1c: /* MMC_DTO */
	343	return s->dto;
	344
	345	case 0x20: /* MMC_DATA */
	346	/* TODO: support 8-bit access */
	347	i = s->fifo[s->fifo_start];
	348	if (s->fifo_len == 0) {
	349	printf("MMC: FIFO underrun\n");
	350	return i;
	351	}
	352	s->fifo_start ++;
	353	s->fifo_len --;
	354	s->fifo_start &= 31;
	355	omap_mmc_transfer(s);
	356	omap_mmc_fifolevel_update(s);
	357	omap_mmc_interrupts_update(s);
	358	return i;
	359
	360	case 0x24: /* MMC_BLEN */
	361	return s->blen_counter;
	362
	363	case 0x28: /* MMC_NBLK */
	364	return s->nblk_counter;
	365
	366	case 0x2c: /* MMC_BUF */
	367	return (s->rx_dma << 15) \| (s->af_level << 8) \|
	368	(s->tx_dma << 7) \| s->ae_level;
	369
	370	case 0x30: /* MMC_SPI */
	371	return 0x0000;
	372	case 0x34: /* MMC_SDIO */
827df9f3	373	return (s->cdet_wakeup << 2) \| (s->cdet_enable) \| s->sdio;
b30bb3a2 AZ	374	case 0x38: /* MMC_SYST */
	375	return 0x0000;
	376
	377	case 0x3c: /* MMC_REV */
827df9f3	378	return s->rev;
b30bb3a2 AZ	379
	380	case 0x40: /* MMC_RSP0 */
	381	case 0x44: /* MMC_RSP1 */
	382	case 0x48: /* MMC_RSP2 */
	383	case 0x4c: /* MMC_RSP3 */
	384	case 0x50: /* MMC_RSP4 */
	385	case 0x54: /* MMC_RSP5 */
	386	case 0x58: /* MMC_RSP6 */
	387	case 0x5c: /* MMC_RSP7 */
	388	return s->rsp[(offset - 0x40) >> 2];
827df9f3 AZ	389
	390	/* OMAP2-specific */
	391	case 0x60: /* MMC_IOSR */
	392	case 0x64: /* MMC_SYSC */
	393	return 0;
	394	case 0x68: /* MMC_SYSS */
	395	return 1; /* RSTD */
b30bb3a2 AZ	396	}
	397
	398	OMAP_BAD_REG(offset);
	399	return 0;
	400	}
	401
a8170e5e	402	static void omap_mmc_write(void *opaque, hwaddr offset,
c304fed7	403	uint64_t value, unsigned size)
b30bb3a2 AZ	404	{
	405	int i;
	406	struct omap_mmc_s s = (struct omap_mmc_s ) opaque;
c304fed7 AK	407
c304fed7 AK	408	if (size != 2) {
77a8257e SW	409	omap_badwidth_write16(opaque, offset, value);
77a8257e SW	410	return;
c304fed7	411	}
b30bb3a2 AZ	412
	413	switch (offset) {
	414	case 0x00: /* MMC_CMD */
	415	if (!s->enable)
	416	break;
	417
	418	s->last_cmd = value;
	419	for (i = 0; i < 8; i ++)
	420	s->rsp[i] = 0x0000;
	421	omap_mmc_command(s, value & 63, (value >> 15) & 1,
c227f099	422	(sd_cmd_type_t) ((value >> 12) & 3),
b30bb3a2	423	(value >> 11) & 1,
c227f099	424	(sd_rsp_type_t) ((value >> 8) & 7),
b30bb3a2 AZ	425	(value >> 7) & 1);
	426	omap_mmc_update(s);
	427	break;
	428
	429	case 0x04: /* MMC_ARGL */
	430	s->arg &= 0xffff0000;
	431	s->arg \|= 0x0000ffff & value;
	432	break;
	433
	434	case 0x08: /* MMC_ARGH */
	435	s->arg &= 0x0000ffff;
	436	s->arg \|= value << 16;
	437	break;
	438
	439	case 0x0c: /* MMC_CON */
	440	s->dw = (value >> 15) & 1;
	441	s->mode = (value >> 12) & 3;
	442	s->enable = (value >> 11) & 1;
827df9f3 AZ	443	s->be = (value >> 10) & 1;
827df9f3 AZ	444	s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff);
b30bb3a2 AZ	445	if (s->mode != 0)
b30bb3a2 AZ	446	printf("SD mode %i unimplemented!\n", s->mode);
827df9f3 AZ	447	if (s->be != 0)
	448	printf("SD FIFO byte sex unimplemented!\n");
	449	if (s->dw != 0 && s->lines < 4)
b30bb3a2	450	printf("4-bit SD bus enabled\n");
827df9f3 AZ	451	if (!s->enable)
827df9f3 AZ	452	omap_mmc_reset(s);
b30bb3a2 AZ	453	break;
	454
	455	case 0x10: /* MMC_STAT */
	456	s->status &= ~value;
	457	omap_mmc_interrupts_update(s);
	458	break;
	459
	460	case 0x14: /* MMC_IE */
827df9f3	461	s->mask = value & 0x7fff;
b30bb3a2 AZ	462	omap_mmc_interrupts_update(s);
	463	break;
	464
	465	case 0x18: /* MMC_CTO */
	466	s->cto = value & 0xff;
827df9f3	467	if (s->cto > 0xfd && s->rev <= 1)
b30bb3a2 AZ	468	printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
	469	break;
	470
	471	case 0x1c: /* MMC_DTO */
	472	s->dto = value & 0xffff;
	473	break;
	474
	475	case 0x20: /* MMC_DATA */
	476	/* TODO: support 8-bit access */
	477	if (s->fifo_len == 32)
	478	break;
	479	s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
	480	s->fifo_len ++;
	481	omap_mmc_transfer(s);
	482	omap_mmc_fifolevel_update(s);
	483	omap_mmc_interrupts_update(s);
	484	break;
	485
	486	case 0x24: /* MMC_BLEN */
	487	s->blen = (value & 0x07ff) + 1;
	488	s->blen_counter = s->blen;
	489	break;
	490
	491	case 0x28: /* MMC_NBLK */
	492	s->nblk = (value & 0x07ff) + 1;
	493	s->nblk_counter = s->nblk;
	494	s->blen_counter = s->blen;
	495	break;
	496
	497	case 0x2c: /* MMC_BUF */
	498	s->rx_dma = (value >> 15) & 1;
	499	s->af_level = (value >> 8) & 0x1f;
	500	s->tx_dma = (value >> 7) & 1;
	501	s->ae_level = value & 0x1f;
	502
	503	if (s->rx_dma)
	504	s->status &= 0xfbff;
	505	if (s->tx_dma)
	506	s->status &= 0xf7ff;
	507	omap_mmc_fifolevel_update(s);
	508	omap_mmc_interrupts_update(s);
	509	break;
	510
	511	/* SPI, SDIO and TEST modes unimplemented */
827df9f3	512	case 0x30: /* MMC_SPI (OMAP1 only) */
b30bb3a2 AZ	513	break;
b30bb3a2 AZ	514	case 0x34: /* MMC_SDIO */
827df9f3 AZ	515	s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020);
	516	s->cdet_wakeup = (value >> 9) & 1;
	517	s->cdet_enable = (value >> 2) & 1;
b30bb3a2 AZ	518	break;
	519	case 0x38: /* MMC_SYST */
	520	break;
	521
	522	case 0x3c: /* MMC_REV */
	523	case 0x40: /* MMC_RSP0 */
	524	case 0x44: /* MMC_RSP1 */
	525	case 0x48: /* MMC_RSP2 */
	526	case 0x4c: /* MMC_RSP3 */
	527	case 0x50: /* MMC_RSP4 */
	528	case 0x54: /* MMC_RSP5 */
	529	case 0x58: /* MMC_RSP6 */
	530	case 0x5c: /* MMC_RSP7 */
	531	OMAP_RO_REG(offset);
	532	break;
	533
827df9f3 AZ	534	/* OMAP2-specific */
	535	case 0x60: /* MMC_IOSR */
	536	if (value & 0xf)
	537	printf("MMC: SDIO bits used!\n");
	538	break;
	539	case 0x64: /* MMC_SYSC */
	540	if (value & (1 << 2)) /* SRTS */
	541	omap_mmc_reset(s);
	542	break;
	543	case 0x68: /* MMC_SYSS */
	544	OMAP_RO_REG(offset);
	545	break;
	546
b30bb3a2 AZ	547	default:
	548	OMAP_BAD_REG(offset);
	549	}
	550	}
	551
c304fed7 AK	552	static const MemoryRegionOps omap_mmc_ops = {
	553	.read = omap_mmc_read,
	554	.write = omap_mmc_write,
	555	.endianness = DEVICE_NATIVE_ENDIAN,
b30bb3a2 AZ	556	};
b30bb3a2 AZ	557
827df9f3	558	static void omap_mmc_cover_cb(void *opaque, int line, int level)
b30bb3a2	559	{
827df9f3 AZ	560	struct omap_mmc_s host = (struct omap_mmc_s ) opaque;
	561
	562	if (!host->cdet_state && level) {
	563	host->status \|= 0x0002;
	564	omap_mmc_interrupts_update(host);
3ffd710e BS	565	if (host->cdet_wakeup) {
	566	/* TODO: Assert wake-up */
	567	}
827df9f3 AZ	568	}
	569
	570	if (host->cdet_state != level) {
	571	qemu_set_irq(host->coverswitch, level);
	572	host->cdet_state = level;
	573	}
b30bb3a2 AZ	574	}
b30bb3a2 AZ	575
a8170e5e	576	struct omap_mmc_s *omap_mmc_init(hwaddr base,
c304fed7	577	MemoryRegion *sysmem,
4be74634	578	BlockBackend *blk,
b30bb3a2 AZ	579	qemu_irq irq, qemu_irq dma[], omap_clk clk)
b30bb3a2 AZ	580	{
b45c03f5	581	struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
b30bb3a2 AZ	582
b30bb3a2 AZ	583	s->irq = irq;
b30bb3a2 AZ	584	s->dma = dma;
b30bb3a2 AZ	585	s->clk = clk;
827df9f3 AZ	586	s->lines = 1; /* TODO: needs to be settable per-board */
	587	s->rev = 1;
	588
	589	omap_mmc_reset(s);
b30bb3a2	590
2c9b15ca	591	memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800);
c304fed7	592	memory_region_add_subregion(sysmem, base, &s->iomem);
b30bb3a2 AZ	593
b30bb3a2 AZ	594	/* Instantiate the storage */
4be74634	595	s->card = sd_init(blk, false);
4f8a066b KW	596	if (s->card == NULL) {
	597	exit(1);
	598	}
b30bb3a2 AZ	599
	600	return s;
	601	}
	602
827df9f3	603	struct omap_mmc_s omap2_mmc_init(struct omap_target_agent_s ta,
4be74634	604	BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
827df9f3 AZ	605	omap_clk fclk, omap_clk iclk)
827df9f3 AZ	606	{
b45c03f5	607	struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
827df9f3 AZ	608
	609	s->irq = irq;
	610	s->dma = dma;
	611	s->clk = fclk;
	612	s->lines = 4;
	613	s->rev = 2;
	614
	615	omap_mmc_reset(s);
	616
2c9b15ca	617	memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc",
c304fed7	618	omap_l4_region_size(ta, 0));
f44336c5	619	omap_l4_attach(ta, 0, &s->iomem);
827df9f3 AZ	620
827df9f3 AZ	621	/* Instantiate the storage */
4be74634	622	s->card = sd_init(blk, false);
4f8a066b KW	623	if (s->card == NULL) {
	624	exit(1);
	625	}
827df9f3	626
f3c7d038	627	s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0);
b9d38e95	628	sd_set_cb(s->card, NULL, s->cdet);
827df9f3 AZ	629
	630	return s;
	631	}
	632
8e129e07 AZ	633	void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
8e129e07 AZ	634	{
827df9f3 AZ	635	if (s->cdet) {
	636	sd_set_cb(s->card, ro, s->cdet);
	637	s->coverswitch = cover;
	638	qemu_set_irq(cover, s->cdet_state);
	639	} else
	640	sd_set_cb(s->card, ro, cover);
	641	}
	642
	643	void omap_mmc_enable(struct omap_mmc_s *s, int enable)
	644	{
	645	sd_enable(s->card, enable);
8e129e07	646	}