[qemu.git] / hw / riscv / sifive_clint.c

/*
 * SiFive CLINT (Core Local Interruptor)
 *
 * Copyright (c) 2016-2017 Sagar Karandikar, [email protected]
 * Copyright (c) 2017 SiFive, Inc.
 *
 * This provides real-time clock, timer and interprocessor interrupts.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "hw/sysbus.h"
#include "target/riscv/cpu.h"
#include "hw/qdev-properties.h"
#include "hw/riscv/sifive_clint.h"
#include "qemu/timer.h"

static uint64_t cpu_riscv_read_rtc(void)
{
    return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
        SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
}

/*
 * Called when timecmp is written to update the QEMU timer or immediately
 * trigger timer interrupt if mtimecmp <= current timer value.
 */
static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
{
    uint64_t next;
    uint64_t diff;

    uint64_t rtc_r = cpu_riscv_read_rtc();

    cpu->env.timecmp = value;
    if (cpu->env.timecmp <= rtc_r) {
        /* if we're setting an MTIMECMP value in the "past",
           immediately raise the timer interrupt */
        riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
        return;
    }

    /* otherwise, set up the future timer interrupt */
    riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
    diff = cpu->env.timecmp - rtc_r;
    /* back to ns (note args switched in muldiv64) */
    next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
        muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
    timer_mod(cpu->env.timer, next);
}

/*
 * Callback used when the timer set using timer_mod expires.
 * Should raise the timer interrupt line
 */
static void sifive_clint_timer_cb(void *opaque)
{
    RISCVCPU *cpu = opaque;
    riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
}

/* CPU wants to read rtc or timecmp register */
static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
{
    SiFiveCLINTState *clint = opaque;
    if (addr >= clint->sip_base &&
        addr < clint->sip_base + (clint->num_harts << 2)) {
        size_t hartid = (addr - clint->sip_base) >> 2;
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            error_report("clint: invalid timecmp hartid: %zu", hartid);
        } else if ((addr & 0x3) == 0) {
            return (env->mip & MIP_MSIP) > 0;
        } else {
            error_report("clint: invalid read: %08x", (uint32_t)addr);
            return 0;
        }
    } else if (addr >= clint->timecmp_base &&
        addr < clint->timecmp_base + (clint->num_harts << 3)) {
        size_t hartid = (addr - clint->timecmp_base) >> 3;
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            error_report("clint: invalid timecmp hartid: %zu", hartid);
        } else if ((addr & 0x7) == 0) {
            /* timecmp_lo */
            uint64_t timecmp = env->timecmp;
            return timecmp & 0xFFFFFFFF;
        } else if ((addr & 0x7) == 4) {
            /* timecmp_hi */
            uint64_t timecmp = env->timecmp;
            return (timecmp >> 32) & 0xFFFFFFFF;
        } else {
            error_report("clint: invalid read: %08x", (uint32_t)addr);
            return 0;
        }
    } else if (addr == clint->time_base) {
        /* time_lo */
        return cpu_riscv_read_rtc() & 0xFFFFFFFF;
    } else if (addr == clint->time_base + 4) {
        /* time_hi */
        return (cpu_riscv_read_rtc() >> 32) & 0xFFFFFFFF;
    }

    error_report("clint: invalid read: %08x", (uint32_t)addr);
    return 0;
}

/* CPU wrote to rtc or timecmp register */
static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
        unsigned size)
{
    SiFiveCLINTState *clint = opaque;

    if (addr >= clint->sip_base &&
        addr < clint->sip_base + (clint->num_harts << 2)) {
        size_t hartid = (addr - clint->sip_base) >> 2;
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            error_report("clint: invalid timecmp hartid: %zu", hartid);
        } else if ((addr & 0x3) == 0) {
            riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MSIP, BOOL_TO_MASK(value));
        } else {
            error_report("clint: invalid sip write: %08x", (uint32_t)addr);
        }
        return;
    } else if (addr >= clint->timecmp_base &&
        addr < clint->timecmp_base + (clint->num_harts << 3)) {
        size_t hartid = (addr - clint->timecmp_base) >> 3;
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            error_report("clint: invalid timecmp hartid: %zu", hartid);
        } else if ((addr & 0x7) == 0) {
            /* timecmp_lo */
            uint64_t timecmp_hi = env->timecmp >> 32;
            sifive_clint_write_timecmp(RISCV_CPU(cpu),
                timecmp_hi << 32 | (value & 0xFFFFFFFF));
            return;
        } else if ((addr & 0x7) == 4) {
            /* timecmp_hi */
            uint64_t timecmp_lo = env->timecmp;
            sifive_clint_write_timecmp(RISCV_CPU(cpu),
                value << 32 | (timecmp_lo & 0xFFFFFFFF));
        } else {
            error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);
        }
        return;
    } else if (addr == clint->time_base) {
        /* time_lo */
        error_report("clint: time_lo write not implemented");
        return;
    } else if (addr == clint->time_base + 4) {
        /* time_hi */
        error_report("clint: time_hi write not implemented");
        return;
    }

    error_report("clint: invalid write: %08x", (uint32_t)addr);
}

static const MemoryRegionOps sifive_clint_ops = {
    .read = sifive_clint_read,
    .write = sifive_clint_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4
    }
};

static Property sifive_clint_properties[] = {
    DEFINE_PROP_UINT32("num-harts", SiFiveCLINTState, num_harts, 0),
    DEFINE_PROP_UINT32("sip-base", SiFiveCLINTState, sip_base, 0),
    DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
    DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0),
    DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void sifive_clint_realize(DeviceState *dev, Error **errp)
{
    SiFiveCLINTState *s = SIFIVE_CLINT(dev);
    memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_clint_ops, s,
                          TYPE_SIFIVE_CLINT, s->aperture_size);
    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
}

static void sifive_clint_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    dc->realize = sifive_clint_realize;
    dc->props = sifive_clint_properties;
}

static const TypeInfo sifive_clint_info = {
    .name          = TYPE_SIFIVE_CLINT,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(SiFiveCLINTState),
    .class_init    = sifive_clint_class_init,
};

static void sifive_clint_register_types(void)
{
    type_register_static(&sifive_clint_info);
}

type_init(sifive_clint_register_types)


/*
 * Create CLINT device.
 */
DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
    uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base)
{
    int i;
    for (i = 0; i < num_harts; i++) {
        CPUState *cpu = qemu_get_cpu(i);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            continue;
        }
        env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                  &sifive_clint_timer_cb, cpu);
        env->timecmp = 0;
    }

    DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_CLINT);
    qdev_prop_set_uint32(dev, "num-harts", num_harts);
    qdev_prop_set_uint32(dev, "sip-base", sip_base);
    qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
    qdev_prop_set_uint32(dev, "time-base", time_base);
    qdev_prop_set_uint32(dev, "aperture-size", size);
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
    return dev;
}
Commit	Line	Data
1c77c410 MC	1	/*
	2	* SiFive CLINT (Core Local Interruptor)
	3	*
	4	* Copyright (c) 2016-2017 Sagar Karandikar, [email protected]
	5	* Copyright (c) 2017 SiFive, Inc.
	6	*
	7	* This provides real-time clock, timer and interprocessor interrupts.
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms and conditions of the GNU General Public License,
	11	* version 2 or later, as published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope it will be useful, but WITHOUT
	14	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	15	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	16	* more details.
	17	*
	18	* You should have received a copy of the GNU General Public License along with
	19	* this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#include "qemu/osdep.h"
	23	#include "qemu/error-report.h"
0b8fa32f	24	#include "qemu/module.h"
1c77c410 MC	25	#include "hw/sysbus.h"
1c77c410 MC	26	#include "target/riscv/cpu.h"
a27bd6c7	27	#include "hw/qdev-properties.h"
1c77c410 MC	28	#include "hw/riscv/sifive_clint.h"
	29	#include "qemu/timer.h"
	30
1c77c410 MC	31	static uint64_t cpu_riscv_read_rtc(void)
1c77c410 MC	32	{
2a8756ed MC	33	return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
2a8756ed MC	34	SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
1c77c410 MC	35	}
	36
	37	/*
	38	* Called when timecmp is written to update the QEMU timer or immediately
	39	* trigger timer interrupt if mtimecmp <= current timer value.
	40	*/
	41	static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
	42	{
	43	uint64_t next;
	44	uint64_t diff;
	45
	46	uint64_t rtc_r = cpu_riscv_read_rtc();
	47
	48	cpu->env.timecmp = value;
	49	if (cpu->env.timecmp <= rtc_r) {
	50	/* if we're setting an MTIMECMP value in the "past",
	51	immediately raise the timer interrupt */
85ba724f	52	riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
1c77c410 MC	53	return;
	54	}
	55
	56	/* otherwise, set up the future timer interrupt */
85ba724f	57	riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
1c77c410 MC	58	diff = cpu->env.timecmp - rtc_r;
	59	/* back to ns (note args switched in muldiv64) */
	60	next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2a8756ed	61	muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
1c77c410 MC	62	timer_mod(cpu->env.timer, next);
	63	}
	64
	65	/*
	66	* Callback used when the timer set using timer_mod expires.
	67	* Should raise the timer interrupt line
	68	*/
	69	static void sifive_clint_timer_cb(void *opaque)
	70	{
	71	RISCVCPU *cpu = opaque;
85ba724f	72	riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
1c77c410 MC	73	}
	74
	75	/* CPU wants to read rtc or timecmp register */
	76	static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
	77	{
	78	SiFiveCLINTState *clint = opaque;
	79	if (addr >= clint->sip_base &&
	80	addr < clint->sip_base + (clint->num_harts << 2)) {
	81	size_t hartid = (addr - clint->sip_base) >> 2;
	82	CPUState *cpu = qemu_get_cpu(hartid);
	83	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	84	if (!env) {
	85	error_report("clint: invalid timecmp hartid: %zu", hartid);
	86	} else if ((addr & 0x3) == 0) {
	87	return (env->mip & MIP_MSIP) > 0;
	88	} else {
	89	error_report("clint: invalid read: %08x", (uint32_t)addr);
	90	return 0;
	91	}
	92	} else if (addr >= clint->timecmp_base &&
	93	addr < clint->timecmp_base + (clint->num_harts << 3)) {
	94	size_t hartid = (addr - clint->timecmp_base) >> 3;
	95	CPUState *cpu = qemu_get_cpu(hartid);
	96	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	97	if (!env) {
	98	error_report("clint: invalid timecmp hartid: %zu", hartid);
	99	} else if ((addr & 0x7) == 0) {
	100	/* timecmp_lo */
	101	uint64_t timecmp = env->timecmp;
	102	return timecmp & 0xFFFFFFFF;
	103	} else if ((addr & 0x7) == 4) {
	104	/* timecmp_hi */
	105	uint64_t timecmp = env->timecmp;
	106	return (timecmp >> 32) & 0xFFFFFFFF;
	107	} else {
	108	error_report("clint: invalid read: %08x", (uint32_t)addr);
	109	return 0;
	110	}
	111	} else if (addr == clint->time_base) {
	112	/* time_lo */
	113	return cpu_riscv_read_rtc() & 0xFFFFFFFF;
	114	} else if (addr == clint->time_base + 4) {
	115	/* time_hi */
	116	return (cpu_riscv_read_rtc() >> 32) & 0xFFFFFFFF;
	117	}
	118
	119	error_report("clint: invalid read: %08x", (uint32_t)addr);
	120	return 0;
	121	}
	122
	123	/* CPU wrote to rtc or timecmp register */
	124	static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
	125	unsigned size)
	126	{
	127	SiFiveCLINTState *clint = opaque;
	128
	129	if (addr >= clint->sip_base &&
	130	addr < clint->sip_base + (clint->num_harts << 2)) {
	131	size_t hartid = (addr - clint->sip_base) >> 2;
	132	CPUState *cpu = qemu_get_cpu(hartid);
	133	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	134	if (!env) {
	135	error_report("clint: invalid timecmp hartid: %zu", hartid);
	136	} else if ((addr & 0x3) == 0) {
85ba724f	137	riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MSIP, BOOL_TO_MASK(value));
1c77c410 MC	138	} else {
	139	error_report("clint: invalid sip write: %08x", (uint32_t)addr);
	140	}
	141	return;
	142	} else if (addr >= clint->timecmp_base &&
	143	addr < clint->timecmp_base + (clint->num_harts << 3)) {
	144	size_t hartid = (addr - clint->timecmp_base) >> 3;
	145	CPUState *cpu = qemu_get_cpu(hartid);
	146	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	147	if (!env) {
	148	error_report("clint: invalid timecmp hartid: %zu", hartid);
	149	} else if ((addr & 0x7) == 0) {
	150	/* timecmp_lo */
ef9e41df	151	uint64_t timecmp_hi = env->timecmp >> 32;
1c77c410	152	sifive_clint_write_timecmp(RISCV_CPU(cpu),
ef9e41df	153	timecmp_hi << 32 \| (value & 0xFFFFFFFF));
1c77c410 MC	154	return;
	155	} else if ((addr & 0x7) == 4) {
	156	/* timecmp_hi */
ef9e41df	157	uint64_t timecmp_lo = env->timecmp;
1c77c410	158	sifive_clint_write_timecmp(RISCV_CPU(cpu),
ef9e41df	159	value << 32 \| (timecmp_lo & 0xFFFFFFFF));
1c77c410 MC	160	} else {
	161	error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);
	162	}
	163	return;
	164	} else if (addr == clint->time_base) {
	165	/* time_lo */
	166	error_report("clint: time_lo write not implemented");
	167	return;
	168	} else if (addr == clint->time_base + 4) {
	169	/* time_hi */
	170	error_report("clint: time_hi write not implemented");
	171	return;
	172	}
	173
	174	error_report("clint: invalid write: %08x", (uint32_t)addr);
	175	}
	176
	177	static const MemoryRegionOps sifive_clint_ops = {
	178	.read = sifive_clint_read,
	179	.write = sifive_clint_write,
	180	.endianness = DEVICE_LITTLE_ENDIAN,
	181	.valid = {
	182	.min_access_size = 4,
	183	.max_access_size = 4
	184	}
	185	};
	186
	187	static Property sifive_clint_properties[] = {
	188	DEFINE_PROP_UINT32("num-harts", SiFiveCLINTState, num_harts, 0),
	189	DEFINE_PROP_UINT32("sip-base", SiFiveCLINTState, sip_base, 0),
	190	DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
	191	DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0),
	192	DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0),
	193	DEFINE_PROP_END_OF_LIST(),
	194	};
	195
	196	static void sifive_clint_realize(DeviceState dev, Error *errp)
	197	{
	198	SiFiveCLINTState *s = SIFIVE_CLINT(dev);
	199	memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_clint_ops, s,
	200	TYPE_SIFIVE_CLINT, s->aperture_size);
	201	sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
	202	}
	203
	204	static void sifive_clint_class_init(ObjectClass klass, void data)
	205	{
	206	DeviceClass *dc = DEVICE_CLASS(klass);
	207	dc->realize = sifive_clint_realize;
	208	dc->props = sifive_clint_properties;
	209	}
	210
	211	static const TypeInfo sifive_clint_info = {
	212	.name = TYPE_SIFIVE_CLINT,
	213	.parent = TYPE_SYS_BUS_DEVICE,
	214	.instance_size = sizeof(SiFiveCLINTState),
	215	.class_init = sifive_clint_class_init,
	216	};
	217
	218	static void sifive_clint_register_types(void)
	219	{
	220	type_register_static(&sifive_clint_info);
	221	}
	222
	223	type_init(sifive_clint_register_types)
224
225
226	/*
227	* Create CLINT device.
228	*/
229	DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
230	uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base)
231	{
232	int i;
233	for (i = 0; i < num_harts; i++) {
234	CPUState *cpu = qemu_get_cpu(i);
235	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
236	if (!env) {
237	continue;
238	}
239	env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
240	&sifive_clint_timer_cb, cpu);
241	env->timecmp = 0;
242	}
243
244	DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_CLINT);
245	qdev_prop_set_uint32(dev, "num-harts", num_harts);
246	qdev_prop_set_uint32(dev, "sip-base", sip_base);
247	qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
248	qdev_prop_set_uint32(dev, "time-base", time_base);
249	qdev_prop_set_uint32(dev, "aperture-size", size);
250	qdev_init_nofail(dev);
251	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
252	return dev;
253	}