[qemu.git] / hw / slavio_misc.c

/*
 * QEMU Sparc SLAVIO aux io port emulation
 *
 * Copyright (c) 2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "sun4m.h"
#include "sysemu.h"

/* debug misc */
//#define DEBUG_MISC

/*
 * This is the auxio port, chip control and system control part of
 * chip STP2001 (Slave I/O), also produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * This also includes the PMC CPU idle controller.
 */

#ifdef DEBUG_MISC
#define MISC_DPRINTF(fmt, ...)                                  \
    do { printf("MISC: " fmt , ## __VA_ARGS__); } while (0)
#else
#define MISC_DPRINTF(fmt, ...)
#endif

typedef struct MiscState {
    qemu_irq irq;
    uint8_t config;
    uint8_t aux1, aux2;
    uint8_t diag, mctrl;
    uint32_t sysctrl;
    uint16_t leds;
    qemu_irq cpu_halt;
    qemu_irq fdc_tc;
} MiscState;

#define MISC_SIZE 1
#define SYSCTRL_SIZE 4

#define MISC_LEDS 0x01600000
#define MISC_CFG  0x01800000
#define MISC_DIAG 0x01a00000
#define MISC_MDM  0x01b00000
#define MISC_SYS  0x01f00000

#define AUX1_TC        0x02

#define AUX2_PWROFF    0x01
#define AUX2_PWRINTCLR 0x02
#define AUX2_PWRFAIL   0x20

#define CFG_PWRINTEN   0x08

#define SYS_RESET      0x01
#define SYS_RESETSTAT  0x02

static void slavio_misc_update_irq(void *opaque)
{
    MiscState *s = opaque;

    if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
        MISC_DPRINTF("Raise IRQ\n");
        qemu_irq_raise(s->irq);
    } else {
        MISC_DPRINTF("Lower IRQ\n");
        qemu_irq_lower(s->irq);
    }
}

static void slavio_misc_reset(void *opaque)
{
    MiscState *s = opaque;

    // Diagnostic and system control registers not cleared in reset
    s->config = s->aux1 = s->aux2 = s->mctrl = 0;
}

void slavio_set_power_fail(void *opaque, int power_failing)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
    if (power_failing && (s->config & CFG_PWRINTEN)) {
        s->aux2 |= AUX2_PWRFAIL;
    } else {
        s->aux2 &= ~AUX2_PWRFAIL;
    }
    slavio_misc_update_irq(s);
}

static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
    s->config = val & 0xff;
    slavio_misc_update_irq(s);
}

static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->config;
    MISC_DPRINTF("Read config %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc *slavio_cfg_mem_read[3] = {
    slavio_cfg_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *slavio_cfg_mem_write[3] = {
    slavio_cfg_mem_writeb,
    NULL,
    NULL,
};

static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
    s->diag = val & 0xff;
}

static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->diag;
    MISC_DPRINTF("Read diag %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc *slavio_diag_mem_read[3] = {
    slavio_diag_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *slavio_diag_mem_write[3] = {
    slavio_diag_mem_writeb,
    NULL,
    NULL,
};

static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
    s->mctrl = val & 0xff;
}

static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->mctrl;
    MISC_DPRINTF("Read modem control %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc *slavio_mdm_mem_read[3] = {
    slavio_mdm_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *slavio_mdm_mem_write[3] = {
    slavio_mdm_mem_writeb,
    NULL,
    NULL,
};

static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
    if (val & AUX1_TC) {
        // Send a pulse to floppy terminal count line
        if (s->fdc_tc) {
            qemu_irq_raise(s->fdc_tc);
            qemu_irq_lower(s->fdc_tc);
        }
        val &= ~AUX1_TC;
    }
    s->aux1 = val & 0xff;
}

static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->aux1;
    MISC_DPRINTF("Read aux1 %2.2x\n", ret);

    return ret;
}

static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = {
    slavio_aux1_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = {
    slavio_aux1_mem_writeb,
    NULL,
    NULL,
};

static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    val &= AUX2_PWRINTCLR | AUX2_PWROFF;
    MISC_DPRINTF("Write aux2 %2.2x\n", val);
    val |= s->aux2 & AUX2_PWRFAIL;
    if (val & AUX2_PWRINTCLR) // Clear Power Fail int
        val &= AUX2_PWROFF;
    s->aux2 = val;
    if (val & AUX2_PWROFF)
        qemu_system_shutdown_request();
    slavio_misc_update_irq(s);
}

static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->aux2;
    MISC_DPRINTF("Read aux2 %2.2x\n", ret);

    return ret;
}

static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = {
    slavio_aux2_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = {
    slavio_aux2_mem_writeb,
    NULL,
    NULL,
};

static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
    qemu_irq_raise(s->cpu_halt);
}

static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
{
    uint32_t ret = 0;

    MISC_DPRINTF("Read power management %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc *apc_mem_read[3] = {
    apc_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *apc_mem_write[3] = {
    apc_mem_writeb,
    NULL,
    NULL,
};

static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    switch (addr) {
    case 0:
        ret = s->sysctrl;
        break;
    default:
        break;
    }
    MISC_DPRINTF("Read system control %08x\n", ret);
    return ret;
}

static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
                                      uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write system control %08x\n", val);
    switch (addr) {
    case 0:
        if (val & SYS_RESET) {
            s->sysctrl = SYS_RESETSTAT;
            qemu_system_reset_request();
        }
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = {
    NULL,
    NULL,
    slavio_sysctrl_mem_readl,
};

static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
    NULL,
    NULL,
    slavio_sysctrl_mem_writel,
};

static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    switch (addr) {
    case 0:
        ret = s->leds;
        break;
    default:
        break;
    }
    MISC_DPRINTF("Read diagnostic LED %04x\n", ret);
    return ret;
}

static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write diagnostic LED %04x\n", val & 0xffff);
    switch (addr) {
    case 0:
        s->leds = val;
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc *slavio_led_mem_read[3] = {
    NULL,
    slavio_led_mem_readw,
    NULL,
};

static CPUWriteMemoryFunc *slavio_led_mem_write[3] = {
    NULL,
    slavio_led_mem_writew,
    NULL,
};

static void slavio_misc_save(QEMUFile *f, void *opaque)
{
    MiscState *s = opaque;
    uint32_t tmp = 0;
    uint8_t tmp8;

    qemu_put_be32s(f, &tmp); /* ignored, was IRQ.  */
    qemu_put_8s(f, &s->config);
    qemu_put_8s(f, &s->aux1);
    qemu_put_8s(f, &s->aux2);
    qemu_put_8s(f, &s->diag);
    qemu_put_8s(f, &s->mctrl);
    tmp8 = s->sysctrl & 0xff;
    qemu_put_8s(f, &tmp8);
}

static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
{
    MiscState *s = opaque;
    uint32_t tmp;
    uint8_t tmp8;

    if (version_id != 1)
        return -EINVAL;

    qemu_get_be32s(f, &tmp);
    qemu_get_8s(f, &s->config);
    qemu_get_8s(f, &s->aux1);
    qemu_get_8s(f, &s->aux2);
    qemu_get_8s(f, &s->diag);
    qemu_get_8s(f, &s->mctrl);
    qemu_get_8s(f, &tmp8);
    s->sysctrl = (uint32_t)tmp8;
    return 0;
}

void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
                       target_phys_addr_t aux1_base,
                       target_phys_addr_t aux2_base, qemu_irq irq,
                       qemu_irq cpu_halt, qemu_irq **fdc_tc)
{
    int io;
    MiscState *s;

    s = qemu_mallocz(sizeof(MiscState));

    if (base) {
        /* 8 bit registers */

        // Slavio control
        io = cpu_register_io_memory(slavio_cfg_mem_read,
                                    slavio_cfg_mem_write, s);
        cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io);

        // Diagnostics
        io = cpu_register_io_memory(slavio_diag_mem_read,
                                    slavio_diag_mem_write, s);
        cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io);

        // Modem control
        io = cpu_register_io_memory(slavio_mdm_mem_read,
                                    slavio_mdm_mem_write, s);
        cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io);

        /* 16 bit registers */
        io = cpu_register_io_memory(slavio_led_mem_read,
                                    slavio_led_mem_write, s);
        /* ss600mp diag LEDs */
        cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE, io);

        /* 32 bit registers */
        io = cpu_register_io_memory(slavio_sysctrl_mem_read,
                                    slavio_sysctrl_mem_write, s);
        // System control
        cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE, io);
    }

    // AUX 1 (Misc System Functions)
    if (aux1_base) {
        io = cpu_register_io_memory(slavio_aux1_mem_read,
                                    slavio_aux1_mem_write, s);
        cpu_register_physical_memory(aux1_base, MISC_SIZE, io);
    }

    // AUX 2 (Software Powerdown Control)
    if (aux2_base) {
        io = cpu_register_io_memory(slavio_aux2_mem_read,
                                    slavio_aux2_mem_write, s);
        cpu_register_physical_memory(aux2_base, MISC_SIZE, io);
    }

    // Power management (APC) XXX: not a Slavio device
    if (power_base) {
        io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s);
        cpu_register_physical_memory(power_base, MISC_SIZE, io);
    }

    s->irq = irq;
    s->cpu_halt = cpu_halt;
    *fdc_tc = &s->fdc_tc;

    register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
                    s);
    qemu_register_reset(slavio_misc_reset, s);
    slavio_misc_reset(s);

    return s;
}
Commit	Line	Data
3475187d FB	1	/*
3475187d FB	2	* QEMU Sparc SLAVIO aux io port emulation
5fafdf24	3	*
3475187d	4	* Copyright (c) 2005 Fabrice Bellard
5fafdf24	5	*
3475187d FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "sun4m.h"
	26	#include "sysemu.h"
	27
3475187d FB	28	/* debug misc */
	29	//#define DEBUG_MISC
	30
	31	/*
	32	* This is the auxio port, chip control and system control part of
	33	* chip STP2001 (Slave I/O), also produced as NCR89C105. See
	34	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
	35	*
	36	* This also includes the PMC CPU idle controller.
	37	*/
	38
	39	#ifdef DEBUG_MISC
001faf32 BS	40	#define MISC_DPRINTF(fmt, ...) \
001faf32 BS	41	do { printf("MISC: " fmt , ## __VA_ARGS__); } while (0)
3475187d	42	#else
001faf32	43	#define MISC_DPRINTF(fmt, ...)
3475187d FB	44	#endif
	45
	46	typedef struct MiscState {
d537cf6c	47	qemu_irq irq;
3475187d FB	48	uint8_t config;
3475187d FB	49	uint8_t aux1, aux2;
bfa30a38 BS	50	uint8_t diag, mctrl;
bfa30a38 BS	51	uint32_t sysctrl;
6a3b9cc9	52	uint16_t leds;
6d0c293d	53	qemu_irq cpu_halt;
2be17ebd	54	qemu_irq fdc_tc;
3475187d FB	55	} MiscState;
3475187d FB	56
5aca8c3b	57	#define MISC_SIZE 1
a8f48dcc	58	#define SYSCTRL_SIZE 4
3475187d	59
7debeb82 BS	60	#define MISC_LEDS 0x01600000
7debeb82 BS	61	#define MISC_CFG 0x01800000
7debeb82 BS	62	#define MISC_DIAG 0x01a00000
	63	#define MISC_MDM 0x01b00000
	64	#define MISC_SYS 0x01f00000
7debeb82	65
2be17ebd BS	66	#define AUX1_TC 0x02
2be17ebd BS	67
7debeb82 BS	68	#define AUX2_PWROFF 0x01
	69	#define AUX2_PWRINTCLR 0x02
	70	#define AUX2_PWRFAIL 0x20
	71
	72	#define CFG_PWRINTEN 0x08
	73
	74	#define SYS_RESET 0x01
	75	#define SYS_RESETSTAT 0x02
	76
3475187d FB	77	static void slavio_misc_update_irq(void *opaque)
	78	{
	79	MiscState *s = opaque;
	80
7debeb82	81	if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
d537cf6c PB	82	MISC_DPRINTF("Raise IRQ\n");
d537cf6c PB	83	qemu_irq_raise(s->irq);
3475187d	84	} else {
d537cf6c PB	85	MISC_DPRINTF("Lower IRQ\n");
d537cf6c PB	86	qemu_irq_lower(s->irq);
3475187d FB	87	}
	88	}
	89
	90	static void slavio_misc_reset(void *opaque)
	91	{
	92	MiscState *s = opaque;
	93
4e3b1ea1	94	// Diagnostic and system control registers not cleared in reset
3475187d FB	95	s->config = s->aux1 = s->aux2 = s->mctrl = 0;
	96	}
	97
	98	void slavio_set_power_fail(void *opaque, int power_failing)
	99	{
	100	MiscState *s = opaque;
	101
	102	MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
7debeb82 BS	103	if (power_failing && (s->config & CFG_PWRINTEN)) {
7debeb82 BS	104	s->aux2 \|= AUX2_PWRFAIL;
3475187d	105	} else {
7debeb82	106	s->aux2 &= ~AUX2_PWRFAIL;
3475187d FB	107	}
	108	slavio_misc_update_irq(s);
	109	}
	110
a8f48dcc BS	111	static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
	112	uint32_t val)
	113	{
	114	MiscState *s = opaque;
	115
	116	MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
	117	s->config = val & 0xff;
	118	slavio_misc_update_irq(s);
	119	}
	120
	121	static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
	122	{
	123	MiscState *s = opaque;
	124	uint32_t ret = 0;
	125
	126	ret = s->config;
	127	MISC_DPRINTF("Read config %2.2x\n", ret);
	128	return ret;
	129	}
	130
	131	static CPUReadMemoryFunc *slavio_cfg_mem_read[3] = {
	132	slavio_cfg_mem_readb,
	133	NULL,
	134	NULL,
	135	};
	136
	137	static CPUWriteMemoryFunc *slavio_cfg_mem_write[3] = {
	138	slavio_cfg_mem_writeb,
	139	NULL,
	140	NULL,
	141	};
	142
	143	static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
bfa30a38	144	uint32_t val)
3475187d FB	145	{
	146	MiscState *s = opaque;
	147
a8f48dcc BS	148	MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
a8f48dcc BS	149	s->diag = val & 0xff;
3475187d FB	150	}
3475187d FB	151
a8f48dcc	152	static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr)
3475187d FB	153	{
	154	MiscState *s = opaque;
	155	uint32_t ret = 0;
	156
a8f48dcc BS	157	ret = s->diag;
	158	MISC_DPRINTF("Read diag %2.2x\n", ret);
	159	return ret;
	160	}
	161
	162	static CPUReadMemoryFunc *slavio_diag_mem_read[3] = {
	163	slavio_diag_mem_readb,
	164	NULL,
	165	NULL,
	166	};
	167
	168	static CPUWriteMemoryFunc *slavio_diag_mem_write[3] = {
	169	slavio_diag_mem_writeb,
	170	NULL,
	171	NULL,
	172	};
	173
	174	static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
	175	uint32_t val)
	176	{
	177	MiscState *s = opaque;
	178
	179	MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
	180	s->mctrl = val & 0xff;
	181	}
	182
	183	static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr)
	184	{
	185	MiscState *s = opaque;
	186	uint32_t ret = 0;
	187
	188	ret = s->mctrl;
	189	MISC_DPRINTF("Read modem control %2.2x\n", ret);
3475187d FB	190	return ret;
	191	}
	192
a8f48dcc BS	193	static CPUReadMemoryFunc *slavio_mdm_mem_read[3] = {
a8f48dcc BS	194	slavio_mdm_mem_readb,
7c560456 BS	195	NULL,
7c560456 BS	196	NULL,
3475187d FB	197	};
3475187d FB	198
a8f48dcc BS	199	static CPUWriteMemoryFunc *slavio_mdm_mem_write[3] = {
a8f48dcc BS	200	slavio_mdm_mem_writeb,
7c560456 BS	201	NULL,
7c560456 BS	202	NULL,
3475187d FB	203	};
3475187d FB	204
0019ad53 BS	205	static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
	206	uint32_t val)
	207	{
	208	MiscState *s = opaque;
	209
	210	MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
2be17ebd BS	211	if (val & AUX1_TC) {
	212	// Send a pulse to floppy terminal count line
	213	if (s->fdc_tc) {
	214	qemu_irq_raise(s->fdc_tc);
	215	qemu_irq_lower(s->fdc_tc);
	216	}
	217	val &= ~AUX1_TC;
	218	}
0019ad53 BS	219	s->aux1 = val & 0xff;
	220	}
	221
	222	static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
	223	{
	224	MiscState *s = opaque;
	225	uint32_t ret = 0;
	226
	227	ret = s->aux1;
	228	MISC_DPRINTF("Read aux1 %2.2x\n", ret);
	229
	230	return ret;
	231	}
	232
	233	static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = {
	234	slavio_aux1_mem_readb,
	235	NULL,
	236	NULL,
	237	};
	238
	239	static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = {
	240	slavio_aux1_mem_writeb,
	241	NULL,
	242	NULL,
	243	};
	244
	245	static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
	246	uint32_t val)
	247	{
	248	MiscState *s = opaque;
	249
	250	val &= AUX2_PWRINTCLR \| AUX2_PWROFF;
	251	MISC_DPRINTF("Write aux2 %2.2x\n", val);
	252	val \|= s->aux2 & AUX2_PWRFAIL;
	253	if (val & AUX2_PWRINTCLR) // Clear Power Fail int
	254	val &= AUX2_PWROFF;
	255	s->aux2 = val;
	256	if (val & AUX2_PWROFF)
	257	qemu_system_shutdown_request();
	258	slavio_misc_update_irq(s);
	259	}
	260
	261	static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
	262	{
	263	MiscState *s = opaque;
	264	uint32_t ret = 0;
	265
	266	ret = s->aux2;
	267	MISC_DPRINTF("Read aux2 %2.2x\n", ret);
	268
	269	return ret;
	270	}
	271
	272	static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = {
	273	slavio_aux2_mem_readb,
	274	NULL,
	275	NULL,
	276	};
	277
	278	static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = {
	279	slavio_aux2_mem_writeb,
	280	NULL,
	281	NULL,
	282	};
283
284	static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
285	{
286	MiscState *s = opaque;
287
288	MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
6d0c293d	289	qemu_irq_raise(s->cpu_halt);
0019ad53 BS	290	}
	291
	292	static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
	293	{
	294	uint32_t ret = 0;
	295
	296	MISC_DPRINTF("Read power management %2.2x\n", ret);
	297	return ret;
	298	}
	299
	300	static CPUReadMemoryFunc *apc_mem_read[3] = {
	301	apc_mem_readb,
	302	NULL,
	303	NULL,
	304	};
	305
	306	static CPUWriteMemoryFunc *apc_mem_write[3] = {
	307	apc_mem_writeb,
	308	NULL,
	309	NULL,
	310	};
	311
bfa30a38 BS	312	static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
	313	{
	314	MiscState *s = opaque;
a8f48dcc	315	uint32_t ret = 0;
bfa30a38	316
a8f48dcc	317	switch (addr) {
bfa30a38 BS	318	case 0:
	319	ret = s->sysctrl;
	320	break;
	321	default:
	322	break;
	323	}
5626b017	324	MISC_DPRINTF("Read system control %08x\n", ret);
bfa30a38 BS	325	return ret;
	326	}
	327
	328	static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
	329	uint32_t val)
	330	{
	331	MiscState *s = opaque;
bfa30a38	332
5626b017	333	MISC_DPRINTF("Write system control %08x\n", val);
a8f48dcc	334	switch (addr) {
bfa30a38	335	case 0:
7debeb82 BS	336	if (val & SYS_RESET) {
7debeb82 BS	337	s->sysctrl = SYS_RESETSTAT;
bfa30a38 BS	338	qemu_system_reset_request();
	339	}
	340	break;
	341	default:
	342	break;
	343	}
	344	}
	345
	346	static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = {
7c560456 BS	347	NULL,
7c560456 BS	348	NULL,
bfa30a38 BS	349	slavio_sysctrl_mem_readl,
	350	};
	351
	352	static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
7c560456 BS	353	NULL,
7c560456 BS	354	NULL,
bfa30a38 BS	355	slavio_sysctrl_mem_writel,
	356	};
	357
7c560456	358	static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
6a3b9cc9 BS	359	{
6a3b9cc9 BS	360	MiscState *s = opaque;
a8f48dcc	361	uint32_t ret = 0;
6a3b9cc9	362
a8f48dcc	363	switch (addr) {
6a3b9cc9 BS	364	case 0:
	365	ret = s->leds;
	366	break;
	367	default:
	368	break;
	369	}
5626b017	370	MISC_DPRINTF("Read diagnostic LED %04x\n", ret);
6a3b9cc9 BS	371	return ret;
	372	}
	373
7c560456	374	static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
6a3b9cc9 BS	375	uint32_t val)
	376	{
	377	MiscState *s = opaque;
6a3b9cc9	378
5626b017	379	MISC_DPRINTF("Write diagnostic LED %04x\n", val & 0xffff);
a8f48dcc	380	switch (addr) {
6a3b9cc9	381	case 0:
d5296cb5	382	s->leds = val;
6a3b9cc9 BS	383	break;
	384	default:
	385	break;
	386	}
	387	}
	388
	389	static CPUReadMemoryFunc *slavio_led_mem_read[3] = {
7c560456 BS	390	NULL,
	391	slavio_led_mem_readw,
	392	NULL,
6a3b9cc9 BS	393	};
	394
	395	static CPUWriteMemoryFunc *slavio_led_mem_write[3] = {
7c560456 BS	396	NULL,
	397	slavio_led_mem_writew,
	398	NULL,
6a3b9cc9 BS	399	};
6a3b9cc9 BS	400
3475187d FB	401	static void slavio_misc_save(QEMUFile f, void opaque)
	402	{
	403	MiscState *s = opaque;
22548760	404	uint32_t tmp = 0;
bfa30a38	405	uint8_t tmp8;
3475187d	406
d537cf6c	407	qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
3475187d FB	408	qemu_put_8s(f, &s->config);
	409	qemu_put_8s(f, &s->aux1);
	410	qemu_put_8s(f, &s->aux2);
	411	qemu_put_8s(f, &s->diag);
	412	qemu_put_8s(f, &s->mctrl);
bfa30a38 BS	413	tmp8 = s->sysctrl & 0xff;
bfa30a38 BS	414	qemu_put_8s(f, &tmp8);
3475187d FB	415	}
	416
	417	static int slavio_misc_load(QEMUFile f, void opaque, int version_id)
	418	{
	419	MiscState *s = opaque;
22548760	420	uint32_t tmp;
bfa30a38	421	uint8_t tmp8;
3475187d FB	422
	423	if (version_id != 1)
	424	return -EINVAL;
	425
d537cf6c	426	qemu_get_be32s(f, &tmp);
3475187d FB	427	qemu_get_8s(f, &s->config);
	428	qemu_get_8s(f, &s->aux1);
	429	qemu_get_8s(f, &s->aux2);
	430	qemu_get_8s(f, &s->diag);
	431	qemu_get_8s(f, &s->mctrl);
bfa30a38 BS	432	qemu_get_8s(f, &tmp8);
bfa30a38 BS	433	s->sysctrl = (uint32_t)tmp8;
3475187d FB	434	return 0;
	435	}
	436
5dcb6b91	437	void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
0019ad53 BS	438	target_phys_addr_t aux1_base,
0019ad53 BS	439	target_phys_addr_t aux2_base, qemu_irq irq,
6d0c293d	440	qemu_irq cpu_halt, qemu_irq **fdc_tc)
3475187d	441	{
0019ad53	442	int io;
3475187d FB	443	MiscState *s;
	444
	445	s = qemu_mallocz(sizeof(MiscState));
3475187d	446
0019ad53 BS	447	if (base) {
0019ad53 BS	448	/* 8 bit registers */
a8f48dcc	449
0019ad53	450	// Slavio control
1eed09cb	451	io = cpu_register_io_memory(slavio_cfg_mem_read,
a8f48dcc BS	452	slavio_cfg_mem_write, s);
	453	cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io);
	454
0019ad53	455	// Diagnostics
1eed09cb	456	io = cpu_register_io_memory(slavio_diag_mem_read,
a8f48dcc BS	457	slavio_diag_mem_write, s);
	458	cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io);
	459
0019ad53	460	// Modem control
1eed09cb	461	io = cpu_register_io_memory(slavio_mdm_mem_read,
a8f48dcc BS	462	slavio_mdm_mem_write, s);
a8f48dcc BS	463	cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io);
0019ad53 BS	464
0019ad53 BS	465	/* 16 bit registers */
1eed09cb	466	io = cpu_register_io_memory(slavio_led_mem_read,
0019ad53 BS	467	slavio_led_mem_write, s);
	468	/* ss600mp diag LEDs */
	469	cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE, io);
	470
	471	/* 32 bit registers */
1eed09cb	472	io = cpu_register_io_memory(slavio_sysctrl_mem_read,
0019ad53 BS	473	slavio_sysctrl_mem_write, s);
	474	// System control
	475	cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE, io);
	476	}
	477
	478	// AUX 1 (Misc System Functions)
	479	if (aux1_base) {
1eed09cb	480	io = cpu_register_io_memory(slavio_aux1_mem_read,
0019ad53 BS	481	slavio_aux1_mem_write, s);
	482	cpu_register_physical_memory(aux1_base, MISC_SIZE, io);
	483	}
	484
	485	// AUX 2 (Software Powerdown Control)
	486	if (aux2_base) {
1eed09cb	487	io = cpu_register_io_memory(slavio_aux2_mem_read,
0019ad53 BS	488	slavio_aux2_mem_write, s);
	489	cpu_register_physical_memory(aux2_base, MISC_SIZE, io);
	490	}
	491
	492	// Power management (APC) XXX: not a Slavio device
	493	if (power_base) {
1eed09cb	494	io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s);
0019ad53 BS	495	cpu_register_physical_memory(power_base, MISC_SIZE, io);
0019ad53 BS	496	}
bfa30a38	497
3475187d	498	s->irq = irq;
6d0c293d	499	s->cpu_halt = cpu_halt;
2be17ebd	500	*fdc_tc = &s->fdc_tc;
3475187d	501
bfa30a38 BS	502	register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
bfa30a38 BS	503	s);
a08d4367	504	qemu_register_reset(slavio_misc_reset, s);
3475187d	505	slavio_misc_reset(s);
0019ad53	506
3475187d FB	507	return s;
3475187d FB	508	}