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cd71c089 LV |
1 | /* |
2 | * qemu user cpu loop | |
3 | * | |
4 | * Copyright (c) 2003-2008 Fabrice Bellard | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu.h" | |
3b249d26 | 22 | #include "user-internals.h" |
cd71c089 | 23 | #include "cpu_loop-common.h" |
2113aed6 | 24 | #include "signal-common.h" |
cd71c089 | 25 | |
82e8e645 LV |
26 | void cpu_loop(CPUMBState *env) |
27 | { | |
f5c7e93a | 28 | CPUState *cs = env_cpu(env); |
23ae825a RH |
29 | int trapnr, ret, si_code; |
30 | ||
82e8e645 LV |
31 | while (1) { |
32 | cpu_exec_start(cs); | |
33 | trapnr = cpu_exec(cs); | |
34 | cpu_exec_end(cs); | |
35 | process_queued_cpu_work(cs); | |
36 | ||
37 | switch (trapnr) { | |
82e8e645 | 38 | case EXCP_INTERRUPT: |
23ae825a RH |
39 | /* just indicate that signals should be handled asap */ |
40 | break; | |
f5235314 | 41 | case EXCP_SYSCALL: |
82e8e645 LV |
42 | /* Return address is 4 bytes after the call. */ |
43 | env->regs[14] += 4; | |
76e8187d | 44 | env->pc = env->regs[14]; |
82e8e645 LV |
45 | ret = do_syscall(env, |
46 | env->regs[12], | |
47 | env->regs[5], | |
48 | env->regs[6], | |
49 | env->regs[7], | |
50 | env->regs[8], | |
51 | env->regs[9], | |
52 | env->regs[10], | |
53 | 0, 0); | |
af254a27 | 54 | if (ret == -QEMU_ERESTARTSYS) { |
82e8e645 | 55 | /* Wind back to before the syscall. */ |
76e8187d | 56 | env->pc -= 4; |
57a0c938 | 57 | } else if (ret != -QEMU_ESIGRETURN) { |
82e8e645 LV |
58 | env->regs[3] = ret; |
59 | } | |
60 | /* All syscall exits result in guest r14 being equal to the | |
61 | * PC we return to, because the kernel syscall exit "rtbd" does | |
62 | * this. (This is true even for sigreturn(); note that r14 is | |
63 | * not a userspace-usable register, as the kernel may clobber it | |
64 | * at any point.) | |
65 | */ | |
76e8187d | 66 | env->regs[14] = env->pc; |
82e8e645 | 67 | break; |
23ae825a | 68 | |
82e8e645 | 69 | case EXCP_HW_EXCP: |
76e8187d | 70 | env->regs[17] = env->pc + 4; |
82e8e645 | 71 | if (env->iflags & D_FLAG) { |
78e9caf2 | 72 | env->esr |= 1 << 12; |
76e8187d | 73 | env->pc -= 4; |
82e8e645 LV |
74 | /* FIXME: if branch was immed, replay the imm as well. */ |
75 | } | |
82e8e645 | 76 | env->iflags &= ~(IMM_FLAG | D_FLAG); |
78e9caf2 | 77 | switch (env->esr & 31) { |
23ae825a | 78 | case ESR_EC_DIVZERO: |
0b25c4a1 | 79 | si_code = TARGET_FPE_INTDIV; |
23ae825a RH |
80 | break; |
81 | case ESR_EC_FPU: | |
0b25c4a1 RH |
82 | /* |
83 | * Note that the kernel passes along fsr as si_code | |
84 | * if there's no recognized bit set. Possibly this | |
85 | * implies that si_code is 0, but follow the structure. | |
86 | */ | |
87 | si_code = env->fsr; | |
88 | if (si_code & FSR_IO) { | |
23ae825a | 89 | si_code = TARGET_FPE_FLTINV; |
0b25c4a1 RH |
90 | } else if (si_code & FSR_OF) { |
91 | si_code = TARGET_FPE_FLTOVF; | |
92 | } else if (si_code & FSR_UF) { | |
93 | si_code = TARGET_FPE_FLTUND; | |
94 | } else if (si_code & FSR_DZ) { | |
23ae825a | 95 | si_code = TARGET_FPE_FLTDIV; |
0b25c4a1 RH |
96 | } else if (si_code & FSR_DO) { |
97 | si_code = TARGET_FPE_FLTRES; | |
23ae825a RH |
98 | } |
99 | break; | |
100 | default: | |
101 | fprintf(stderr, "Unhandled hw-exception: 0x%x\n", | |
102 | env->esr & ESR_EC_MASK); | |
103 | cpu_dump_state(cs, stderr, 0); | |
104 | exit(EXIT_FAILURE); | |
82e8e645 | 105 | } |
23ae825a | 106 | force_sig_fault(TARGET_SIGFPE, si_code, env->pc); |
82e8e645 | 107 | break; |
23ae825a | 108 | |
82e8e645 | 109 | case EXCP_DEBUG: |
23ae825a | 110 | force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc); |
82e8e645 LV |
111 | break; |
112 | case EXCP_ATOMIC: | |
113 | cpu_exec_step_atomic(cs); | |
114 | break; | |
115 | default: | |
84ca4fa9 | 116 | fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr); |
90c84c56 | 117 | cpu_dump_state(cs, stderr, 0); |
82e8e645 LV |
118 | exit(EXIT_FAILURE); |
119 | } | |
120 | process_pending_signals (env); | |
121 | } | |
122 | } | |
123 | ||
cd71c089 LV |
124 | void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) |
125 | { | |
82e8e645 LV |
126 | env->regs[0] = regs->r0; |
127 | env->regs[1] = regs->r1; | |
128 | env->regs[2] = regs->r2; | |
129 | env->regs[3] = regs->r3; | |
130 | env->regs[4] = regs->r4; | |
131 | env->regs[5] = regs->r5; | |
132 | env->regs[6] = regs->r6; | |
133 | env->regs[7] = regs->r7; | |
134 | env->regs[8] = regs->r8; | |
135 | env->regs[9] = regs->r9; | |
136 | env->regs[10] = regs->r10; | |
137 | env->regs[11] = regs->r11; | |
138 | env->regs[12] = regs->r12; | |
139 | env->regs[13] = regs->r13; | |
140 | env->regs[14] = regs->r14; | |
141 | env->regs[15] = regs->r15; | |
142 | env->regs[16] = regs->r16; | |
143 | env->regs[17] = regs->r17; | |
144 | env->regs[18] = regs->r18; | |
145 | env->regs[19] = regs->r19; | |
146 | env->regs[20] = regs->r20; | |
147 | env->regs[21] = regs->r21; | |
148 | env->regs[22] = regs->r22; | |
149 | env->regs[23] = regs->r23; | |
150 | env->regs[24] = regs->r24; | |
151 | env->regs[25] = regs->r25; | |
152 | env->regs[26] = regs->r26; | |
153 | env->regs[27] = regs->r27; | |
154 | env->regs[28] = regs->r28; | |
155 | env->regs[29] = regs->r29; | |
156 | env->regs[30] = regs->r30; | |
157 | env->regs[31] = regs->r31; | |
76e8187d | 158 | env->pc = regs->pc; |
cd71c089 | 159 | } |