[qemu.git] / hw / ssi / omap_spi.c

/*
 * TI OMAP processor's Multichannel SPI emulation.
 *
 * Copyright (C) 2007-2009 Nokia Corporation
 *
 * Original code for OMAP2 by Andrzej Zaborowski <[email protected]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 or
 * (at your option) any later version of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/hw.h"
#include "hw/irq.h"
#include "hw/arm/omap.h"

/* Multichannel SPI */
struct omap_mcspi_s {
    MemoryRegion iomem;
    qemu_irq irq;
    int chnum;

    uint32_t sysconfig;
    uint32_t systest;
    uint32_t irqst;
    uint32_t irqen;
    uint32_t wken;
    uint32_t control;

    struct omap_mcspi_ch_s {
        qemu_irq txdrq;
        qemu_irq rxdrq;
        uint32_t (*txrx)(void *opaque, uint32_t, int);
        void *opaque;

        uint32_t tx;
        uint32_t rx;

        uint32_t config;
        uint32_t status;
        uint32_t control;
    } ch[4];
};

static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
{
    qemu_set_irq(s->irq, s->irqst & s->irqen);
}

static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
{
    qemu_set_irq(ch->txdrq,
                    (ch->control & 1) &&		/* EN */
                    (ch->config & (1 << 14)) &&		/* DMAW */
                    (ch->status & (1 << 1)) &&		/* TXS */
                    ((ch->config >> 12) & 3) != 1);	/* TRM */
    qemu_set_irq(ch->rxdrq,
                    (ch->control & 1) &&		/* EN */
                    (ch->config & (1 << 15)) &&		/* DMAW */
                    (ch->status & (1 << 0)) &&		/* RXS */
                    ((ch->config >> 12) & 3) != 2);	/* TRM */
}

static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
{
    struct omap_mcspi_ch_s *ch = s->ch + chnum;

    if (!(ch->control & 1))				/* EN */
        return;
    if ((ch->status & (1 << 0)) &&			/* RXS */
                    ((ch->config >> 12) & 3) != 2 &&	/* TRM */
                    !(ch->config & (1 << 19)))		/* TURBO */
        goto intr_update;
    if ((ch->status & (1 << 1)) &&			/* TXS */
                    ((ch->config >> 12) & 3) != 1)	/* TRM */
        goto intr_update;

    if (!(s->control & 1) ||				/* SINGLE */
                    (ch->config & (1 << 20))) {		/* FORCE */
        if (ch->txrx)
            ch->rx = ch->txrx(ch->opaque, ch->tx,	/* WL */
                            1 + (0x1f & (ch->config >> 7)));
    }

    ch->tx = 0;
    ch->status |= 1 << 2;				/* EOT */
    ch->status |= 1 << 1;				/* TXS */
    if (((ch->config >> 12) & 3) != 2)			/* TRM */
        ch->status |= 1 << 0;				/* RXS */

intr_update:
    if ((ch->status & (1 << 0)) &&			/* RXS */
                    ((ch->config >> 12) & 3) != 2 &&	/* TRM */
                    !(ch->config & (1 << 19)))		/* TURBO */
        s->irqst |= 1 << (2 + 4 * chnum);		/* RX_FULL */
    if ((ch->status & (1 << 1)) &&			/* TXS */
                    ((ch->config >> 12) & 3) != 1)	/* TRM */
        s->irqst |= 1 << (0 + 4 * chnum);		/* TX_EMPTY */
    omap_mcspi_interrupt_update(s);
    omap_mcspi_dmarequest_update(ch);
}

void omap_mcspi_reset(struct omap_mcspi_s *s)
{
    int ch;

    s->sysconfig = 0;
    s->systest = 0;
    s->irqst = 0;
    s->irqen = 0;
    s->wken = 0;
    s->control = 4;

    for (ch = 0; ch < 4; ch ++) {
        s->ch[ch].config = 0x060000;
        s->ch[ch].status = 2;				/* TXS */
        s->ch[ch].control = 0;

        omap_mcspi_dmarequest_update(s->ch + ch);
    }

    omap_mcspi_interrupt_update(s);
}

static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
                                unsigned size)
{
    struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
    int ch = 0;
    uint32_t ret;

    if (size != 4) {
        return omap_badwidth_read32(opaque, addr);
    }

    switch (addr) {
    case 0x00:	/* MCSPI_REVISION */
        return 0x91;

    case 0x10:	/* MCSPI_SYSCONFIG */
        return s->sysconfig;

    case 0x14:	/* MCSPI_SYSSTATUS */
        return 1;					/* RESETDONE */

    case 0x18:	/* MCSPI_IRQSTATUS */
        return s->irqst;

    case 0x1c:	/* MCSPI_IRQENABLE */
        return s->irqen;

    case 0x20:	/* MCSPI_WAKEUPENABLE */
        return s->wken;

    case 0x24:	/* MCSPI_SYST */
        return s->systest;

    case 0x28:	/* MCSPI_MODULCTRL */
        return s->control;

    case 0x68: ch ++;
        /* fall through */
    case 0x54: ch ++;
        /* fall through */
    case 0x40: ch ++;
        /* fall through */
    case 0x2c:	/* MCSPI_CHCONF */
        return s->ch[ch].config;

    case 0x6c: ch ++;
        /* fall through */
    case 0x58: ch ++;
        /* fall through */
    case 0x44: ch ++;
        /* fall through */
    case 0x30:	/* MCSPI_CHSTAT */
        return s->ch[ch].status;

    case 0x70: ch ++;
        /* fall through */
    case 0x5c: ch ++;
        /* fall through */
    case 0x48: ch ++;
        /* fall through */
    case 0x34:	/* MCSPI_CHCTRL */
        return s->ch[ch].control;

    case 0x74: ch ++;
        /* fall through */
    case 0x60: ch ++;
        /* fall through */
    case 0x4c: ch ++;
        /* fall through */
    case 0x38:	/* MCSPI_TX */
        return s->ch[ch].tx;

    case 0x78: ch ++;
        /* fall through */
    case 0x64: ch ++;
        /* fall through */
    case 0x50: ch ++;
        /* fall through */
    case 0x3c:	/* MCSPI_RX */
        s->ch[ch].status &= ~(1 << 0);			/* RXS */
        ret = s->ch[ch].rx;
        omap_mcspi_transfer_run(s, ch);
        return ret;
    }

    OMAP_BAD_REG(addr);
    return 0;
}

static void omap_mcspi_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
{
    struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
    int ch = 0;

    if (size != 4) {
        omap_badwidth_write32(opaque, addr, value);
        return;
    }

    switch (addr) {
    case 0x00:	/* MCSPI_REVISION */
    case 0x14:	/* MCSPI_SYSSTATUS */
    case 0x30:	/* MCSPI_CHSTAT0 */
    case 0x3c:	/* MCSPI_RX0 */
    case 0x44:	/* MCSPI_CHSTAT1 */
    case 0x50:	/* MCSPI_RX1 */
    case 0x58:	/* MCSPI_CHSTAT2 */
    case 0x64:	/* MCSPI_RX2 */
    case 0x6c:	/* MCSPI_CHSTAT3 */
    case 0x78:	/* MCSPI_RX3 */
        OMAP_RO_REG(addr);
        return;

    case 0x10:	/* MCSPI_SYSCONFIG */
        if (value & (1 << 1))				/* SOFTRESET */
            omap_mcspi_reset(s);
        s->sysconfig = value & 0x31d;
        break;

    case 0x18:	/* MCSPI_IRQSTATUS */
        if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
            s->irqst &= ~value;
            omap_mcspi_interrupt_update(s);
        }
        break;

    case 0x1c:	/* MCSPI_IRQENABLE */
        s->irqen = value & 0x1777f;
        omap_mcspi_interrupt_update(s);
        break;

    case 0x20:	/* MCSPI_WAKEUPENABLE */
        s->wken = value & 1;
        break;

    case 0x24:	/* MCSPI_SYST */
        if (s->control & (1 << 3))			/* SYSTEM_TEST */
            if (value & (1 << 11)) {			/* SSB */
                s->irqst |= 0x1777f;
                omap_mcspi_interrupt_update(s);
            }
        s->systest = value & 0xfff;
        break;

    case 0x28:	/* MCSPI_MODULCTRL */
        if (value & (1 << 3))				/* SYSTEM_TEST */
            if (s->systest & (1 << 11)) {		/* SSB */
                s->irqst |= 0x1777f;
                omap_mcspi_interrupt_update(s);
            }
        s->control = value & 0xf;
        break;

    case 0x68: ch ++;
        /* fall through */
    case 0x54: ch ++;
        /* fall through */
    case 0x40: ch ++;
        /* fall through */
    case 0x2c:	/* MCSPI_CHCONF */
        if ((value ^ s->ch[ch].config) & (3 << 14))	/* DMAR | DMAW */
            omap_mcspi_dmarequest_update(s->ch + ch);
        if (((value >> 12) & 3) == 3) { /* TRM */
            qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid TRM value (3)\n",
                          __func__);
        }
        if (((value >> 7) & 0x1f) < 3) { /* WL */
            qemu_log_mask(LOG_GUEST_ERROR,
                          "%s: invalid WL value (%" PRIx64 ")\n",
                          __func__, (value >> 7) & 0x1f);
        }
        s->ch[ch].config = value & 0x7fffff;
        break;

    case 0x70: ch ++;
        /* fall through */
    case 0x5c: ch ++;
        /* fall through */
    case 0x48: ch ++;
        /* fall through */
    case 0x34:	/* MCSPI_CHCTRL */
        if (value & ~s->ch[ch].control & 1) {		/* EN */
            s->ch[ch].control |= 1;
            omap_mcspi_transfer_run(s, ch);
        } else
            s->ch[ch].control = value & 1;
        break;

    case 0x74: ch ++;
        /* fall through */
    case 0x60: ch ++;
        /* fall through */
    case 0x4c: ch ++;
        /* fall through */
    case 0x38:	/* MCSPI_TX */
        s->ch[ch].tx = value;
        s->ch[ch].status &= ~(1 << 1);			/* TXS */
        omap_mcspi_transfer_run(s, ch);
        break;

    default:
        OMAP_BAD_REG(addr);
        return;
    }
}

static const MemoryRegionOps omap_mcspi_ops = {
    .read = omap_mcspi_read,
    .write = omap_mcspi_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
                qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
{
    struct omap_mcspi_s *s = g_new0(struct omap_mcspi_s, 1);
    struct omap_mcspi_ch_s *ch = s->ch;

    s->irq = irq;
    s->chnum = chnum;
    while (chnum --) {
        ch->txdrq = *drq ++;
        ch->rxdrq = *drq ++;
        ch ++;
    }
    omap_mcspi_reset(s);

    memory_region_init_io(&s->iomem, NULL, &omap_mcspi_ops, s, "omap.mcspi",
                          omap_l4_region_size(ta, 0));
    omap_l4_attach(ta, 0, &s->iomem);

    return s;
}

void omap_mcspi_attach(struct omap_mcspi_s *s,
                uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
                int chipselect)
{
    if (chipselect < 0 || chipselect >= s->chnum)
        hw_error("%s: Bad chipselect %i\n", __func__, chipselect);

    s->ch[chipselect].txrx = txrx;
    s->ch[chipselect].opaque = opaque;
}
Commit	Line	Data
2d08cc7c	1	/*
	2	* TI OMAP processor's Multichannel SPI emulation.
	3	*
	4	* Copyright (C) 2007-2009 Nokia Corporation
	5	*
	6	* Original code for OMAP2 by Andrzej Zaborowski <[email protected]>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 or
	11	* (at your option) any later version of the License.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License along
	19	* with this program; if not, write to the Free Software Foundation, Inc.,
	20	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
	21	*/
64552b6b	22
17b7f2db	23	#include "qemu/osdep.h"
31a1246d	24	#include "qemu/log.h"
83c9f4ca	25	#include "hw/hw.h"
64552b6b	26	#include "hw/irq.h"
0d09e41a	27	#include "hw/arm/omap.h"
2d08cc7c	28
	29	/* Multichannel SPI */
	30	struct omap_mcspi_s {
1a072690	31	MemoryRegion iomem;
2d08cc7c	32	qemu_irq irq;
	33	int chnum;
	34
	35	uint32_t sysconfig;
	36	uint32_t systest;
	37	uint32_t irqst;
	38	uint32_t irqen;
	39	uint32_t wken;
	40	uint32_t control;
	41
	42	struct omap_mcspi_ch_s {
	43	qemu_irq txdrq;
	44	qemu_irq rxdrq;
	45	uint32_t (txrx)(void opaque, uint32_t, int);
	46	void *opaque;
	47
	48	uint32_t tx;
	49	uint32_t rx;
	50
	51	uint32_t config;
	52	uint32_t status;
	53	uint32_t control;
	54	} ch[4];
	55	};
	56
	57	static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
	58	{
	59	qemu_set_irq(s->irq, s->irqst & s->irqen);
	60	}
	61
	62	static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
	63	{
	64	qemu_set_irq(ch->txdrq,
	65	(ch->control & 1) && /* EN */
	66	(ch->config & (1 << 14)) && /* DMAW */
	67	(ch->status & (1 << 1)) && /* TXS */
	68	((ch->config >> 12) & 3) != 1); /* TRM */
	69	qemu_set_irq(ch->rxdrq,
	70	(ch->control & 1) && /* EN */
	71	(ch->config & (1 << 15)) && /* DMAW */
	72	(ch->status & (1 << 0)) && /* RXS */
	73	((ch->config >> 12) & 3) != 2); /* TRM */
	74	}
	75
	76	static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
	77	{
	78	struct omap_mcspi_ch_s *ch = s->ch + chnum;
	79
	80	if (!(ch->control & 1)) /* EN */
	81	return;
	82	if ((ch->status & (1 << 0)) && /* RXS */
	83	((ch->config >> 12) & 3) != 2 && /* TRM */
	84	!(ch->config & (1 << 19))) /* TURBO */
	85	goto intr_update;
	86	if ((ch->status & (1 << 1)) && /* TXS */
	87	((ch->config >> 12) & 3) != 1) /* TRM */
	88	goto intr_update;
	89
	90	if (!(s->control & 1) \|\| /* SINGLE */
	91	(ch->config & (1 << 20))) { /* FORCE */
	92	if (ch->txrx)
	93	ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
	94	1 + (0x1f & (ch->config >> 7)));
	95	}
96
97	ch->tx = 0;
98	ch->status \|= 1 << 2; /* EOT */
99	ch->status \|= 1 << 1; /* TXS */
100	if (((ch->config >> 12) & 3) != 2) /* TRM */
101	ch->status \|= 1 << 0; /* RXS */
102
103	intr_update:
104	if ((ch->status & (1 << 0)) && /* RXS */
105	((ch->config >> 12) & 3) != 2 && /* TRM */
106	!(ch->config & (1 << 19))) /* TURBO */
107	s->irqst \|= 1 << (2 + 4 * chnum); /* RX_FULL */
108	if ((ch->status & (1 << 1)) && /* TXS */
109	((ch->config >> 12) & 3) != 1) /* TRM */
110	s->irqst \|= 1 << (0 + 4 * chnum); /* TX_EMPTY */
111	omap_mcspi_interrupt_update(s);
112	omap_mcspi_dmarequest_update(ch);
113	}
114
115	void omap_mcspi_reset(struct omap_mcspi_s *s)
116	{
117	int ch;
118
119	s->sysconfig = 0;
120	s->systest = 0;
121	s->irqst = 0;
122	s->irqen = 0;
123	s->wken = 0;
124	s->control = 4;
125
126	for (ch = 0; ch < 4; ch ++) {
127	s->ch[ch].config = 0x060000;
128	s->ch[ch].status = 2; /* TXS */
129	s->ch[ch].control = 0;
130
131	omap_mcspi_dmarequest_update(s->ch + ch);
132	}
133
134	omap_mcspi_interrupt_update(s);
135	}
136
a8170e5e	137	static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
1a072690	138	unsigned size)
2d08cc7c	139	{
	140	struct omap_mcspi_s s = (struct omap_mcspi_s ) opaque;
	141	int ch = 0;
	142	uint32_t ret;
	143
1a072690 BC	144	if (size != 4) {
	145	return omap_badwidth_read32(opaque, addr);
	146	}
	147
2d08cc7c	148	switch (addr) {
	149	case 0x00: /* MCSPI_REVISION */
	150	return 0x91;
	151
	152	case 0x10: /* MCSPI_SYSCONFIG */
	153	return s->sysconfig;
	154
	155	case 0x14: /* MCSPI_SYSSTATUS */
	156	return 1; /* RESETDONE */
	157
	158	case 0x18: /* MCSPI_IRQSTATUS */
	159	return s->irqst;
	160
	161	case 0x1c: /* MCSPI_IRQENABLE */
	162	return s->irqen;
	163
	164	case 0x20: /* MCSPI_WAKEUPENABLE */
	165	return s->wken;
	166
	167	case 0x24: /* MCSPI_SYST */
	168	return s->systest;
	169
	170	case 0x28: /* MCSPI_MODULCTRL */
	171	return s->control;
	172
	173	case 0x68: ch ++;
be688dfb	174	/* fall through */
2d08cc7c	175	case 0x54: ch ++;
be688dfb	176	/* fall through */
2d08cc7c	177	case 0x40: ch ++;
be688dfb	178	/* fall through */
2d08cc7c	179	case 0x2c: /* MCSPI_CHCONF */
	180	return s->ch[ch].config;
	181
	182	case 0x6c: ch ++;
be688dfb	183	/* fall through */
2d08cc7c	184	case 0x58: ch ++;
be688dfb	185	/* fall through */
2d08cc7c	186	case 0x44: ch ++;
be688dfb	187	/* fall through */
2d08cc7c	188	case 0x30: /* MCSPI_CHSTAT */
	189	return s->ch[ch].status;
	190
	191	case 0x70: ch ++;
be688dfb	192	/* fall through */
2d08cc7c	193	case 0x5c: ch ++;
be688dfb	194	/* fall through */
2d08cc7c	195	case 0x48: ch ++;
be688dfb	196	/* fall through */
2d08cc7c	197	case 0x34: /* MCSPI_CHCTRL */
	198	return s->ch[ch].control;
	199
	200	case 0x74: ch ++;
be688dfb	201	/* fall through */
2d08cc7c	202	case 0x60: ch ++;
be688dfb	203	/* fall through */
2d08cc7c	204	case 0x4c: ch ++;
be688dfb	205	/* fall through */
2d08cc7c	206	case 0x38: /* MCSPI_TX */
	207	return s->ch[ch].tx;
	208
	209	case 0x78: ch ++;
be688dfb	210	/* fall through */
2d08cc7c	211	case 0x64: ch ++;
be688dfb	212	/* fall through */
2d08cc7c	213	case 0x50: ch ++;
be688dfb	214	/* fall through */
2d08cc7c	215	case 0x3c: /* MCSPI_RX */
	216	s->ch[ch].status &= ~(1 << 0); /* RXS */
	217	ret = s->ch[ch].rx;
	218	omap_mcspi_transfer_run(s, ch);
	219	return ret;
	220	}
	221
	222	OMAP_BAD_REG(addr);
	223	return 0;
	224	}
	225
a8170e5e	226	static void omap_mcspi_write(void *opaque, hwaddr addr,
1a072690	227	uint64_t value, unsigned size)
2d08cc7c	228	{
	229	struct omap_mcspi_s s = (struct omap_mcspi_s ) opaque;
	230	int ch = 0;
	231
1a072690	232	if (size != 4) {
77a8257e SW	233	omap_badwidth_write32(opaque, addr, value);
77a8257e SW	234	return;
1a072690 BC	235	}
1a072690 BC	236
2d08cc7c	237	switch (addr) {
	238	case 0x00: /* MCSPI_REVISION */
	239	case 0x14: /* MCSPI_SYSSTATUS */
	240	case 0x30: /* MCSPI_CHSTAT0 */
	241	case 0x3c: /* MCSPI_RX0 */
	242	case 0x44: /* MCSPI_CHSTAT1 */
	243	case 0x50: /* MCSPI_RX1 */
	244	case 0x58: /* MCSPI_CHSTAT2 */
	245	case 0x64: /* MCSPI_RX2 */
	246	case 0x6c: /* MCSPI_CHSTAT3 */
	247	case 0x78: /* MCSPI_RX3 */
	248	OMAP_RO_REG(addr);
	249	return;
	250
	251	case 0x10: /* MCSPI_SYSCONFIG */
	252	if (value & (1 << 1)) /* SOFTRESET */
	253	omap_mcspi_reset(s);
	254	s->sysconfig = value & 0x31d;
	255	break;
	256
	257	case 0x18: /* MCSPI_IRQSTATUS */
	258	if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
	259	s->irqst &= ~value;
	260	omap_mcspi_interrupt_update(s);
	261	}
	262	break;
	263
	264	case 0x1c: /* MCSPI_IRQENABLE */
	265	s->irqen = value & 0x1777f;
	266	omap_mcspi_interrupt_update(s);
	267	break;
	268
	269	case 0x20: /* MCSPI_WAKEUPENABLE */
	270	s->wken = value & 1;
	271	break;
	272
	273	case 0x24: /* MCSPI_SYST */
	274	if (s->control & (1 << 3)) /* SYSTEM_TEST */
	275	if (value & (1 << 11)) { /* SSB */
	276	s->irqst \|= 0x1777f;
	277	omap_mcspi_interrupt_update(s);
	278	}
	279	s->systest = value & 0xfff;
	280	break;
	281
	282	case 0x28: /* MCSPI_MODULCTRL */
	283	if (value & (1 << 3)) /* SYSTEM_TEST */
	284	if (s->systest & (1 << 11)) { /* SSB */
	285	s->irqst \|= 0x1777f;
	286	omap_mcspi_interrupt_update(s);
	287	}
	288	s->control = value & 0xf;
	289	break;
	290
	291	case 0x68: ch ++;
be688dfb	292	/* fall through */
2d08cc7c	293	case 0x54: ch ++;
be688dfb	294	/* fall through */
2d08cc7c	295	case 0x40: ch ++;
be688dfb	296	/* fall through */
2d08cc7c	297	case 0x2c: /* MCSPI_CHCONF */
	298	if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR \| DMAW */
	299	omap_mcspi_dmarequest_update(s->ch + ch);
31a1246d PMD	300	if (((value >> 12) & 3) == 3) { /* TRM */
	301	qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid TRM value (3)\n",
	302	__func__);
	303	}
	304	if (((value >> 7) & 0x1f) < 3) { /* WL */
	305	qemu_log_mask(LOG_GUEST_ERROR,
	306	"%s: invalid WL value (%" PRIx64 ")\n",
	307	__func__, (value >> 7) & 0x1f);
	308	}
2d08cc7c	309	s->ch[ch].config = value & 0x7fffff;
	310	break;
	311
	312	case 0x70: ch ++;
be688dfb	313	/* fall through */
2d08cc7c	314	case 0x5c: ch ++;
be688dfb	315	/* fall through */
2d08cc7c	316	case 0x48: ch ++;
be688dfb	317	/* fall through */
2d08cc7c	318	case 0x34: /* MCSPI_CHCTRL */
	319	if (value & ~s->ch[ch].control & 1) { /* EN */
	320	s->ch[ch].control \|= 1;
	321	omap_mcspi_transfer_run(s, ch);
	322	} else
	323	s->ch[ch].control = value & 1;
	324	break;
	325
	326	case 0x74: ch ++;
be688dfb	327	/* fall through */
2d08cc7c	328	case 0x60: ch ++;
be688dfb	329	/* fall through */
2d08cc7c	330	case 0x4c: ch ++;
be688dfb	331	/* fall through */
2d08cc7c	332	case 0x38: /* MCSPI_TX */
	333	s->ch[ch].tx = value;
	334	s->ch[ch].status &= ~(1 << 1); /* TXS */
	335	omap_mcspi_transfer_run(s, ch);
	336	break;
	337
	338	default:
	339	OMAP_BAD_REG(addr);
	340	return;
	341	}
	342	}
	343
1a072690 BC	344	static const MemoryRegionOps omap_mcspi_ops = {
	345	.read = omap_mcspi_read,
	346	.write = omap_mcspi_write,
	347	.endianness = DEVICE_NATIVE_ENDIAN,
2d08cc7c	348	};
	349
	350	struct omap_mcspi_s omap_mcspi_init(struct omap_target_agent_s ta, int chnum,
	351	qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
	352	{
b45c03f5	353	struct omap_mcspi_s *s = g_new0(struct omap_mcspi_s, 1);
2d08cc7c	354	struct omap_mcspi_ch_s *ch = s->ch;
	355
	356	s->irq = irq;
	357	s->chnum = chnum;
	358	while (chnum --) {
	359	ch->txdrq = *drq ++;
	360	ch->rxdrq = *drq ++;
	361	ch ++;
	362	}
	363	omap_mcspi_reset(s);
	364
2c9b15ca	365	memory_region_init_io(&s->iomem, NULL, &omap_mcspi_ops, s, "omap.mcspi",
1a072690	366	omap_l4_region_size(ta, 0));
f44336c5	367	omap_l4_attach(ta, 0, &s->iomem);
2d08cc7c	368
	369	return s;
	370	}
	371
	372	void omap_mcspi_attach(struct omap_mcspi_s *s,
	373	uint32_t (txrx)(void opaque, uint32_t, int), void *opaque,
	374	int chipselect)
	375	{
	376	if (chipselect < 0 \|\| chipselect >= s->chnum)
a89f364a	377	hw_error("%s: Bad chipselect %i\n", __func__, chipselect);
2d08cc7c	378
	379	s->ch[chipselect].txrx = txrx;
	380	s->ch[chipselect].opaque = opaque;
	381	}