[qemu.git] / hw / misc / nrf51_rng.c

/*
 * nRF51 Random Number Generator
 *
 * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
 *
 * Copyright 2018 Steffen Görtz <[email protected]>
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qapi/error.h"
#include "hw/arm/nrf51.h"
#include "hw/irq.h"
#include "hw/misc/nrf51_rng.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qemu/guest-random.h"

static void update_irq(NRF51RNGState *s)
{
    bool irq = s->interrupt_enabled && s->event_valrdy;
    qemu_set_irq(s->irq, irq);
}

static uint64_t rng_read(void *opaque, hwaddr offset, unsigned int size)
{
    NRF51RNGState *s = NRF51_RNG(opaque);
    uint64_t r = 0;

    switch (offset) {
    case NRF51_RNG_EVENT_VALRDY:
        r = s->event_valrdy;
        break;
    case NRF51_RNG_REG_SHORTS:
        r = s->shortcut_stop_on_valrdy;
        break;
    case NRF51_RNG_REG_INTEN:
    case NRF51_RNG_REG_INTENSET:
    case NRF51_RNG_REG_INTENCLR:
        r = s->interrupt_enabled;
        break;
    case NRF51_RNG_REG_CONFIG:
        r = s->filter_enabled;
        break;
    case NRF51_RNG_REG_VALUE:
        r = s->value;
        break;

    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: bad read offset 0x%" HWADDR_PRIx "\n",
                      __func__, offset);
    }

    return r;
}

static int64_t calc_next_timeout(NRF51RNGState *s)
{
    int64_t timeout = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL);
    if (s->filter_enabled) {
        timeout += s->period_filtered_us;
    } else {
        timeout += s->period_unfiltered_us;
    }

    return timeout;
}


static void rng_update_timer(NRF51RNGState *s)
{
    if (s->active) {
        timer_mod(&s->timer, calc_next_timeout(s));
    } else {
        timer_del(&s->timer);
    }
}


static void rng_write(void *opaque, hwaddr offset,
                       uint64_t value, unsigned int size)
{
    NRF51RNGState *s = NRF51_RNG(opaque);

    switch (offset) {
    case NRF51_RNG_TASK_START:
        if (value == NRF51_TRIGGER_TASK) {
            s->active = 1;
            rng_update_timer(s);
        }
        break;
    case NRF51_RNG_TASK_STOP:
        if (value == NRF51_TRIGGER_TASK) {
            s->active = 0;
            rng_update_timer(s);
        }
        break;
    case NRF51_RNG_EVENT_VALRDY:
        if (value == NRF51_EVENT_CLEAR) {
            s->event_valrdy = 0;
        }
        break;
    case NRF51_RNG_REG_SHORTS:
        s->shortcut_stop_on_valrdy =
                (value & BIT_MASK(NRF51_RNG_REG_SHORTS_VALRDY_STOP)) ? 1 : 0;
        break;
    case NRF51_RNG_REG_INTEN:
        s->interrupt_enabled =
                (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) ? 1 : 0;
        break;
    case NRF51_RNG_REG_INTENSET:
        if (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) {
            s->interrupt_enabled = 1;
        }
        break;
    case NRF51_RNG_REG_INTENCLR:
        if (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) {
            s->interrupt_enabled = 0;
        }
        break;
    case NRF51_RNG_REG_CONFIG:
        s->filter_enabled =
                      (value & BIT_MASK(NRF51_RNG_REG_CONFIG_DECEN)) ? 1 : 0;
        break;

    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: bad write offset 0x%" HWADDR_PRIx "\n",
                      __func__, offset);
    }

    update_irq(s);
}

static const MemoryRegionOps rng_ops = {
    .read =  rng_read,
    .write = rng_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .impl.min_access_size = 4,
    .impl.max_access_size = 4
};

static void nrf51_rng_timer_expire(void *opaque)
{
    NRF51RNGState *s = NRF51_RNG(opaque);

    qemu_guest_getrandom_nofail(&s->value, 1);

    s->event_valrdy = 1;
    qemu_set_irq(s->eep_valrdy, 1);

    if (s->shortcut_stop_on_valrdy) {
        s->active = 0;
    }

    rng_update_timer(s);
    update_irq(s);
}

static void nrf51_rng_tep_start(void *opaque, int n, int level)
{
    NRF51RNGState *s = NRF51_RNG(opaque);

    if (level) {
        s->active = 1;
        rng_update_timer(s);
    }
}

static void nrf51_rng_tep_stop(void *opaque, int n, int level)
{
    NRF51RNGState *s = NRF51_RNG(opaque);

    if (level) {
        s->active = 0;
        rng_update_timer(s);
    }
}


static void nrf51_rng_init(Object *obj)
{
    NRF51RNGState *s = NRF51_RNG(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    memory_region_init_io(&s->mmio, obj, &rng_ops, s,
            TYPE_NRF51_RNG, NRF51_RNG_SIZE);
    sysbus_init_mmio(sbd, &s->mmio);

    timer_init_us(&s->timer, QEMU_CLOCK_VIRTUAL, nrf51_rng_timer_expire, s);

    sysbus_init_irq(sbd, &s->irq);

    /* Tasks */
    qdev_init_gpio_in_named(DEVICE(s), nrf51_rng_tep_start, "tep_start", 1);
    qdev_init_gpio_in_named(DEVICE(s), nrf51_rng_tep_stop, "tep_stop", 1);

    /* Events */
    qdev_init_gpio_out_named(DEVICE(s), &s->eep_valrdy, "eep_valrdy", 1);
}

static void nrf51_rng_reset(DeviceState *dev)
{
    NRF51RNGState *s = NRF51_RNG(dev);

    s->value = 0;
    s->active = 0;
    s->event_valrdy = 0;
    s->shortcut_stop_on_valrdy = 0;
    s->interrupt_enabled = 0;
    s->filter_enabled = 0;

    rng_update_timer(s);
}


static Property nrf51_rng_properties[] = {
    DEFINE_PROP_UINT16("period_unfiltered_us", NRF51RNGState,
            period_unfiltered_us, 167),
    DEFINE_PROP_UINT16("period_filtered_us", NRF51RNGState,
            period_filtered_us, 660),
    DEFINE_PROP_END_OF_LIST(),
};

static const VMStateDescription vmstate_rng = {
    .name = "nrf51_soc.rng",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(active, NRF51RNGState),
        VMSTATE_UINT32(event_valrdy, NRF51RNGState),
        VMSTATE_UINT32(shortcut_stop_on_valrdy, NRF51RNGState),
        VMSTATE_UINT32(interrupt_enabled, NRF51RNGState),
        VMSTATE_UINT32(filter_enabled, NRF51RNGState),
        VMSTATE_END_OF_LIST()
    }
};

static void nrf51_rng_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    device_class_set_props(dc, nrf51_rng_properties);
    dc->vmsd = &vmstate_rng;
    dc->reset = nrf51_rng_reset;
}

static const TypeInfo nrf51_rng_info = {
    .name = TYPE_NRF51_RNG,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(NRF51RNGState),
    .instance_init = nrf51_rng_init,
    .class_init = nrf51_rng_class_init
};

static void nrf51_rng_register_types(void)
{
    type_register_static(&nrf51_rng_info);
}

type_init(nrf51_rng_register_types)
Commit	Line	Data
90c58941 SG	1	/*
	2	* nRF51 Random Number Generator
	3	*
	4	* Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
	5	*
	6	* Copyright 2018 Steffen Görtz <[email protected]>
	7	*
	8	* This code is licensed under the GPL version 2 or later. See
	9	* the COPYING file in the top-level directory.
	10	*/
	11
	12	#include "qemu/osdep.h"
	13	#include "qemu/log.h"
0b8fa32f	14	#include "qemu/module.h"
90c58941 SG	15	#include "qapi/error.h"
90c58941 SG	16	#include "hw/arm/nrf51.h"
64552b6b	17	#include "hw/irq.h"
90c58941	18	#include "hw/misc/nrf51_rng.h"
a27bd6c7	19	#include "hw/qdev-properties.h"
d6454270	20	#include "migration/vmstate.h"
19173fd3	21	#include "qemu/guest-random.h"
90c58941 SG	22
	23	static void update_irq(NRF51RNGState *s)
	24	{
	25	bool irq = s->interrupt_enabled && s->event_valrdy;
	26	qemu_set_irq(s->irq, irq);
	27	}
	28
	29	static uint64_t rng_read(void *opaque, hwaddr offset, unsigned int size)
	30	{
	31	NRF51RNGState *s = NRF51_RNG(opaque);
	32	uint64_t r = 0;
	33
	34	switch (offset) {
	35	case NRF51_RNG_EVENT_VALRDY:
	36	r = s->event_valrdy;
	37	break;
	38	case NRF51_RNG_REG_SHORTS:
	39	r = s->shortcut_stop_on_valrdy;
	40	break;
	41	case NRF51_RNG_REG_INTEN:
	42	case NRF51_RNG_REG_INTENSET:
	43	case NRF51_RNG_REG_INTENCLR:
	44	r = s->interrupt_enabled;
	45	break;
	46	case NRF51_RNG_REG_CONFIG:
	47	r = s->filter_enabled;
	48	break;
	49	case NRF51_RNG_REG_VALUE:
	50	r = s->value;
	51	break;
	52
	53	default:
	54	qemu_log_mask(LOG_GUEST_ERROR,
	55	"%s: bad read offset 0x%" HWADDR_PRIx "\n",
	56	__func__, offset);
	57	}
	58
	59	return r;
	60	}
	61
	62	static int64_t calc_next_timeout(NRF51RNGState *s)
	63	{
	64	int64_t timeout = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL);
	65	if (s->filter_enabled) {
	66	timeout += s->period_filtered_us;
	67	} else {
	68	timeout += s->period_unfiltered_us;
	69	}
	70
	71	return timeout;
	72	}
	73
	74
	75	static void rng_update_timer(NRF51RNGState *s)
	76	{
	77	if (s->active) {
	78	timer_mod(&s->timer, calc_next_timeout(s));
	79	} else {
	80	timer_del(&s->timer);
	81	}
	82	}
	83
	84
	85	static void rng_write(void *opaque, hwaddr offset,
86	uint64_t value, unsigned int size)
87	{
88	NRF51RNGState *s = NRF51_RNG(opaque);
89
90	switch (offset) {
91	case NRF51_RNG_TASK_START:
92	if (value == NRF51_TRIGGER_TASK) {
93	s->active = 1;
94	rng_update_timer(s);
95	}
96	break;
97	case NRF51_RNG_TASK_STOP:
98	if (value == NRF51_TRIGGER_TASK) {
99	s->active = 0;
100	rng_update_timer(s);
101	}
102	break;
103	case NRF51_RNG_EVENT_VALRDY:
104	if (value == NRF51_EVENT_CLEAR) {
105	s->event_valrdy = 0;
106	}
107	break;
108	case NRF51_RNG_REG_SHORTS:
109	s->shortcut_stop_on_valrdy =
110	(value & BIT_MASK(NRF51_RNG_REG_SHORTS_VALRDY_STOP)) ? 1 : 0;
111	break;
112	case NRF51_RNG_REG_INTEN:
113	s->interrupt_enabled =
114	(value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) ? 1 : 0;
115	break;
116	case NRF51_RNG_REG_INTENSET:
117	if (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) {
118	s->interrupt_enabled = 1;
119	}
120	break;
121	case NRF51_RNG_REG_INTENCLR:
122	if (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) {
123	s->interrupt_enabled = 0;
124	}
125	break;
126	case NRF51_RNG_REG_CONFIG:
127	s->filter_enabled =
128	(value & BIT_MASK(NRF51_RNG_REG_CONFIG_DECEN)) ? 1 : 0;
129	break;
130
131	default:
132	qemu_log_mask(LOG_GUEST_ERROR,
133	"%s: bad write offset 0x%" HWADDR_PRIx "\n",
134	__func__, offset);
135	}
136
137	update_irq(s);
138	}
139
140	static const MemoryRegionOps rng_ops = {
141	.read = rng_read,
142	.write = rng_write,
143	.endianness = DEVICE_LITTLE_ENDIAN,
144	.impl.min_access_size = 4,
145	.impl.max_access_size = 4
146	};
147
148	static void nrf51_rng_timer_expire(void *opaque)
149	{
150	NRF51RNGState *s = NRF51_RNG(opaque);
151
19173fd3	152	qemu_guest_getrandom_nofail(&s->value, 1);
90c58941 SG	153
	154	s->event_valrdy = 1;
	155	qemu_set_irq(s->eep_valrdy, 1);
	156
	157	if (s->shortcut_stop_on_valrdy) {
	158	s->active = 0;
	159	}
	160
	161	rng_update_timer(s);
	162	update_irq(s);
	163	}
	164
	165	static void nrf51_rng_tep_start(void *opaque, int n, int level)
	166	{
	167	NRF51RNGState *s = NRF51_RNG(opaque);
	168
	169	if (level) {
	170	s->active = 1;
	171	rng_update_timer(s);
	172	}
	173	}
	174
	175	static void nrf51_rng_tep_stop(void *opaque, int n, int level)
	176	{
	177	NRF51RNGState *s = NRF51_RNG(opaque);
	178
	179	if (level) {
	180	s->active = 0;
	181	rng_update_timer(s);
	182	}
	183	}
	184
	185
	186	static void nrf51_rng_init(Object *obj)
	187	{
	188	NRF51RNGState *s = NRF51_RNG(obj);
	189	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	190
	191	memory_region_init_io(&s->mmio, obj, &rng_ops, s,
	192	TYPE_NRF51_RNG, NRF51_RNG_SIZE);
	193	sysbus_init_mmio(sbd, &s->mmio);
	194
	195	timer_init_us(&s->timer, QEMU_CLOCK_VIRTUAL, nrf51_rng_timer_expire, s);
	196
	197	sysbus_init_irq(sbd, &s->irq);
	198
	199	/* Tasks */
	200	qdev_init_gpio_in_named(DEVICE(s), nrf51_rng_tep_start, "tep_start", 1);
	201	qdev_init_gpio_in_named(DEVICE(s), nrf51_rng_tep_stop, "tep_stop", 1);
	202
	203	/* Events */
	204	qdev_init_gpio_out_named(DEVICE(s), &s->eep_valrdy, "eep_valrdy", 1);
	205	}
	206
	207	static void nrf51_rng_reset(DeviceState *dev)
	208	{
	209	NRF51RNGState *s = NRF51_RNG(dev);
	210
	211	s->value = 0;
	212	s->active = 0;
	213	s->event_valrdy = 0;
	214	s->shortcut_stop_on_valrdy = 0;
	215	s->interrupt_enabled = 0;
	216	s->filter_enabled = 0;
217
218	rng_update_timer(s);
219	}
220
221
222	static Property nrf51_rng_properties[] = {
223	DEFINE_PROP_UINT16("period_unfiltered_us", NRF51RNGState,
224	period_unfiltered_us, 167),
225	DEFINE_PROP_UINT16("period_filtered_us", NRF51RNGState,
226	period_filtered_us, 660),
227	DEFINE_PROP_END_OF_LIST(),
228	};
229
230	static const VMStateDescription vmstate_rng = {
231	.name = "nrf51_soc.rng",
232	.version_id = 1,
233	.minimum_version_id = 1,
234	.fields = (VMStateField[]) {
235	VMSTATE_UINT32(active, NRF51RNGState),
236	VMSTATE_UINT32(event_valrdy, NRF51RNGState),
237	VMSTATE_UINT32(shortcut_stop_on_valrdy, NRF51RNGState),
238	VMSTATE_UINT32(interrupt_enabled, NRF51RNGState),
239	VMSTATE_UINT32(filter_enabled, NRF51RNGState),
240	VMSTATE_END_OF_LIST()
241	}
242	};
243
244	static void nrf51_rng_class_init(ObjectClass klass, void data)
245	{
246	DeviceClass *dc = DEVICE_CLASS(klass);
247
4f67d30b	248	device_class_set_props(dc, nrf51_rng_properties);
90c58941 SG	249	dc->vmsd = &vmstate_rng;
	250	dc->reset = nrf51_rng_reset;
	251	}
	252
	253	static const TypeInfo nrf51_rng_info = {
	254	.name = TYPE_NRF51_RNG,
	255	.parent = TYPE_SYS_BUS_DEVICE,
	256	.instance_size = sizeof(NRF51RNGState),
	257	.instance_init = nrf51_rng_init,
	258	.class_init = nrf51_rng_class_init
	259	};
	260
	261	static void nrf51_rng_register_types(void)
	262	{
	263	type_register_static(&nrf51_rng_info);
	264	}
	265
	266	type_init(nrf51_rng_register_types)