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5fafdf24 | 1 | /* |
e69954b9 PB |
2 | * ARM RealView Baseboard System emulation. |
3 | * | |
a1bb27b1 | 4 | * Copyright (c) 2006-2007 CodeSourcery. |
e69954b9 PB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This code is licenced under the GPL. | |
8 | */ | |
9 | ||
87ecb68b PB |
10 | #include "hw.h" |
11 | #include "arm-misc.h" | |
12 | #include "primecell.h" | |
13 | #include "devices.h" | |
14 | #include "pci.h" | |
15 | #include "net.h" | |
16 | #include "sysemu.h" | |
17 | #include "boards.h" | |
e69954b9 PB |
18 | |
19 | /* Board init. */ | |
20 | ||
f93eb9ff AZ |
21 | static struct arm_boot_info realview_binfo = { |
22 | .loader_start = 0x0, | |
23 | .board_id = 0x33b, | |
24 | }; | |
25 | ||
00f82b8a | 26 | static void realview_init(ram_addr_t ram_size, int vga_ram_size, |
6ac0e82d | 27 | const char *boot_device, DisplayState *ds, |
e69954b9 | 28 | const char *kernel_filename, const char *kernel_cmdline, |
94fc95cd | 29 | const char *initrd_filename, const char *cpu_model) |
e69954b9 PB |
30 | { |
31 | CPUState *env; | |
d537cf6c | 32 | qemu_irq *pic; |
e69954b9 PB |
33 | void *scsi_hba; |
34 | PCIBus *pci_bus; | |
35 | NICInfo *nd; | |
36 | int n; | |
37 | int done_smc = 0; | |
9ee6e8bb PB |
38 | qemu_irq cpu_irq[4]; |
39 | int ncpu; | |
e4bcb14c | 40 | int index; |
e69954b9 | 41 | |
3371d272 PB |
42 | if (!cpu_model) |
43 | cpu_model = "arm926"; | |
9ee6e8bb PB |
44 | /* FIXME: obey smp_cpus. */ |
45 | if (strcmp(cpu_model, "arm11mpcore") == 0) { | |
46 | ncpu = 4; | |
47 | } else { | |
48 | ncpu = 1; | |
49 | } | |
50 | ||
51 | for (n = 0; n < ncpu; n++) { | |
52 | env = cpu_init(cpu_model); | |
53 | if (!env) { | |
54 | fprintf(stderr, "Unable to find CPU definition\n"); | |
55 | exit(1); | |
56 | } | |
57 | pic = arm_pic_init_cpu(env); | |
58 | cpu_irq[n] = pic[ARM_PIC_CPU_IRQ]; | |
59 | if (n > 0) { | |
60 | /* Set entry point for secondary CPUs. This assumes we're using | |
61 | the init code from arm_boot.c. Real hardware resets all CPUs | |
62 | the same. */ | |
63 | env->regs[15] = 0x80000000; | |
64 | } | |
aaed909a FB |
65 | } |
66 | ||
1235fc06 | 67 | /* ??? RAM should repeat to fill physical memory space. */ |
e69954b9 PB |
68 | /* SDRAM at address zero. */ |
69 | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); | |
70 | ||
71 | arm_sysctl_init(0x10000000, 0xc1400400); | |
9ee6e8bb PB |
72 | |
73 | if (ncpu == 1) { | |
74 | /* ??? The documentation says GIC1 is nFIQ and either GIC2 or GIC3 | |
75 | is nIRQ (there are inconsistencies). However Linux 2.6.17 expects | |
76 | GIC1 to be nIRQ and ignores all the others, so do that for now. */ | |
77 | pic = realview_gic_init(0x10040000, cpu_irq[0]); | |
78 | } else { | |
79 | pic = mpcore_irq_init(cpu_irq); | |
80 | } | |
81 | ||
d537cf6c PB |
82 | pl050_init(0x10006000, pic[20], 0); |
83 | pl050_init(0x10007000, pic[21], 1); | |
e69954b9 | 84 | |
9ee6e8bb PB |
85 | pl011_init(0x10009000, pic[12], serial_hds[0], PL011_ARM); |
86 | pl011_init(0x1000a000, pic[13], serial_hds[1], PL011_ARM); | |
87 | pl011_init(0x1000b000, pic[14], serial_hds[2], PL011_ARM); | |
88 | pl011_init(0x1000c000, pic[15], serial_hds[3], PL011_ARM); | |
e69954b9 PB |
89 | |
90 | /* DMA controller is optional, apparently. */ | |
d537cf6c | 91 | pl080_init(0x10030000, pic[24], 2); |
e69954b9 | 92 | |
d537cf6c PB |
93 | sp804_init(0x10011000, pic[4]); |
94 | sp804_init(0x10012000, pic[5]); | |
e69954b9 | 95 | |
d537cf6c | 96 | pl110_init(ds, 0x10020000, pic[23], 1); |
e69954b9 | 97 | |
e4bcb14c TS |
98 | index = drive_get_index(IF_SD, 0, 0); |
99 | if (index == -1) { | |
100 | fprintf(stderr, "qemu: missing SecureDigital card\n"); | |
101 | exit(1); | |
102 | } | |
103 | pl181_init(0x10005000, drives_table[index].bdrv, pic[17], pic[18]); | |
a1bb27b1 | 104 | |
7e1543c2 PB |
105 | pl031_init(0x10017000, pic[10]); |
106 | ||
e69954b9 PB |
107 | pci_bus = pci_vpb_init(pic, 48, 1); |
108 | if (usb_enabled) { | |
e24ad6f1 | 109 | usb_ohci_init_pci(pci_bus, 3, -1); |
e69954b9 | 110 | } |
e4bcb14c TS |
111 | if (drive_get_max_bus(IF_SCSI) > 0) { |
112 | fprintf(stderr, "qemu: too many SCSI bus\n"); | |
113 | exit(1); | |
114 | } | |
e69954b9 | 115 | scsi_hba = lsi_scsi_init(pci_bus, -1); |
e4bcb14c TS |
116 | for (n = 0; n < LSI_MAX_DEVS; n++) { |
117 | index = drive_get_index(IF_SCSI, 0, n); | |
118 | if (index == -1) | |
119 | continue; | |
120 | lsi_scsi_attach(scsi_hba, drives_table[index].bdrv, n); | |
e69954b9 PB |
121 | } |
122 | for(n = 0; n < nb_nics; n++) { | |
123 | nd = &nd_table[n]; | |
0ae18cee AL |
124 | |
125 | if ((!nd->model && !done_smc) || strcmp(nd->model, "smc91c111") == 0) { | |
d537cf6c | 126 | smc91c111_init(nd, 0x4e000000, pic[28]); |
0ae18cee | 127 | done_smc = 1; |
e69954b9 | 128 | } else { |
cb457d76 | 129 | pci_nic_init(pci_bus, nd, -1, "rtl8139"); |
e69954b9 PB |
130 | } |
131 | } | |
132 | ||
133 | /* Memory map for RealView Emulation Baseboard: */ | |
134 | /* 0x10000000 System registers. */ | |
135 | /* 0x10001000 System controller. */ | |
136 | /* 0x10002000 Two-Wire Serial Bus. */ | |
137 | /* 0x10003000 Reserved. */ | |
138 | /* 0x10004000 AACI. */ | |
139 | /* 0x10005000 MCI. */ | |
140 | /* 0x10006000 KMI0. */ | |
141 | /* 0x10007000 KMI1. */ | |
142 | /* 0x10008000 Character LCD. */ | |
143 | /* 0x10009000 UART0. */ | |
144 | /* 0x1000a000 UART1. */ | |
145 | /* 0x1000b000 UART2. */ | |
146 | /* 0x1000c000 UART3. */ | |
147 | /* 0x1000d000 SSPI. */ | |
148 | /* 0x1000e000 SCI. */ | |
149 | /* 0x1000f000 Reserved. */ | |
150 | /* 0x10010000 Watchdog. */ | |
151 | /* 0x10011000 Timer 0+1. */ | |
152 | /* 0x10012000 Timer 2+3. */ | |
153 | /* 0x10013000 GPIO 0. */ | |
154 | /* 0x10014000 GPIO 1. */ | |
155 | /* 0x10015000 GPIO 2. */ | |
156 | /* 0x10016000 Reserved. */ | |
7e1543c2 | 157 | /* 0x10017000 RTC. */ |
e69954b9 PB |
158 | /* 0x10018000 DMC. */ |
159 | /* 0x10019000 PCI controller config. */ | |
160 | /* 0x10020000 CLCD. */ | |
161 | /* 0x10030000 DMA Controller. */ | |
9ee6e8bb PB |
162 | /* 0x10040000 GIC1. */ |
163 | /* 0x10050000 GIC2. */ | |
164 | /* 0x10060000 GIC3. */ | |
165 | /* 0x10070000 GIC4. */ | |
e69954b9 PB |
166 | /* 0x10080000 SMC. */ |
167 | /* 0x40000000 NOR flash. */ | |
168 | /* 0x44000000 DoC flash. */ | |
169 | /* 0x48000000 SRAM. */ | |
170 | /* 0x4c000000 Configuration flash. */ | |
171 | /* 0x4e000000 Ethernet. */ | |
172 | /* 0x4f000000 USB. */ | |
173 | /* 0x50000000 PISMO. */ | |
174 | /* 0x54000000 PISMO. */ | |
175 | /* 0x58000000 PISMO. */ | |
176 | /* 0x5c000000 PISMO. */ | |
177 | /* 0x60000000 PCI. */ | |
178 | /* 0x61000000 PCI Self Config. */ | |
179 | /* 0x62000000 PCI Config. */ | |
180 | /* 0x63000000 PCI IO. */ | |
181 | /* 0x64000000 PCI mem 0. */ | |
182 | /* 0x68000000 PCI mem 1. */ | |
183 | /* 0x6c000000 PCI mem 2. */ | |
184 | ||
f93eb9ff AZ |
185 | realview_binfo.ram_size = ram_size; |
186 | realview_binfo.kernel_filename = kernel_filename; | |
187 | realview_binfo.kernel_cmdline = kernel_cmdline; | |
188 | realview_binfo.initrd_filename = initrd_filename; | |
189 | realview_binfo.nb_cpus = ncpu; | |
190 | arm_load_kernel(first_cpu, &realview_binfo); | |
9ee6e8bb PB |
191 | |
192 | /* ??? Hack to map an additional page of ram for the secondary CPU | |
193 | startup code. I guess this works on real hardware because the | |
194 | BootROM happens to be in ROM/flash or in memory that isn't clobbered | |
195 | until after Linux boots the secondary CPUs. */ | |
196 | cpu_register_physical_memory(0x80000000, 0x1000, IO_MEM_RAM + ram_size); | |
e69954b9 PB |
197 | } |
198 | ||
199 | QEMUMachine realview_machine = { | |
c9b1ae2c BS |
200 | .name = "realview", |
201 | .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)", | |
202 | .init = realview_init, | |
203 | .ram_require = 0x1000, | |
204 | .use_scsi = 1, | |
e69954b9 | 205 | }; |