[qemu.git] / hw / pl011.c

/*
 * Arm PrimeCell PL011 UART
 *
 * Copyright (c) 2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */

#include "vl.h"

typedef struct {
    uint32_t base;
    uint32_t readbuff;
    uint32_t flags;
    uint32_t lcr;
    uint32_t cr;
    uint32_t dmacr;
    uint32_t int_enabled;
    uint32_t int_level;
    uint32_t read_fifo[16];
    uint32_t ilpr;
    uint32_t ibrd;
    uint32_t fbrd;
    uint32_t ifl;
    int read_pos;
    int read_count;
    int read_trigger;
    CharDriverState *chr;
    qemu_irq irq;
    enum pl011_type type;
} pl011_state;

#define PL011_INT_TX 0x20
#define PL011_INT_RX 0x10

#define PL011_FLAG_TXFE 0x80
#define PL011_FLAG_RXFF 0x40
#define PL011_FLAG_TXFF 0x20
#define PL011_FLAG_RXFE 0x10

static const unsigned char pl011_id[2][8] = {
  { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }, /* PL011_ARM */
  { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }, /* PL011_LUMINARY */
};

static void pl011_update(pl011_state *s)
{
    uint32_t flags;

    flags = s->int_level & s->int_enabled;
    qemu_set_irq(s->irq, flags != 0);
}

static uint32_t pl011_read(void *opaque, target_phys_addr_t offset)
{
    pl011_state *s = (pl011_state *)opaque;
    uint32_t c;

    offset -= s->base;
    if (offset >= 0xfe0 && offset < 0x1000) {
        return pl011_id[s->type][(offset - 0xfe0) >> 2];
    }
    switch (offset >> 2) {
    case 0: /* UARTDR */
        s->flags &= ~PL011_FLAG_RXFF;
        c = s->read_fifo[s->read_pos];
        if (s->read_count > 0) {
            s->read_count--;
            if (++s->read_pos == 16)
                s->read_pos = 0;
        }
        if (s->read_count == 0) {
            s->flags |= PL011_FLAG_RXFE;
        }
        if (s->read_count == s->read_trigger - 1)
            s->int_level &= ~ PL011_INT_RX;
        pl011_update(s);
        return c;
    case 1: /* UARTCR */
        return 0;
    case 6: /* UARTFR */
        return s->flags;
    case 8: /* UARTILPR */
        return s->ilpr;
    case 9: /* UARTIBRD */
        return s->ibrd;
    case 10: /* UARTFBRD */
        return s->fbrd;
    case 11: /* UARTLCR_H */
        return s->lcr;
    case 12: /* UARTCR */
        return s->cr;
    case 13: /* UARTIFLS */
        return s->ifl;
    case 14: /* UARTIMSC */
        return s->int_enabled;
    case 15: /* UARTRIS */
        return s->int_level;
    case 16: /* UARTMIS */
        return s->int_level & s->int_enabled;
    case 18: /* UARTDMACR */
        return s->dmacr;
    default:
        cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl011_set_read_trigger(pl011_state *s)
{
#if 0
    /* The docs say the RX interrupt is triggered when the FIFO exceeds
       the threshold.  However linux only reads the FIFO in response to an
       interrupt.  Triggering the interrupt when the FIFO is non-empty seems
       to make things work.  */
    if (s->lcr & 0x10)
        s->read_trigger = (s->ifl >> 1) & 0x1c;
    else
#endif
        s->read_trigger = 1;
}

static void pl011_write(void *opaque, target_phys_addr_t offset,
                          uint32_t value)
{
    pl011_state *s = (pl011_state *)opaque;
    unsigned char ch;

    offset -= s->base;
    switch (offset >> 2) {
    case 0: /* UARTDR */
        /* ??? Check if transmitter is enabled.  */
        ch = value;
        if (s->chr)
            qemu_chr_write(s->chr, &ch, 1);
        s->int_level |= PL011_INT_TX;
        pl011_update(s);
        break;
    case 1: /* UARTCR */
        s->cr = value;
        break;
    case 6: /* UARTFR */
        /* Writes to Flag register are ignored.  */
        break;
    case 8: /* UARTUARTILPR */
        s->ilpr = value;
        break;
    case 9: /* UARTIBRD */
        s->ibrd = value;
        break;
    case 10: /* UARTFBRD */
        s->fbrd = value;
        break;
    case 11: /* UARTLCR_H */
        s->lcr = value;
        pl011_set_read_trigger(s);
        break;
    case 12: /* UARTCR */
        /* ??? Need to implement the enable and loopback bits.  */
        s->cr = value;
        break;
    case 13: /* UARTIFS */
        s->ifl = value;
        pl011_set_read_trigger(s);
        break;
    case 14: /* UARTIMSC */
        s->int_enabled = value;
        pl011_update(s);
        break;
    case 17: /* UARTICR */
        s->int_level &= ~value;
        pl011_update(s);
        break;
    case 18: /* UARTDMACR */
        s->dmacr = value;
        if (value & 3)
            cpu_abort(cpu_single_env, "PL011: DMA not implemented\n");
        break;
    default:
        cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", (int)offset);
    }
}

static int pl011_can_receive(void *opaque)
{
    pl011_state *s = (pl011_state *)opaque;

    if (s->lcr & 0x10)
        return s->read_count < 16;
    else
        return s->read_count < 1;
}

static void pl011_receive(void *opaque, const uint8_t *buf, int size)
{
    pl011_state *s = (pl011_state *)opaque;
    int slot;

    slot = s->read_pos + s->read_count;
    if (slot >= 16)
        slot -= 16;
    s->read_fifo[slot] = *buf;
    s->read_count++;
    s->flags &= ~PL011_FLAG_RXFE;
    if (s->cr & 0x10 || s->read_count == 16) {
        s->flags |= PL011_FLAG_RXFF;
    }
    if (s->read_count == s->read_trigger) {
        s->int_level |= PL011_INT_RX;
        pl011_update(s);
    }
}

static void pl011_event(void *opaque, int event)
{
    /* ??? Should probably implement break.  */
}

static CPUReadMemoryFunc *pl011_readfn[] = {
   pl011_read,
   pl011_read,
   pl011_read
};

static CPUWriteMemoryFunc *pl011_writefn[] = {
   pl011_write,
   pl011_write,
   pl011_write
};

void pl011_init(uint32_t base, qemu_irq irq,
                CharDriverState *chr, enum pl011_type type)
{
    int iomemtype;
    pl011_state *s;

    s = (pl011_state *)qemu_mallocz(sizeof(pl011_state));
    iomemtype = cpu_register_io_memory(0, pl011_readfn,
                                       pl011_writefn, s);
    cpu_register_physical_memory(base, 0x00001000, iomemtype);
    s->base = base;
    s->irq = irq;
    s->type = type;
    s->chr = chr;
    s->read_trigger = 1;
    s->ifl = 0x12;
    s->cr = 0x300;
    s->flags = 0x90;
    if (chr){
        qemu_chr_add_handlers(chr, pl011_can_receive, pl011_receive,
                              pl011_event, s);
    }
    /* ??? Save/restore.  */
}
Commit	Line	Data
5fafdf24	1	/*
cdbdb648 PB	2	* Arm PrimeCell PL011 UART
	3	*
	4	* Copyright (c) 2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
	10	#include "vl.h"
	11
	12	typedef struct {
	13	uint32_t base;
	14	uint32_t readbuff;
	15	uint32_t flags;
	16	uint32_t lcr;
	17	uint32_t cr;
	18	uint32_t dmacr;
	19	uint32_t int_enabled;
	20	uint32_t int_level;
	21	uint32_t read_fifo[16];
	22	uint32_t ilpr;
	23	uint32_t ibrd;
	24	uint32_t fbrd;
	25	uint32_t ifl;
	26	int read_pos;
	27	int read_count;
	28	int read_trigger;
	29	CharDriverState *chr;
d537cf6c	30	qemu_irq irq;
9ee6e8bb	31	enum pl011_type type;
cdbdb648 PB	32	} pl011_state;
	33
	34	#define PL011_INT_TX 0x20
	35	#define PL011_INT_RX 0x10
	36
	37	#define PL011_FLAG_TXFE 0x80
	38	#define PL011_FLAG_RXFF 0x40
	39	#define PL011_FLAG_TXFF 0x20
	40	#define PL011_FLAG_RXFE 0x10
	41
9ee6e8bb PB	42	static const unsigned char pl011_id[2][8] = {
	43	{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }, /* PL011_ARM */
	44	{ 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }, /* PL011_LUMINARY */
	45	};
cdbdb648 PB	46
	47	static void pl011_update(pl011_state *s)
	48	{
	49	uint32_t flags;
3b46e624	50
cdbdb648	51	flags = s->int_level & s->int_enabled;
d537cf6c	52	qemu_set_irq(s->irq, flags != 0);
cdbdb648 PB	53	}
	54
	55	static uint32_t pl011_read(void *opaque, target_phys_addr_t offset)
	56	{
	57	pl011_state s = (pl011_state )opaque;
	58	uint32_t c;
	59
	60	offset -= s->base;
	61	if (offset >= 0xfe0 && offset < 0x1000) {
9ee6e8bb	62	return pl011_id[s->type][(offset - 0xfe0) >> 2];
cdbdb648 PB	63	}
	64	switch (offset >> 2) {
	65	case 0: /* UARTDR */
	66	s->flags &= ~PL011_FLAG_RXFF;
	67	c = s->read_fifo[s->read_pos];
	68	if (s->read_count > 0) {
	69	s->read_count--;
	70	if (++s->read_pos == 16)
	71	s->read_pos = 0;
	72	}
	73	if (s->read_count == 0) {
	74	s->flags \|= PL011_FLAG_RXFE;
	75	}
	76	if (s->read_count == s->read_trigger - 1)
	77	s->int_level &= ~ PL011_INT_RX;
	78	pl011_update(s);
	79	return c;
	80	case 1: /* UARTCR */
	81	return 0;
	82	case 6: /* UARTFR */
	83	return s->flags;
	84	case 8: /* UARTILPR */
	85	return s->ilpr;
	86	case 9: /* UARTIBRD */
	87	return s->ibrd;
	88	case 10: /* UARTFBRD */
	89	return s->fbrd;
	90	case 11: /* UARTLCR_H */
	91	return s->lcr;
	92	case 12: /* UARTCR */
	93	return s->cr;
	94	case 13: /* UARTIFLS */
	95	return s->ifl;
	96	case 14: /* UARTIMSC */
	97	return s->int_enabled;
	98	case 15: /* UARTRIS */
	99	return s->int_level;
	100	case 16: /* UARTMIS */
	101	return s->int_level & s->int_enabled;
	102	case 18: /* UARTDMACR */
	103	return s->dmacr;
	104	default:
4d1165fa	105	cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", (int)offset);
cdbdb648 PB	106	return 0;
	107	}
	108	}
	109
	110	static void pl011_set_read_trigger(pl011_state *s)
	111	{
	112	#if 0
	113	/* The docs say the RX interrupt is triggered when the FIFO exceeds
	114	the threshold. However linux only reads the FIFO in response to an
	115	interrupt. Triggering the interrupt when the FIFO is non-empty seems
	116	to make things work. */
	117	if (s->lcr & 0x10)
	118	s->read_trigger = (s->ifl >> 1) & 0x1c;
	119	else
	120	#endif
	121	s->read_trigger = 1;
	122	}
	123
	124	static void pl011_write(void *opaque, target_phys_addr_t offset,
	125	uint32_t value)
	126	{
	127	pl011_state s = (pl011_state )opaque;
	128	unsigned char ch;
	129
	130	offset -= s->base;
	131	switch (offset >> 2) {
	132	case 0: /* UARTDR */
	133	/* ??? Check if transmitter is enabled. */
	134	ch = value;
	135	if (s->chr)
	136	qemu_chr_write(s->chr, &ch, 1);
	137	s->int_level \|= PL011_INT_TX;
	138	pl011_update(s);
	139	break;
	140	case 1: /* UARTCR */
	141	s->cr = value;
	142	break;
9ee6e8bb PB	143	case 6: /* UARTFR */
	144	/* Writes to Flag register are ignored. */
	145	break;
cdbdb648 PB	146	case 8: /* UARTUARTILPR */
	147	s->ilpr = value;
	148	break;
	149	case 9: /* UARTIBRD */
	150	s->ibrd = value;
	151	break;
	152	case 10: /* UARTFBRD */
	153	s->fbrd = value;
	154	break;
	155	case 11: /* UARTLCR_H */
	156	s->lcr = value;
	157	pl011_set_read_trigger(s);
	158	break;
	159	case 12: /* UARTCR */
	160	/* ??? Need to implement the enable and loopback bits. */
	161	s->cr = value;
	162	break;
	163	case 13: /* UARTIFS */
	164	s->ifl = value;
	165	pl011_set_read_trigger(s);
	166	break;
	167	case 14: /* UARTIMSC */
	168	s->int_enabled = value;
	169	pl011_update(s);
	170	break;
	171	case 17: /* UARTICR */
	172	s->int_level &= ~value;
	173	pl011_update(s);
	174	break;
	175	case 18: /* UARTDMACR */
	176	s->dmacr = value;
	177	if (value & 3)
	178	cpu_abort(cpu_single_env, "PL011: DMA not implemented\n");
	179	break;
	180	default:
4d1165fa	181	cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", (int)offset);
cdbdb648 PB	182	}
	183	}
	184
aa1f17c1	185	static int pl011_can_receive(void *opaque)
cdbdb648 PB	186	{
	187	pl011_state s = (pl011_state )opaque;
	188
	189	if (s->lcr & 0x10)
	190	return s->read_count < 16;
	191	else
	192	return s->read_count < 1;
	193	}
	194
aa1f17c1	195	static void pl011_receive(void opaque, const uint8_t buf, int size)
cdbdb648 PB	196	{
	197	pl011_state s = (pl011_state )opaque;
	198	int slot;
	199
	200	slot = s->read_pos + s->read_count;
	201	if (slot >= 16)
	202	slot -= 16;
	203	s->read_fifo[slot] = *buf;
	204	s->read_count++;
	205	s->flags &= ~PL011_FLAG_RXFE;
	206	if (s->cr & 0x10 \|\| s->read_count == 16) {
	207	s->flags \|= PL011_FLAG_RXFF;
	208	}
	209	if (s->read_count == s->read_trigger) {
	210	s->int_level \|= PL011_INT_RX;
	211	pl011_update(s);
	212	}
	213	}
	214
	215	static void pl011_event(void *opaque, int event)
	216	{
	217	/* ??? Should probably implement break. */
	218	}
	219
	220	static CPUReadMemoryFunc *pl011_readfn[] = {
	221	pl011_read,
	222	pl011_read,
	223	pl011_read
	224	};
	225
	226	static CPUWriteMemoryFunc *pl011_writefn[] = {
	227	pl011_write,
	228	pl011_write,
	229	pl011_write
	230	};
	231
d537cf6c	232	void pl011_init(uint32_t base, qemu_irq irq,
9ee6e8bb	233	CharDriverState *chr, enum pl011_type type)
cdbdb648 PB	234	{
	235	int iomemtype;
	236	pl011_state *s;
	237
	238	s = (pl011_state *)qemu_mallocz(sizeof(pl011_state));
	239	iomemtype = cpu_register_io_memory(0, pl011_readfn,
	240	pl011_writefn, s);
187337f8	241	cpu_register_physical_memory(base, 0x00001000, iomemtype);
cdbdb648	242	s->base = base;
cdbdb648	243	s->irq = irq;
9ee6e8bb	244	s->type = type;
cdbdb648 PB	245	s->chr = chr;
	246	s->read_trigger = 1;
	247	s->ifl = 0x12;
	248	s->cr = 0x300;
	249	s->flags = 0x90;
5fafdf24	250	if (chr){
aa1f17c1	251	qemu_chr_add_handlers(chr, pl011_can_receive, pl011_receive,
e5b0bc44	252	pl011_event, s);
cdbdb648 PB	253	}
	254	/* ??? Save/restore. */
	255	}
	256