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7c23b892
AZ		 1/*
2 * QEMU e1000 emulation
3 *
2758aa52
MT		 4 * Software developer's manual:
5 * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
6 *
7c23b892
AZ		 7 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
8 * Copyright (c) 2008 Qumranet
9 * Based on work done by:
10 * Copyright (c) 2007 Dan Aloni
11 * Copyright (c) 2004 Antony T Curtis
12 *
13 * This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU Lesser General Public
15 * License as published by the Free Software Foundation; either
16 * version 2 of the License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * Lesser General Public License for more details.
22 *
23 * You should have received a copy of the GNU Lesser General Public
8167ee88 24 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7c23b892
AZ		 25 */
26
27
28#include "hw.h"
29#include "pci.h"
30#include "net.h"
7200ac3c 31#include "net/checksum.h"
fbdaa002 32#include "loader.h"
7c23b892 33
7c23b892
AZ		 34#include "e1000_hw.h"
35
27124888 36#define E1000_DEBUG
7c23b892 37
27124888 38#ifdef E1000_DEBUG
7c23b892
AZ		 39enum {
40 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
41 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
42 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
43 DEBUG_RXFILTER, DEBUG_NOTYET,
44};
45#define DBGBIT(x) (1<<DEBUG_##x)
46static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
47
6c7f4b47 48#define DBGOUT(what, fmt, ...) do { \
7c23b892 49 if (debugflags & DBGBIT(what)) \
6c7f4b47 50 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
7c23b892
AZ		 51 } while (0)
52#else
6c7f4b47 53#define DBGOUT(what, fmt, ...) do {} while (0)
7c23b892
AZ		 54#endif
55
56#define IOPORT_SIZE 0x40
e94bbefe 57#define PNPMMIO_SIZE 0x20000
7c23b892
AZ		 58
59/*
60 * HW models:
61 * E1000_DEV_ID_82540EM works with Windows and Linux
62 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
63 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
64 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
65 * Others never tested
66 */
67enum { E1000_DEVID = E1000_DEV_ID_82540EM };
68
69/*
70 * May need to specify additional MAC-to-PHY entries --
71 * Intel's Windows driver refuses to initialize unless they match
72 */
73enum {
74 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
75 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
76 /* default to E1000_DEV_ID_82540EM */ 0xc20
77};
78
79typedef struct E1000State_st {
80 PCIDevice dev;
a03e2aec 81 NICState *nic;
fbdaa002 82 NICConf conf;
7c23b892
AZ		 83 int mmio_index;
84
85 uint32_t mac_reg[0x8000];
86 uint16_t phy_reg[0x20];
87 uint16_t eeprom_data[64];
88
89 uint32_t rxbuf_size;
90 uint32_t rxbuf_min_shift;
91 int check_rxov;
92 struct e1000_tx {
93 unsigned char header[256];
8f2e8d1f 94 unsigned char vlan_header[4];
b10fec9b 95 /* Fields vlan and data must not be reordered or separated. */
8f2e8d1f 96 unsigned char vlan[4];
7c23b892
AZ		 97 unsigned char data[0x10000];
98 uint16_t size;
99 unsigned char sum_needed;
8f2e8d1f 100 unsigned char vlan_needed;
7c23b892
AZ		 101 uint8_t ipcss;
102 uint8_t ipcso;
103 uint16_t ipcse;
104 uint8_t tucss;
105 uint8_t tucso;
106 uint16_t tucse;
107 uint8_t hdr_len;
108 uint16_t mss;
109 uint32_t paylen;
110 uint16_t tso_frames;
111 char tse;
b6c4f71f
BS		 112 int8_t ip;
113 int8_t tcp;
1b0009db 114 char cptse; // current packet tse bit
7c23b892
AZ		 115 } tx;
116
117 struct {
118 uint32_t val_in; // shifted in from guest driver
119 uint16_t bitnum_in;
120 uint16_t bitnum_out;
121 uint16_t reading;
122 uint32_t old_eecd;
123 } eecd_state;
124} E1000State;
125
126#define defreg(x) x = (E1000_##x>>2)
127enum {
128 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
129 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
130 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
131 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
132 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
133 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
134 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
135 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
136 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
8f2e8d1f
AL		 137 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
138 defreg(VET),
7c23b892
AZ		 139};
140
141enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
88b4e9db 142static const char phy_regcap[0x20] = {
7c23b892
AZ		 143 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
144 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
145 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
146 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
147 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
700f6e2c 148 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
7c23b892
AZ		 149};
150
151static void
6e355d90
IY		 152ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr,
153 pcibus_t size, int type)
7c23b892 154{
89e8b13c
IY		 155 DBGOUT(IO, "e1000_ioport_map addr=0x%04"FMT_PCIBUS
156 " size=0x%08"FMT_PCIBUS"\n", addr, size);
7c23b892
AZ		 157}
158
159static void
160set_interrupt_cause(E1000State *s, int index, uint32_t val)
161{
162 if (val)
163 val |= E1000_ICR_INT_ASSERTED;
164 s->mac_reg[ICR] = val;
b1332393 165 s->mac_reg[ICS] = val;
bc26e55a 166 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
7c23b892
AZ		 167}
168
169static void
170set_ics(E1000State *s, int index, uint32_t val)
171{
172 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
173 s->mac_reg[IMS]);
174 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
175}
176
177static int
178rxbufsize(uint32_t v)
179{
180 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
181 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
182 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
183 switch (v) {
184 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
185 return 16384;
186 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
187 return 8192;
188 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
189 return 4096;
190 case E1000_RCTL_SZ_1024:
191 return 1024;
192 case E1000_RCTL_SZ_512:
193 return 512;
194 case E1000_RCTL_SZ_256:
195 return 256;
196 }
197 return 2048;
198}
199
cab3c825
KW		 200static void
201set_ctrl(E1000State *s, int index, uint32_t val)
202{
203 /* RST is self clearing */
204 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
205}
206
7c23b892
AZ		 207static void
208set_rx_control(E1000State *s, int index, uint32_t val)
209{
210 s->mac_reg[RCTL] = val;
211 s->rxbuf_size = rxbufsize(val);
212 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
213 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
214 s->mac_reg[RCTL]);
215}
216
217static void
218set_mdic(E1000State *s, int index, uint32_t val)
219{
220 uint32_t data = val & E1000_MDIC_DATA_MASK;
221 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
222
223 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
224 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
225 else if (val & E1000_MDIC_OP_READ) {
226 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
227 if (!(phy_regcap[addr] & PHY_R)) {
228 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
229 val |= E1000_MDIC_ERROR;
230 } else
231 val = (val ^ data) | s->phy_reg[addr];
232 } else if (val & E1000_MDIC_OP_WRITE) {
233 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
234 if (!(phy_regcap[addr] & PHY_W)) {
235 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
236 val |= E1000_MDIC_ERROR;
237 } else
238 s->phy_reg[addr] = data;
239 }
240 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
241 set_ics(s, 0, E1000_ICR_MDAC);
242}
243
244static uint32_t
245get_eecd(E1000State *s, int index)
246{
247 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
248
249 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
250 s->eecd_state.bitnum_out, s->eecd_state.reading);
251 if (!s->eecd_state.reading ||
252 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
253 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
254 ret |= E1000_EECD_DO;
255 return ret;
256}
257
258static void
259set_eecd(E1000State *s, int index, uint32_t val)
260{
261 uint32_t oldval = s->eecd_state.old_eecd;
262
263 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
264 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
9651ac55
IT		 265 if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
266 return;
267 if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
268 s->eecd_state.val_in = 0;
269 s->eecd_state.bitnum_in = 0;
270 s->eecd_state.bitnum_out = 0;
271 s->eecd_state.reading = 0;
272 }
7c23b892
AZ		 273 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
274 return;
275 if (!(E1000_EECD_SK & val)) { // falling edge
276 s->eecd_state.bitnum_out++;
277 return;
278 }
7c23b892
AZ		 279 s->eecd_state.val_in <<= 1;
280 if (val & E1000_EECD_DI)
281 s->eecd_state.val_in |= 1;
282 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
283 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
284 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
285 EEPROM_READ_OPCODE_MICROWIRE);
286 }
287 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
288 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
289 s->eecd_state.reading);
290}
291
292static uint32_t
293flash_eerd_read(E1000State *s, int x)
294{
295 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
296
b1332393
BP		 297 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
298 return (s->mac_reg[EERD]);
299
7c23b892 300 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
b1332393
BP		 301 return (E1000_EEPROM_RW_REG_DONE | r);
302
303 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
304 E1000_EEPROM_RW_REG_DONE | r);
7c23b892
AZ		 305}
306
7c23b892
AZ		 307static void
308putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
309{
c6a6a5e3
AL		 310 uint32_t sum;
311
7c23b892
AZ		 312 if (cse && cse < n)
313 n = cse + 1;
c6a6a5e3
AL		 314 if (sloc < n-1) {
315 sum = net_checksum_add(n-css, data+css);
7c23b892 316 cpu_to_be16wu((uint16_t *)(data + sloc),
c6a6a5e3
AL		 317 net_checksum_finish(sum));
318 }
7c23b892
AZ		 319}
320
8f2e8d1f
AL		 321static inline int
322vlan_enabled(E1000State *s)
323{
324 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
325}
326
327static inline int
328vlan_rx_filter_enabled(E1000State *s)
329{
330 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
331}
332
333static inline int
334is_vlan_packet(E1000State *s, const uint8_t *buf)
335{
336 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
337 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
338}
339
340static inline int
341is_vlan_txd(uint32_t txd_lower)
342{
343 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
344}
345
55e8d1ce
MT		 346/* FCS aka Ethernet CRC-32. We don't get it from backends and can't
347 * fill it in, just pad descriptor length by 4 bytes unless guest
348 * told us to trip it off the packet. */
349static inline int
350fcs_len(E1000State *s)
351{
352 return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4;
353}
354
7c23b892
AZ		 355static void
356xmit_seg(E1000State *s)
357{
358 uint16_t len, *sp;
359 unsigned int frames = s->tx.tso_frames, css, sofar, n;
360 struct e1000_tx *tp = &s->tx;
361
1b0009db 362 if (tp->tse && tp->cptse) {
7c23b892
AZ		 363 css = tp->ipcss;
364 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
365 frames, tp->size, css);
366 if (tp->ip) { // IPv4
367 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
368 tp->size - css);
369 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
370 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
371 } else // IPv6
372 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
373 tp->size - css);
374 css = tp->tucss;
375 len = tp->size - css;
376 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
377 if (tp->tcp) {
378 sofar = frames * tp->mss;
379 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
88738c09 380 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
7c23b892
AZ		 381 if (tp->paylen - sofar > tp->mss)
382 tp->data[css + 13] &= ~9; // PSH, FIN
383 } else // UDP
384 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
385 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
386 // add pseudo-header length before checksum calculation
387 sp = (uint16_t *)(tp->data + tp->tucso);
388 cpu_to_be16wu(sp, be16_to_cpup(sp) + len);
389 }
390 tp->tso_frames++;
391 }
392
393 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
394 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
395 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
396 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
8f2e8d1f 397 if (tp->vlan_needed) {
b10fec9b
SW		 398 memmove(tp->vlan, tp->data, 4);
399 memmove(tp->data, tp->data + 4, 8);
8f2e8d1f 400 memcpy(tp->data + 8, tp->vlan_header, 4);
a03e2aec 401 qemu_send_packet(&s->nic->nc, tp->vlan, tp->size + 4);
8f2e8d1f 402 } else
a03e2aec 403 qemu_send_packet(&s->nic->nc, tp->data, tp->size);
7c23b892
AZ		 404 s->mac_reg[TPT]++;
405 s->mac_reg[GPTC]++;
406 n = s->mac_reg[TOTL];
407 if ((s->mac_reg[TOTL] += s->tx.size) < n)
408 s->mac_reg[TOTH]++;
409}
410
411static void
412process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
413{
414 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
415 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
416 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
417 unsigned int msh = 0xfffff, hdr = 0;
418 uint64_t addr;
419 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
420 struct e1000_tx *tp = &s->tx;
421
422 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
423 op = le32_to_cpu(xp->cmd_and_length);
424 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
425 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
426 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
427 tp->tucss = xp->upper_setup.tcp_fields.tucss;
428 tp->tucso = xp->upper_setup.tcp_fields.tucso;
429 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
430 tp->paylen = op & 0xfffff;
431 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
432 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
433 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
434 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
435 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
436 tp->tso_frames = 0;
437 if (tp->tucso == 0) { // this is probably wrong
438 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
439 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
440 }
441 return;
1b0009db
AZ		 442 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
443 // data descriptor
7c23b892 444 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
1b0009db
AZ		 445 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
446 } else
447 // legacy descriptor
448 tp->cptse = 0;
7c23b892 449
8f2e8d1f
AL		 450 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
451 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
452 tp->vlan_needed = 1;
453 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
454 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
455 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
456 le16_to_cpu(dp->upper.fields.special));
457 }
458
7c23b892 459 addr = le64_to_cpu(dp->buffer_addr);
1b0009db 460 if (tp->tse && tp->cptse) {
7c23b892
AZ		 461 hdr = tp->hdr_len;
462 msh = hdr + tp->mss;
1b0009db
AZ		 463 do {
464 bytes = split_size;
465 if (tp->size + bytes > msh)
466 bytes = msh - tp->size;
467 cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
468 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
469 memmove(tp->header, tp->data, hdr);
470 tp->size = sz;
471 addr += bytes;
472 if (sz == msh) {
473 xmit_seg(s);
474 memmove(tp->data, tp->header, hdr);
475 tp->size = hdr;
476 }
477 } while (split_size -= bytes);
478 } else if (!tp->tse && tp->cptse) {
479 // context descriptor TSE is not set, while data descriptor TSE is set
480 DBGOUT(TXERR, "TCP segmentaion Error\n");
481 } else {
482 cpu_physical_memory_read(addr, tp->data + tp->size, split_size);
483 tp->size += split_size;
7c23b892 484 }
7c23b892
AZ		 485
486 if (!(txd_lower & E1000_TXD_CMD_EOP))
487 return;
1b0009db 488 if (!(tp->tse && tp->cptse && tp->size < hdr))
7c23b892
AZ		 489 xmit_seg(s);
490 tp->tso_frames = 0;
491 tp->sum_needed = 0;
8f2e8d1f 492 tp->vlan_needed = 0;
7c23b892 493 tp->size = 0;
1b0009db 494 tp->cptse = 0;
7c23b892
AZ		 495}
496
497static uint32_t
c227f099 498txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
7c23b892
AZ		 499{
500 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
501
502 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
503 return 0;
504 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
505 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
506 dp->upper.data = cpu_to_le32(txd_upper);
507 cpu_physical_memory_write(base + ((char *)&dp->upper - (char *)dp),
508 (void *)&dp->upper, sizeof(dp->upper));
509 return E1000_ICR_TXDW;
510}
511
512static void
513start_xmit(E1000State *s)
514{
c227f099 515 target_phys_addr_t base;
7c23b892
AZ		 516 struct e1000_tx_desc desc;
517 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
518
519 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
520 DBGOUT(TX, "tx disabled\n");
521 return;
522 }
523
524 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
525 base = ((uint64_t)s->mac_reg[TDBAH] << 32) + s->mac_reg[TDBAL] +
526 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
527 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
528
529 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
6106075b 530 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
7c23b892
AZ		 531 desc.upper.data);
532
533 process_tx_desc(s, &desc);
534 cause |= txdesc_writeback(base, &desc);
535
536 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
537 s->mac_reg[TDH] = 0;
538 /*
539 * the following could happen only if guest sw assigns
540 * bogus values to TDT/TDLEN.
541 * there's nothing too intelligent we could do about this.
542 */
543 if (s->mac_reg[TDH] == tdh_start) {
544 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
545 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
546 break;
547 }
548 }
549 set_ics(s, 0, cause);
550}
551
552static int
553receive_filter(E1000State *s, const uint8_t *buf, int size)
554{
af2960f9
BS		 555 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
556 static const int mta_shift[] = {4, 3, 2, 0};
7c23b892
AZ		 557 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
558
8f2e8d1f
AL		 559 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
560 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
561 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
562 ((vid >> 5) & 0x7f));
563 if ((vfta & (1 << (vid & 0x1f))) == 0)
564 return 0;
565 }
566
7c23b892
AZ		 567 if (rctl & E1000_RCTL_UPE) // promiscuous
568 return 1;
569
570 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
571 return 1;
572
573 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
574 return 1;
575
576 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
577 if (!(rp[1] & E1000_RAH_AV))
578 continue;
579 ra[0] = cpu_to_le32(rp[0]);
580 ra[1] = cpu_to_le32(rp[1]);
581 if (!memcmp(buf, (uint8_t *)ra, 6)) {
582 DBGOUT(RXFILTER,
583 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
584 (int)(rp - s->mac_reg - RA)/2,
585 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
586 return 1;
587 }
588 }
589 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
590 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
591
592 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
593 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
594 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
595 return 1;
596 DBGOUT(RXFILTER,
597 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
598 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
599 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
600 s->mac_reg[MTA + (f >> 5)]);
601
602 return 0;
603}
604
99ed7e30 605static void
a03e2aec 606e1000_set_link_status(VLANClientState *nc)
99ed7e30 607{
a03e2aec 608 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
99ed7e30
AL		 609 uint32_t old_status = s->mac_reg[STATUS];
610
a03e2aec 611 if (nc->link_down)
99ed7e30
AL		 612 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
613 else
614 s->mac_reg[STATUS] |= E1000_STATUS_LU;
615
616 if (s->mac_reg[STATUS] != old_status)
617 set_ics(s, 0, E1000_ICR_LSC);
618}
619
7c23b892 620static int
a03e2aec 621e1000_can_receive(VLANClientState *nc)
7c23b892 622{
a03e2aec 623 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
7c23b892 624
4105de67 625 return (s->mac_reg[RCTL] & E1000_RCTL_EN);
7c23b892
AZ		 626}
627
4f1c942b 628static ssize_t
a03e2aec 629e1000_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
7c23b892 630{
a03e2aec 631 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
7c23b892 632 struct e1000_rx_desc desc;
c227f099 633 target_phys_addr_t base;
7c23b892
AZ		 634 unsigned int n, rdt;
635 uint32_t rdh_start;
8f2e8d1f
AL		 636 uint16_t vlan_special = 0;
637 uint8_t vlan_status = 0, vlan_offset = 0;
7c23b892
AZ		 638
639 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
4f1c942b 640 return -1;
7c23b892
AZ		 641
642 if (size > s->rxbuf_size) {
cda9046b
MM		 643 DBGOUT(RX, "packet too large for buffers (%lu > %d)\n",
644 (unsigned long)size, s->rxbuf_size);
4f1c942b 645 return -1;
7c23b892
AZ		 646 }
647
648 if (!receive_filter(s, buf, size))
4f1c942b 649 return size;
7c23b892 650
8f2e8d1f
AL		 651 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
652 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
98835fe3 653 memmove((uint8_t *)buf + 4, buf, 12);
8f2e8d1f
AL		 654 vlan_status = E1000_RXD_STAT_VP;
655 vlan_offset = 4;
656 size -= 4;
657 }
658
7c23b892 659 rdh_start = s->mac_reg[RDH];
7c23b892
AZ		 660 do {
661 if (s->mac_reg[RDH] == s->mac_reg[RDT] && s->check_rxov) {
662 set_ics(s, 0, E1000_ICS_RXO);
4f1c942b 663 return -1;
7c23b892
AZ		 664 }
665 base = ((uint64_t)s->mac_reg[RDBAH] << 32) + s->mac_reg[RDBAL] +
666 sizeof(desc) * s->mac_reg[RDH];
667 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
8f2e8d1f
AL		 668 desc.special = vlan_special;
669 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
7c23b892
AZ		 670 if (desc.buffer_addr) {
671 cpu_physical_memory_write(le64_to_cpu(desc.buffer_addr),
8f2e8d1f 672 (void *)(buf + vlan_offset), size);
55e8d1ce 673 desc.length = cpu_to_le16(size + fcs_len(s));
7c23b892
AZ		 674 desc.status |= E1000_RXD_STAT_EOP|E1000_RXD_STAT_IXSM;
675 } else // as per intel docs; skip descriptors with null buf addr
676 DBGOUT(RX, "Null RX descriptor!!\n");
677 cpu_physical_memory_write(base, (void *)&desc, sizeof(desc));
678
679 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
680 s->mac_reg[RDH] = 0;
681 s->check_rxov = 1;
682 /* see comment in start_xmit; same here */
683 if (s->mac_reg[RDH] == rdh_start) {
684 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
685 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
686 set_ics(s, 0, E1000_ICS_RXO);
4f1c942b 687 return -1;
7c23b892
AZ		 688 }
689 } while (desc.buffer_addr == 0);
690
691 s->mac_reg[GPRC]++;
692 s->mac_reg[TPR]++;
693 n = s->mac_reg[TORL];
694 if ((s->mac_reg[TORL] += size) < n)
695 s->mac_reg[TORH]++;
696
697 n = E1000_ICS_RXT0;
698 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
699 rdt += s->mac_reg[RDLEN] / sizeof(desc);
bf16cc8f
AL		 700 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
701 s->rxbuf_min_shift)
7c23b892
AZ		 702 n |= E1000_ICS_RXDMT0;
703
704 set_ics(s, 0, n);
4f1c942b
MM		 705
706 return size;
7c23b892
AZ		 707}
708
709static uint32_t
710mac_readreg(E1000State *s, int index)
711{
712 return s->mac_reg[index];
713}
714
715static uint32_t
716mac_icr_read(E1000State *s, int index)
717{
718 uint32_t ret = s->mac_reg[ICR];
719
720 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
721 set_interrupt_cause(s, 0, 0);
722 return ret;
723}
724
725static uint32_t
726mac_read_clr4(E1000State *s, int index)
727{
728 uint32_t ret = s->mac_reg[index];
729
730 s->mac_reg[index] = 0;
731 return ret;
732}
733
734static uint32_t
735mac_read_clr8(E1000State *s, int index)
736{
737 uint32_t ret = s->mac_reg[index];
738
739 s->mac_reg[index] = 0;
740 s->mac_reg[index-1] = 0;
741 return ret;
742}
743
744static void
745mac_writereg(E1000State *s, int index, uint32_t val)
746{
747 s->mac_reg[index] = val;
748}
749
750static void
751set_rdt(E1000State *s, int index, uint32_t val)
752{
753 s->check_rxov = 0;
754 s->mac_reg[index] = val & 0xffff;
755}
756
757static void
758set_16bit(E1000State *s, int index, uint32_t val)
759{
760 s->mac_reg[index] = val & 0xffff;
761}
762
763static void
764set_dlen(E1000State *s, int index, uint32_t val)
765{
766 s->mac_reg[index] = val & 0xfff80;
767}
768
769static void
770set_tctl(E1000State *s, int index, uint32_t val)
771{
772 s->mac_reg[index] = val;
773 s->mac_reg[TDT] &= 0xffff;
774 start_xmit(s);
775}
776
777static void
778set_icr(E1000State *s, int index, uint32_t val)
779{
780 DBGOUT(INTERRUPT, "set_icr %x\n", val);
781 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
782}
783
784static void
785set_imc(E1000State *s, int index, uint32_t val)
786{
787 s->mac_reg[IMS] &= ~val;
788 set_ics(s, 0, 0);
789}
790
791static void
792set_ims(E1000State *s, int index, uint32_t val)
793{
794 s->mac_reg[IMS] |= val;
795 set_ics(s, 0, 0);
796}
797
798#define getreg(x) [x] = mac_readreg
799static uint32_t (*macreg_readops[])(E1000State *, int) = {
800 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
801 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
802 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
803 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
b1332393 804 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
a00b2335
KA		 805 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
806 getreg(TDLEN), getreg(RDLEN),
7c23b892
AZ		 807
808 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
809 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
810 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
811 [CRCERRS ... MPC] = &mac_readreg,
812 [RA ... RA+31] = &mac_readreg,
813 [MTA ... MTA+127] = &mac_readreg,
8f2e8d1f 814 [VFTA ... VFTA+127] = &mac_readreg,
7c23b892 815};
b1503cda 816enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
7c23b892
AZ		 817
818#define putreg(x) [x] = mac_writereg
819static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
820 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
821 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
cab3c825 822 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
7c23b892
AZ		 823 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
824 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
825 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
826 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
cab3c825 827 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
7c23b892
AZ		 828 [RA ... RA+31] = &mac_writereg,
829 [MTA ... MTA+127] = &mac_writereg,
8f2e8d1f 830 [VFTA ... VFTA+127] = &mac_writereg,
7c23b892 831};
b1503cda 832enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
7c23b892
AZ		 833
834static void
c227f099 835e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
7c23b892
AZ		 836{
837 E1000State *s = opaque;
8da3ff18 838 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892 839
6b59fc74
AJ		 840#ifdef TARGET_WORDS_BIGENDIAN
841 val = bswap32(val);
842#endif
7c23b892 843 if (index < NWRITEOPS && macreg_writeops[index])
6b59fc74 844 macreg_writeops[index](s, index, val);
7c23b892
AZ		 845 else if (index < NREADOPS && macreg_readops[index])
846 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val);
847 else
848 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08x\n",
849 index<<2, val);
850}
851
852static void
c227f099 853e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
7c23b892
AZ		 854{
855 // emulate hw without byte enables: no RMW
856 e1000_mmio_writel(opaque, addr & ~3,
6b59fc74 857 (val & 0xffff) << (8*(addr & 3)));
7c23b892
AZ		 858}
859
860static void
c227f099 861e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
7c23b892
AZ		 862{
863 // emulate hw without byte enables: no RMW
864 e1000_mmio_writel(opaque, addr & ~3,
6b59fc74 865 (val & 0xff) << (8*(addr & 3)));
7c23b892
AZ		 866}
867
868static uint32_t
c227f099 869e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
7c23b892
AZ		 870{
871 E1000State *s = opaque;
8da3ff18 872 unsigned int index = (addr & 0x1ffff) >> 2;
7c23b892
AZ		 873
874 if (index < NREADOPS && macreg_readops[index])
6b59fc74
AJ		 875 {
876 uint32_t val = macreg_readops[index](s, index);
877#ifdef TARGET_WORDS_BIGENDIAN
878 val = bswap32(val);
879#endif
880 return val;
881 }
7c23b892
AZ		 882 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
883 return 0;
884}
885
886static uint32_t
c227f099 887e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
7c23b892 888{
6b59fc74 889 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
7c23b892
AZ		 890 (8 * (addr & 3))) & 0xff;
891}
892
893static uint32_t
c227f099 894e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
7c23b892 895{
6b59fc74
AJ		 896 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
897 (8 * (addr & 3))) & 0xffff;
7c23b892
AZ		 898}
899
e482dc3e 900static bool is_version_1(void *opaque, int version_id)
7c23b892 901{
e482dc3e 902 return version_id == 1;
7c23b892
AZ		 903}
904
e482dc3e
JQ		 905static const VMStateDescription vmstate_e1000 = {
906 .name = "e1000",
907 .version_id = 2,
908 .minimum_version_id = 1,
909 .minimum_version_id_old = 1,
910 .fields = (VMStateField []) {
911 VMSTATE_PCI_DEVICE(dev, E1000State),
912 VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
913 VMSTATE_UNUSED(4), /* Was mmio_base. */
914 VMSTATE_UINT32(rxbuf_size, E1000State),
915 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
916 VMSTATE_UINT32(eecd_state.val_in, E1000State),
917 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
918 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
919 VMSTATE_UINT16(eecd_state.reading, E1000State),
920 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
921 VMSTATE_UINT8(tx.ipcss, E1000State),
922 VMSTATE_UINT8(tx.ipcso, E1000State),
923 VMSTATE_UINT16(tx.ipcse, E1000State),
924 VMSTATE_UINT8(tx.tucss, E1000State),
925 VMSTATE_UINT8(tx.tucso, E1000State),
926 VMSTATE_UINT16(tx.tucse, E1000State),
927 VMSTATE_UINT32(tx.paylen, E1000State),
928 VMSTATE_UINT8(tx.hdr_len, E1000State),
929 VMSTATE_UINT16(tx.mss, E1000State),
930 VMSTATE_UINT16(tx.size, E1000State),
931 VMSTATE_UINT16(tx.tso_frames, E1000State),
932 VMSTATE_UINT8(tx.sum_needed, E1000State),
933 VMSTATE_INT8(tx.ip, E1000State),
934 VMSTATE_INT8(tx.tcp, E1000State),
935 VMSTATE_BUFFER(tx.header, E1000State),
936 VMSTATE_BUFFER(tx.data, E1000State),
937 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
938 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
939 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
940 VMSTATE_UINT32(mac_reg[EECD], E1000State),
941 VMSTATE_UINT32(mac_reg[EERD], E1000State),
942 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
943 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
944 VMSTATE_UINT32(mac_reg[ICR], E1000State),
945 VMSTATE_UINT32(mac_reg[ICS], E1000State),
946 VMSTATE_UINT32(mac_reg[IMC], E1000State),
947 VMSTATE_UINT32(mac_reg[IMS], E1000State),
948 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
949 VMSTATE_UINT32(mac_reg[MANC], E1000State),
950 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
951 VMSTATE_UINT32(mac_reg[MPC], E1000State),
952 VMSTATE_UINT32(mac_reg[PBA], E1000State),
953 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
954 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
955 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
956 VMSTATE_UINT32(mac_reg[RDH], E1000State),
957 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
958 VMSTATE_UINT32(mac_reg[RDT], E1000State),
959 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
960 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
961 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
962 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
963 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
964 VMSTATE_UINT32(mac_reg[TDH], E1000State),
965 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
966 VMSTATE_UINT32(mac_reg[TDT], E1000State),
967 VMSTATE_UINT32(mac_reg[TORH], E1000State),
968 VMSTATE_UINT32(mac_reg[TORL], E1000State),
969 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
970 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
971 VMSTATE_UINT32(mac_reg[TPR], E1000State),
972 VMSTATE_UINT32(mac_reg[TPT], E1000State),
973 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
974 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
975 VMSTATE_UINT32(mac_reg[VET], E1000State),
976 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
977 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
978 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
979 VMSTATE_END_OF_LIST()
980 }
981};
7c23b892 982
88b4e9db 983static const uint16_t e1000_eeprom_template[64] = {
7c23b892
AZ		 984 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
985 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
986 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
987 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
988 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
989 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
990 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
991 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
992};
993
88b4e9db 994static const uint16_t phy_reg_init[] = {
7c23b892
AZ		 995 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
996 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
997 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
998 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
999 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
700f6e2c 1000 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
7c23b892
AZ		 1001};
1002
88b4e9db 1003static const uint32_t mac_reg_init[] = {
7c23b892
AZ		 1004 [PBA] = 0x00100030,
1005 [LEDCTL] = 0x602,
1006 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
1007 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
1008 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
1009 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
1010 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
1011 E1000_STATUS_LU,
1012 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
1013 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
1014 E1000_MANC_RMCP_EN,
1015};
1016
1017/* PCI interface */
1018
d60efc6b 1019static CPUWriteMemoryFunc * const e1000_mmio_write[] = {
7c23b892
AZ		 1020 e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel
1021};
1022
d60efc6b 1023static CPUReadMemoryFunc * const e1000_mmio_read[] = {
7c23b892
AZ		 1024 e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl
1025};
1026
1027static void
1028e1000_mmio_map(PCIDevice *pci_dev, int region_num,
6e355d90 1029 pcibus_t addr, pcibus_t size, int type)
7c23b892 1030{
7d9e52bd 1031 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
f65ed4c1
AL		 1032 int i;
1033 const uint32_t excluded_regs[] = {
1034 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1035 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1036 };
1037
7c23b892 1038
89e8b13c
IY		 1039 DBGOUT(MMIO, "e1000_mmio_map addr=0x%08"FMT_PCIBUS" 0x%08"FMT_PCIBUS"\n",
1040 addr, size);
7c23b892 1041
7c23b892 1042 cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
f65ed4c1
AL		 1043 qemu_register_coalesced_mmio(addr, excluded_regs[0]);
1044
1045 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
1046 qemu_register_coalesced_mmio(addr + excluded_regs[i] + 4,
1047 excluded_regs[i + 1] -
1048 excluded_regs[i] - 4);
7c23b892
AZ		 1049}
1050
b946a153 1051static void
a03e2aec 1052e1000_cleanup(VLANClientState *nc)
b946a153 1053{
a03e2aec 1054 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 1055
a03e2aec 1056 s->nic = NULL;
b946a153
AL		 1057}
1058
4b09be85
AL		 1059static int
1060pci_e1000_uninit(PCIDevice *dev)
1061{
7d9e52bd 1062 E1000State *d = DO_UPCAST(E1000State, dev, dev);
4b09be85
AL		 1063
1064 cpu_unregister_io_memory(d->mmio_index);
a03e2aec 1065 qemu_del_vlan_client(&d->nic->nc);
4b09be85
AL		 1066 return 0;
1067}
1068
32c86e95
BS		 1069static void e1000_reset(void *opaque)
1070{
1071 E1000State *d = opaque;
1072
1073 memset(d->phy_reg, 0, sizeof d->phy_reg);
1074 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
1075 memset(d->mac_reg, 0, sizeof d->mac_reg);
1076 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
1077 d->rxbuf_min_shift = 1;
1078 memset(&d->tx, 0, sizeof d->tx);
1079}
1080
a03e2aec
MM		 1081static NetClientInfo net_e1000_info = {
1082 .type = NET_CLIENT_TYPE_NIC,
1083 .size = sizeof(NICState),
1084 .can_receive = e1000_can_receive,
1085 .receive = e1000_receive,
1086 .cleanup = e1000_cleanup,
1087 .link_status_changed = e1000_set_link_status,
1088};
1089
81a322d4 1090static int pci_e1000_init(PCIDevice *pci_dev)
7c23b892 1091{
7d9e52bd 1092 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
7c23b892 1093 uint8_t *pci_conf;
7c23b892 1094 uint16_t checksum = 0;
7c23b892 1095 int i;
fbdaa002 1096 uint8_t *macaddr;
aff427a1 1097
7c23b892 1098 pci_conf = d->dev.config;
7c23b892 1099
deb54399
AL		 1100 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
1101 pci_config_set_device_id(pci_conf, E1000_DEVID);
a9cbacb0
MT		 1102 /* TODO: we have no capabilities, so why is this bit set? */
1103 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST);
1104 pci_conf[PCI_REVISION_ID] = 0x03;
173a543b 1105 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
a9cbacb0
MT		 1106 /* TODO: RST# value should be 0, PCI spec 6.2.4 */
1107 pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
7c23b892 1108
a9cbacb0
MT		 1109 /* TODO: RST# value should be 0 if programmable, PCI spec 6.2.4 */
1110 pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
7c23b892 1111
1eed09cb 1112 d->mmio_index = cpu_register_io_memory(e1000_mmio_read,
7c23b892
AZ		 1113 e1000_mmio_write, d);
1114
28c2c264 1115 pci_register_bar((PCIDevice *)d, 0, PNPMMIO_SIZE,
0392a017 1116 PCI_BASE_ADDRESS_SPACE_MEMORY, e1000_mmio_map);
7c23b892 1117
28c2c264 1118 pci_register_bar((PCIDevice *)d, 1, IOPORT_SIZE,
0392a017 1119 PCI_BASE_ADDRESS_SPACE_IO, ioport_map);
7c23b892 1120
7c23b892
AZ		 1121 memmove(d->eeprom_data, e1000_eeprom_template,
1122 sizeof e1000_eeprom_template);
fbdaa002
GH		 1123 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1124 macaddr = d->conf.macaddr.a;
7c23b892 1125 for (i = 0; i < 3; i++)
9d07d757 1126 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
7c23b892
AZ		 1127 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1128 checksum += d->eeprom_data[i];
1129 checksum = (uint16_t) EEPROM_SUM - checksum;
1130 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1131
a03e2aec
MM		 1132 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
1133 d->dev.qdev.info->name, d->dev.qdev.id, d);
7c23b892 1134
a03e2aec 1135 qemu_format_nic_info_str(&d->nic->nc, macaddr);
81a322d4 1136 return 0;
9d07d757 1137}
72da4208 1138
fbdaa002
GH		 1139static void qdev_e1000_reset(DeviceState *dev)
1140{
1141 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1142 e1000_reset(d);
1143}
1144
0aab0d3a 1145static PCIDeviceInfo e1000_info = {
fbdaa002
GH		 1146 .qdev.name = "e1000",
1147 .qdev.desc = "Intel Gigabit Ethernet",
1148 .qdev.size = sizeof(E1000State),
1149 .qdev.reset = qdev_e1000_reset,
be73cfe2 1150 .qdev.vmsd = &vmstate_e1000,
fbdaa002
GH		 1151 .init = pci_e1000_init,
1152 .exit = pci_e1000_uninit,
8c52c8f3 1153 .romfile = "pxe-e1000.bin",
fbdaa002
GH		 1154 .qdev.props = (Property[]) {
1155 DEFINE_NIC_PROPERTIES(E1000State, conf),
1156 DEFINE_PROP_END_OF_LIST(),
1157 }
0aab0d3a
GH		 1158};
1159
9d07d757
PB		 1160static void e1000_register_devices(void)
1161{
0aab0d3a 1162 pci_qdev_register(&e1000_info);
7c23b892 1163}
9d07d757
PB		 1164
1165device_init(e1000_register_devices)
Empty description
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