[qemu.git] / hw / arm / exynos4210.c

/*
 *  Samsung exynos4210 SoC emulation
 *
 *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
 *    Maksim Kozlov <[email protected]>
 *    Evgeny Voevodin <[email protected]>
 *    Igor Mitsyanko  <[email protected]>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "qemu/log.h"
#include "cpu.h"
#include "hw/cpu/a9mpcore.h"
#include "hw/boards.h"
#include "sysemu/sysemu.h"
#include "hw/sysbus.h"
#include "hw/arm/arm.h"
#include "hw/loader.h"
#include "hw/arm/exynos4210.h"
#include "hw/sd/sdhci.h"
#include "hw/usb/hcd-ehci.h"

#define EXYNOS4210_CHIPID_ADDR         0x10000000

/* PWM */
#define EXYNOS4210_PWM_BASE_ADDR       0x139D0000

/* RTC */
#define EXYNOS4210_RTC_BASE_ADDR       0x10070000

/* MCT */
#define EXYNOS4210_MCT_BASE_ADDR       0x10050000

/* I2C */
#define EXYNOS4210_I2C_SHIFT           0x00010000
#define EXYNOS4210_I2C_BASE_ADDR       0x13860000
/* Interrupt Group of External Interrupt Combiner for I2C */
#define EXYNOS4210_I2C_INTG            27
#define EXYNOS4210_HDMI_INTG           16

/* UART's definitions */
#define EXYNOS4210_UART0_BASE_ADDR     0x13800000
#define EXYNOS4210_UART1_BASE_ADDR     0x13810000
#define EXYNOS4210_UART2_BASE_ADDR     0x13820000
#define EXYNOS4210_UART3_BASE_ADDR     0x13830000
#define EXYNOS4210_UART0_FIFO_SIZE     256
#define EXYNOS4210_UART1_FIFO_SIZE     64
#define EXYNOS4210_UART2_FIFO_SIZE     16
#define EXYNOS4210_UART3_FIFO_SIZE     16
/* Interrupt Group of External Interrupt Combiner for UART */
#define EXYNOS4210_UART_INT_GRP        26

/* External GIC */
#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR    0x10480000
#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR   0x10490000

/* Combiner */
#define EXYNOS4210_EXT_COMBINER_BASE_ADDR   0x10440000
#define EXYNOS4210_INT_COMBINER_BASE_ADDR   0x10448000

/* SD/MMC host controllers */
#define EXYNOS4210_SDHCI_CAPABILITIES       0x05E80080
#define EXYNOS4210_SDHCI_BASE_ADDR          0x12510000
#define EXYNOS4210_SDHCI_ADDR(n)            (EXYNOS4210_SDHCI_BASE_ADDR + \
                                                0x00010000 * (n))
#define EXYNOS4210_SDHCI_NUMBER             4

/* PMU SFR base address */
#define EXYNOS4210_PMU_BASE_ADDR            0x10020000

/* Clock controller SFR base address */
#define EXYNOS4210_CLK_BASE_ADDR            0x10030000

/* PRNG/HASH SFR base address */
#define EXYNOS4210_RNG_BASE_ADDR            0x10830400

/* Display controllers (FIMD) */
#define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000

/* EHCI */
#define EXYNOS4210_EHCI_BASE_ADDR           0x12580000

static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
                                    0x09, 0x00, 0x00, 0x00 };

static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset,
                                               unsigned size)
{
    assert(offset < sizeof(chipid_and_omr));
    return chipid_and_omr[offset];
}

static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset,
                                            uint64_t value, unsigned size)
{
    return;
}

static const MemoryRegionOps exynos4210_chipid_and_omr_ops = {
    .read = exynos4210_chipid_and_omr_read,
    .write = exynos4210_chipid_and_omr_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .impl = {
        .max_access_size = 1,
    }
};

void exynos4210_write_secondary(ARMCPU *cpu,
        const struct arm_boot_info *info)
{
    int n;
    uint32_t smpboot[] = {
        0xe59f3034, /* ldr r3, External gic_cpu_if */
        0xe59f2034, /* ldr r2, Internal gic_cpu_if */
        0xe59f0034, /* ldr r0, startaddr */
        0xe3a01001, /* mov r1, #1 */
        0xe5821000, /* str r1, [r2] */
        0xe5831000, /* str r1, [r3] */
        0xe3a010ff, /* mov r1, #0xff */
        0xe5821004, /* str r1, [r2, #4] */
        0xe5831004, /* str r1, [r3, #4] */
        0xf57ff04f, /* dsb */
        0xe320f003, /* wfi */
        0xe5901000, /* ldr     r1, [r0] */
        0xe1110001, /* tst     r1, r1 */
        0x0afffffb, /* beq     <wfi> */
        0xe12fff11, /* bx      r1 */
        EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
        0,          /* gic_cpu_if: base address of Internal GIC CPU interface */
        0           /* bootreg: Boot register address is held here */
    };
    smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
    smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
    for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
        smpboot[n] = tswap32(smpboot[n]);
    }
    rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
                       info->smp_loader_start);
}

static uint64_t exynos4210_calc_affinity(int cpu)
{
    /* Exynos4210 has 0x9 as cluster ID */
    return (0x9 << ARM_AFF1_SHIFT) | cpu;
}

Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
{
    Exynos4210State *s = g_new0(Exynos4210State, 1);
    qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
    SysBusDevice *busdev;
    DeviceState *dev;
    int i, n;

    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
        Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9"));

        /* By default A9 CPUs have EL3 enabled.  This board does not currently
         * support EL3 so the CPU EL3 property is disabled before realization.
         */
        if (object_property_find(cpuobj, "has_el3", NULL)) {
            object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
        }

        s->cpu[n] = ARM_CPU(cpuobj);
        object_property_set_int(cpuobj, exynos4210_calc_affinity(n),
                                "mp-affinity", &error_abort);
        object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
                                "reset-cbar", &error_abort);
        object_property_set_bool(cpuobj, true, "realized", &error_fatal);
    }

    /*** IRQs ***/

    s->irq_table = exynos4210_init_irq(&s->irqs);

    /* IRQ Gate */
    for (i = 0; i < EXYNOS4210_NCPUS; i++) {
        dev = qdev_create(NULL, "exynos4210.irq_gate");
        qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
        qdev_init_nofail(dev);
        /* Get IRQ Gate input in gate_irq */
        for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
            gate_irq[i][n] = qdev_get_gpio_in(dev, n);
        }
        busdev = SYS_BUS_DEVICE(dev);

        /* Connect IRQ Gate output to CPU's IRQ line */
        sysbus_connect_irq(busdev, 0,
                           qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
    }

    /* Private memory region and Internal GIC */
    dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
        sysbus_connect_irq(busdev, n, gate_irq[n][0]);
    }
    for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
    }

    /* Cache controller */
    sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);

    /* External GIC */
    dev = qdev_create(NULL, "exynos4210.gic");
    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    /* Map CPU interface */
    sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
    /* Map Distributer interface */
    sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
        sysbus_connect_irq(busdev, n, gate_irq[n][1]);
    }
    for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
    }

    /* Internal Interrupt Combiner */
    dev = qdev_create(NULL, "exynos4210.combiner");
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
        sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
    }
    exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
    sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);

    /* External Interrupt Combiner */
    dev = qdev_create(NULL, "exynos4210.combiner");
    qdev_prop_set_uint32(dev, "external", 1);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
        sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
    }
    exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
    sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);

    /* Initialize board IRQs. */
    exynos4210_init_board_irqs(&s->irqs);

    /*** Memory ***/

    /* Chip-ID and OMR */
    memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops,
        NULL, "exynos4210.chipid", sizeof(chipid_and_omr));
    memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
                                &s->chipid_mem);

    /* Internal ROM */
    memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom",
                           EXYNOS4210_IROM_SIZE, &error_fatal);
    memory_region_set_readonly(&s->irom_mem, true);
    memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
                                &s->irom_mem);
    /* mirror of iROM */
    memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias",
                             &s->irom_mem,
                             0,
                             EXYNOS4210_IROM_SIZE);
    memory_region_set_readonly(&s->irom_alias_mem, true);
    memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
                                &s->irom_alias_mem);

    /* Internal RAM */
    memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram",
                           EXYNOS4210_IRAM_SIZE, &error_fatal);
    memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
                                &s->iram_mem);

   /* PMU.
    * The only reason of existence at the moment is that secondary CPU boot
    * loader uses PMU INFORM5 register as a holding pen.
    */
    sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);

    sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);
    sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL);

    /* PWM */
    sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
                          s->irq_table[exynos4210_get_irq(22, 0)],
                          s->irq_table[exynos4210_get_irq(22, 1)],
                          s->irq_table[exynos4210_get_irq(22, 2)],
                          s->irq_table[exynos4210_get_irq(22, 3)],
                          s->irq_table[exynos4210_get_irq(22, 4)],
                          NULL);
    /* RTC */
    sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
                          s->irq_table[exynos4210_get_irq(23, 0)],
                          s->irq_table[exynos4210_get_irq(23, 1)],
                          NULL);

    /* Multi Core Timer */
    dev = qdev_create(NULL, "exynos4210.mct");
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    for (n = 0; n < 4; n++) {
        /* Connect global timer interrupts to Combiner gpio_in */
        sysbus_connect_irq(busdev, n,
                s->irq_table[exynos4210_get_irq(1, 4 + n)]);
    }
    /* Connect local timer interrupts to Combiner gpio_in */
    sysbus_connect_irq(busdev, 4,
            s->irq_table[exynos4210_get_irq(51, 0)]);
    sysbus_connect_irq(busdev, 5,
            s->irq_table[exynos4210_get_irq(35, 3)]);
    sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);

    /*** I2C ***/
    for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
        uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
        qemu_irq i2c_irq;

        if (n < 8) {
            i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
        } else {
            i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
        }

        dev = qdev_create(NULL, "exynos4210.i2c");
        qdev_init_nofail(dev);
        busdev = SYS_BUS_DEVICE(dev);
        sysbus_connect_irq(busdev, 0, i2c_irq);
        sysbus_mmio_map(busdev, 0, addr);
        s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
    }


    /*** UARTs ***/
    exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
                           EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0),
                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);

    exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
                           EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1),
                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);

    exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
                           EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2),
                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);

    exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
                           EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3),
                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);

    /*** SD/MMC host controllers ***/
    for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) {
        DeviceState *carddev;
        BlockBackend *blk;
        DriveInfo *di;

        /* Compatible with:
         * - SD Host Controller Specification Version 2.0
         * - SDIO Specification Version 2.0
         * - MMC Specification Version 4.3
         * - SDMA
         * - ADMA2
         *
         * As this part of the Exynos4210 is not publically available,
         * we used the "HS-MMC Controller S3C2416X RISC Microprocessor"
         * public datasheet which is very similar (implementing
         * MMC Specification Version 4.0 being the only difference noted)
         */
        dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
        qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
        qdev_init_nofail(dev);

        busdev = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n));
        sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]);

        di = drive_get(IF_SD, 0, n);
        blk = di ? blk_by_legacy_dinfo(di) : NULL;
        carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
        qdev_prop_set_drive(carddev, "drive", blk, &error_abort);
        qdev_init_nofail(carddev);
    }

    /*** Display controller (FIMD) ***/
    sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
            s->irq_table[exynos4210_get_irq(11, 0)],
            s->irq_table[exynos4210_get_irq(11, 1)],
            s->irq_table[exynos4210_get_irq(11, 2)],
            NULL);

    sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
            s->irq_table[exynos4210_get_irq(28, 3)]);

    return s;
}
Commit	Line	Data
0caa7113 EV	1	/*
	2	* Samsung exynos4210 SoC emulation
	3	*
	4	* Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
	5	* Maksim Kozlov <[email protected]>
	6	* Evgeny Voevodin <[email protected]>
	7	* Igor Mitsyanko <[email protected]>
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	17	* for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along
	20	* with this program; if not, see <http://www.gnu.org/licenses/>.
	21	*
	22	*/
	23
12b16722	24	#include "qemu/osdep.h"
da34e65c	25	#include "qapi/error.h"
4771d756	26	#include "qemu-common.h"
1e0228fd	27	#include "qemu/log.h"
4771d756	28	#include "cpu.h"
9e883790	29	#include "hw/cpu/a9mpcore.h"
83c9f4ca	30	#include "hw/boards.h"
9c17d615	31	#include "sysemu/sysemu.h"
83c9f4ca	32	#include "hw/sysbus.h"
bd2be150	33	#include "hw/arm/arm.h"
83c9f4ca	34	#include "hw/loader.h"
0d09e41a	35	#include "hw/arm/exynos4210.h"
c2de81e2	36	#include "hw/sd/sdhci.h"
83c9f4ca	37	#include "hw/usb/hcd-ehci.h"
0caa7113 EV	38
	39	#define EXYNOS4210_CHIPID_ADDR 0x10000000
	40
62db8bf3 EV	41	/* PWM */
	42	#define EXYNOS4210_PWM_BASE_ADDR 0x139D0000
	43
7bdf43a7 OO	44	/* RTC */
	45	#define EXYNOS4210_RTC_BASE_ADDR 0x10070000
	46
12c775db EV	47	/* MCT */
	48	#define EXYNOS4210_MCT_BASE_ADDR 0x10050000
	49
ffbbe7d0 MI	50	/* I2C */
	51	#define EXYNOS4210_I2C_SHIFT 0x00010000
	52	#define EXYNOS4210_I2C_BASE_ADDR 0x13860000
	53	/* Interrupt Group of External Interrupt Combiner for I2C */
	54	#define EXYNOS4210_I2C_INTG 27
	55	#define EXYNOS4210_HDMI_INTG 16
	56
e5a4914e MK	57	/* UART's definitions */
	58	#define EXYNOS4210_UART0_BASE_ADDR 0x13800000
	59	#define EXYNOS4210_UART1_BASE_ADDR 0x13810000
	60	#define EXYNOS4210_UART2_BASE_ADDR 0x13820000
	61	#define EXYNOS4210_UART3_BASE_ADDR 0x13830000
	62	#define EXYNOS4210_UART0_FIFO_SIZE 256
	63	#define EXYNOS4210_UART1_FIFO_SIZE 64
	64	#define EXYNOS4210_UART2_FIFO_SIZE 16
	65	#define EXYNOS4210_UART3_FIFO_SIZE 16
	66	/* Interrupt Group of External Interrupt Combiner for UART */
	67	#define EXYNOS4210_UART_INT_GRP 26
	68
0caa7113 EV	69	/* External GIC */
	70	#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000
	71	#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000
	72
	73	/* Combiner */
	74	#define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000
	75	#define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000
	76
d77b71c2 KK	77	/* SD/MMC host controllers */
	78	#define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080
	79	#define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000
	80	#define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \
	81	0x00010000 * (n))
	82	#define EXYNOS4210_SDHCI_NUMBER 4
	83
df91b48f MK	84	/* PMU SFR base address */
	85	#define EXYNOS4210_PMU_BASE_ADDR 0x10020000
	86
1e0228fd KK	87	/* Clock controller SFR base address */
	88	#define EXYNOS4210_CLK_BASE_ADDR 0x10030000
	89
499ca137 KK	90	/* PRNG/HASH SFR base address */
	91	#define EXYNOS4210_RNG_BASE_ADDR 0x10830400
	92
30628cb1 MI	93	/* Display controllers (FIMD) */
	94	#define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000
	95
358d615b LW	96	/* EHCI */
	97	#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
	98
0caa7113 EV	99	static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
	100	0x09, 0x00, 0x00, 0x00 };
	101
11a5e482 IM	102	static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset,
	103	unsigned size)
	104	{
	105	assert(offset < sizeof(chipid_and_omr));
	106	return chipid_and_omr[offset];
	107	}
	108
	109	static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset,
	110	uint64_t value, unsigned size)
	111	{
	112	return;
	113	}
	114
	115	static const MemoryRegionOps exynos4210_chipid_and_omr_ops = {
	116	.read = exynos4210_chipid_and_omr_read,
	117	.write = exynos4210_chipid_and_omr_write,
	118	.endianness = DEVICE_NATIVE_ENDIAN,
	119	.impl = {
	120	.max_access_size = 1,
	121	}
	122	};
	123
9543b0cd	124	void exynos4210_write_secondary(ARMCPU *cpu,
3f088e36 EV	125	const struct arm_boot_info *info)
	126	{
	127	int n;
	128	uint32_t smpboot[] = {
bf471f79 PM	129	0xe59f3034, /* ldr r3, External gic_cpu_if */
	130	0xe59f2034, /* ldr r2, Internal gic_cpu_if */
	131	0xe59f0034, /* ldr r0, startaddr */
3f088e36 EV	132	0xe3a01001, /* mov r1, #1 */
	133	0xe5821000, /* str r1, [r2] */
	134	0xe5831000, /* str r1, [r3] */
bf471f79 PM	135	0xe3a010ff, /* mov r1, #0xff */
	136	0xe5821004, /* str r1, [r2, #4] */
	137	0xe5831004, /* str r1, [r3, #4] */
	138	0xf57ff04f, /* dsb */
3f088e36 EV	139	0xe320f003, /* wfi */
	140	0xe5901000, /* ldr r1, [r0] */
	141	0xe1110001, /* tst r1, r1 */
	142	0x0afffffb, /* beq <wfi> */
	143	0xe12fff11, /* bx r1 */
	144	EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
	145	0, /* gic_cpu_if: base address of Internal GIC CPU interface */
	146	0 /* bootreg: Boot register address is held here */
	147	};
	148	smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
	149	smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
	150	for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
	151	smpboot[n] = tswap32(smpboot[n]);
	152	}
	153	rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
	154	info->smp_loader_start);
	155	}
	156
f3a6339a KK	157	static uint64_t exynos4210_calc_affinity(int cpu)
f3a6339a KK	158	{
f3a6339a	159	/* Exynos4210 has 0x9 as cluster ID */
4a4ff4c5	160	return (0x9 << ARM_AFF1_SHIFT) \| cpu;
f3a6339a KK	161	}
f3a6339a KK	162
a2f2f624	163	Exynos4210State exynos4210_init(MemoryRegion system_mem)
0caa7113	164	{
76a82ced	165	Exynos4210State *s = g_new0(Exynos4210State, 1);
61558e7a	166	qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
0caa7113	167	SysBusDevice *busdev;
310150c0 KK	168	DeviceState *dev;
310150c0 KK	169	int i, n;
4719ab91	170
0caa7113	171	for (n = 0; n < EXYNOS4210_NCPUS; n++) {
ba1ba5cc	172	Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9"));
4719ab91	173
61e2f352 GB	174	/* By default A9 CPUs have EL3 enabled. This board does not currently
	175	* support EL3 so the CPU EL3 property is disabled before realization.
	176	*/
	177	if (object_property_find(cpuobj, "has_el3", NULL)) {
007b0657	178	object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
61e2f352 GB	179	}
61e2f352 GB	180
4719ab91	181	s->cpu[n] = ARM_CPU(cpuobj);
f3a6339a KK	182	object_property_set_int(cpuobj, exynos4210_calc_affinity(n),
f3a6339a KK	183	"mp-affinity", &error_abort);
4719ab91 PM	184	object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
4719ab91 PM	185	"reset-cbar", &error_abort);
007b0657	186	object_property_set_bool(cpuobj, true, "realized", &error_fatal);
0caa7113 EV	187	}
	188
	189	/* IRQs */
	190
	191	s->irq_table = exynos4210_init_irq(&s->irqs);
	192
	193	/* IRQ Gate */
61558e7a EV	194	for (i = 0; i < EXYNOS4210_NCPUS; i++) {
	195	dev = qdev_create(NULL, "exynos4210.irq_gate");
	196	qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
	197	qdev_init_nofail(dev);
	198	/* Get IRQ Gate input in gate_irq */
	199	for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
	200	gate_irq[i][n] = qdev_get_gpio_in(dev, n);
	201	}
1356b98d	202	busdev = SYS_BUS_DEVICE(dev);
61558e7a	203
ad666d91 PM	204	/* Connect IRQ Gate output to CPU's IRQ line */
	205	sysbus_connect_irq(busdev, 0,
	206	qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
0caa7113 EV	207	}
	208
	209	/* Private memory region and Internal GIC */
9e883790	210	dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
0caa7113 EV	211	qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
0caa7113 EV	212	qdev_init_nofail(dev);
1356b98d	213	busdev = SYS_BUS_DEVICE(dev);
0caa7113 EV	214	sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
0caa7113 EV	215	for (n = 0; n < EXYNOS4210_NCPUS; n++) {
61558e7a	216	sysbus_connect_irq(busdev, n, gate_irq[n][0]);
0caa7113 EV	217	}
	218	for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
	219	s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
	220	}
	221
	222	/* Cache controller */
	223	sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
	224
	225	/* External GIC */
	226	dev = qdev_create(NULL, "exynos4210.gic");
	227	qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
	228	qdev_init_nofail(dev);
1356b98d	229	busdev = SYS_BUS_DEVICE(dev);
0caa7113 EV	230	/* Map CPU interface */
	231	sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
	232	/* Map Distributer interface */
	233	sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
	234	for (n = 0; n < EXYNOS4210_NCPUS; n++) {
61558e7a	235	sysbus_connect_irq(busdev, n, gate_irq[n][1]);
0caa7113 EV	236	}
	237	for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
	238	s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
	239	}
	240
	241	/* Internal Interrupt Combiner */
	242	dev = qdev_create(NULL, "exynos4210.combiner");
	243	qdev_init_nofail(dev);
1356b98d	244	busdev = SYS_BUS_DEVICE(dev);
0caa7113 EV	245	for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
	246	sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
	247	}
	248	exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
	249	sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
	250
	251	/* External Interrupt Combiner */
	252	dev = qdev_create(NULL, "exynos4210.combiner");
	253	qdev_prop_set_uint32(dev, "external", 1);
	254	qdev_init_nofail(dev);
1356b98d	255	busdev = SYS_BUS_DEVICE(dev);
0caa7113 EV	256	for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
	257	sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
	258	}
	259	exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
	260	sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
	261
	262	/* Initialize board IRQs. */
	263	exynos4210_init_board_irqs(&s->irqs);
	264
	265	/* Memory */
	266
	267	/* Chip-ID and OMR */
2c9b15ca	268	memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops,
11a5e482	269	NULL, "exynos4210.chipid", sizeof(chipid_and_omr));
0caa7113 EV	270	memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
	271	&s->chipid_mem);
	272
	273	/* Internal ROM */
98a99ce0	274	memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom",
f8ed85ac	275	EXYNOS4210_IROM_SIZE, &error_fatal);
0caa7113 EV	276	memory_region_set_readonly(&s->irom_mem, true);
	277	memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
	278	&s->irom_mem);
	279	/* mirror of iROM */
2c9b15ca	280	memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias",
0caa7113	281	&s->irom_mem,
7892df06	282	0,
0caa7113 EV	283	EXYNOS4210_IROM_SIZE);
	284	memory_region_set_readonly(&s->irom_alias_mem, true);
	285	memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
	286	&s->irom_alias_mem);
	287
	288	/* Internal RAM */
98a99ce0	289	memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram",
f8ed85ac	290	EXYNOS4210_IRAM_SIZE, &error_fatal);
0caa7113 EV	291	memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
	292	&s->iram_mem);
	293
df91b48f MK	294	/* PMU.
	295	* The only reason of existence at the moment is that secondary CPU boot
	296	* loader uses PMU INFORM5 register as a holding pen.
	297	*/
	298	sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
	299
1e0228fd	300	sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);
499ca137	301	sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL);
1e0228fd	302
62db8bf3 EV	303	/* PWM */
	304	sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
	305	s->irq_table[exynos4210_get_irq(22, 0)],
	306	s->irq_table[exynos4210_get_irq(22, 1)],
	307	s->irq_table[exynos4210_get_irq(22, 2)],
	308	s->irq_table[exynos4210_get_irq(22, 3)],
	309	s->irq_table[exynos4210_get_irq(22, 4)],
	310	NULL);
7bdf43a7 OO	311	/* RTC */
	312	sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
	313	s->irq_table[exynos4210_get_irq(23, 0)],
	314	s->irq_table[exynos4210_get_irq(23, 1)],
	315	NULL);
62db8bf3	316
12c775db EV	317	/* Multi Core Timer */
	318	dev = qdev_create(NULL, "exynos4210.mct");
	319	qdev_init_nofail(dev);
1356b98d	320	busdev = SYS_BUS_DEVICE(dev);
12c775db EV	321	for (n = 0; n < 4; n++) {
	322	/* Connect global timer interrupts to Combiner gpio_in */
	323	sysbus_connect_irq(busdev, n,
	324	s->irq_table[exynos4210_get_irq(1, 4 + n)]);
	325	}
	326	/* Connect local timer interrupts to Combiner gpio_in */
	327	sysbus_connect_irq(busdev, 4,
	328	s->irq_table[exynos4210_get_irq(51, 0)]);
	329	sysbus_connect_irq(busdev, 5,
	330	s->irq_table[exynos4210_get_irq(35, 3)]);
	331	sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
	332
ffbbe7d0 MI	333	/* I2C */
	334	for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
	335	uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
	336	qemu_irq i2c_irq;
	337
	338	if (n < 8) {
	339	i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
	340	} else {
	341	i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
	342	}
	343
	344	dev = qdev_create(NULL, "exynos4210.i2c");
	345	qdev_init_nofail(dev);
1356b98d	346	busdev = SYS_BUS_DEVICE(dev);
ffbbe7d0 MI	347	sysbus_connect_irq(busdev, 0, i2c_irq);
ffbbe7d0 MI	348	sysbus_mmio_map(busdev, 0, addr);
a5c82852	349	s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
ffbbe7d0 MI	350	}
	351
	352
e5a4914e MK	353	/* UARTs */
e5a4914e MK	354	exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
5561adf0	355	EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0),
e5a4914e MK	356	s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
	357
	358	exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
5561adf0	359	EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1),
e5a4914e MK	360	s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
	361
	362	exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
5561adf0	363	EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2),
e5a4914e MK	364	s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
	365
	366	exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
5561adf0	367	EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3),
e5a4914e MK	368	s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
e5a4914e MK	369
d77b71c2 KK	370	/* SD/MMC host controllers */
	371	for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) {
	372	DeviceState *carddev;
	373	BlockBackend *blk;
	374	DriveInfo *di;
	375
2edb4434 PMD	376	/* Compatible with:
	377	* - SD Host Controller Specification Version 2.0
	378	* - SDIO Specification Version 2.0
	379	* - MMC Specification Version 4.3
	380	* - SDMA
	381	* - ADMA2
	382	*
	383	* As this part of the Exynos4210 is not publically available,
	384	* we used the "HS-MMC Controller S3C2416X RISC Microprocessor"
	385	* public datasheet which is very similar (implementing
	386	* MMC Specification Version 4.0 being the only difference noted)
	387	*/
c2de81e2	388	dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
3c675da5	389	qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
d77b71c2 KK	390	qdev_init_nofail(dev);
	391
	392	busdev = SYS_BUS_DEVICE(dev);
	393	sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n));
	394	sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]);
	395
	396	di = drive_get(IF_SD, 0, n);
	397	blk = di ? blk_by_legacy_dinfo(di) : NULL;
	398	carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
	399	qdev_prop_set_drive(carddev, "drive", blk, &error_abort);
	400	qdev_init_nofail(carddev);
	401	}
	402
30628cb1 MI	403	/* Display controller (FIMD) */
	404	sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
	405	s->irq_table[exynos4210_get_irq(11, 0)],
	406	s->irq_table[exynos4210_get_irq(11, 1)],
	407	s->irq_table[exynos4210_get_irq(11, 2)],
	408	NULL);
	409
358d615b LW	410	sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
	411	s->irq_table[exynos4210_get_irq(28, 3)]);
	412
0caa7113 EV	413	return s;
0caa7113 EV	414	}