[qemu.git] / hw / spapr_pci.c

/*
 * QEMU sPAPR PCI host originated from Uninorth PCI host
 *
 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
 * Copyright (C) 2011 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "pci.h"
#include "pci_host.h"
#include "hw/spapr.h"
#include "hw/spapr_pci.h"
#include "exec-memory.h"
#include <libfdt.h>

#include "hw/pci_internals.h"

static const uint32_t bars[] = {
    PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1,
    PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3,
    PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5
    /*, PCI_ROM_ADDRESS*/
};

static PCIDevice *find_dev(sPAPREnvironment *spapr,
                           uint64_t buid, uint32_t config_addr)
{
    DeviceState *qdev;
    int devfn = (config_addr >> 8) & 0xFF;
    sPAPRPHBState *phb;

    QLIST_FOREACH(phb, &spapr->phbs, list) {
        if (phb->buid != buid) {
            continue;
        }

        QTAILQ_FOREACH(qdev, &phb->host_state.bus->qbus.children, sibling) {
            PCIDevice *dev = (PCIDevice *)qdev;
            if (dev->devfn == devfn) {
                return dev;
            }
        }
    }

    return NULL;
}

static uint32_t rtas_pci_cfgaddr(uint32_t arg)
{
    return ((arg >> 20) & 0xf00) | (arg & 0xff);
}

static uint32_t rtas_read_pci_config_do(PCIDevice *pci_dev, uint32_t addr,
                                        uint32_t limit, uint32_t len)
{
    if ((addr + len) <= limit) {
        return pci_host_config_read_common(pci_dev, addr, limit, len);
    } else {
        return ~0x0;
    }
}

static void rtas_write_pci_config_do(PCIDevice *pci_dev, uint32_t addr,
                                     uint32_t limit, uint32_t val,
                                     uint32_t len)
{
    if ((addr + len) <= limit) {
        pci_host_config_write_common(pci_dev, addr, limit, val, len);
    }
}

static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
                                     uint32_t token, uint32_t nargs,
                                     target_ulong args,
                                     uint32_t nret, target_ulong rets)
{
    uint32_t val, size, addr;
    uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
    PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));

    if (!dev) {
        rtas_st(rets, 0, -1);
        return;
    }
    size = rtas_ld(args, 3);
    addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
    val = rtas_read_pci_config_do(dev, addr, pci_config_size(dev), size);
    rtas_st(rets, 0, 0);
    rtas_st(rets, 1, val);
}

static void rtas_read_pci_config(sPAPREnvironment *spapr,
                                 uint32_t token, uint32_t nargs,
                                 target_ulong args,
                                 uint32_t nret, target_ulong rets)
{
    uint32_t val, size, addr;
    PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));

    if (!dev) {
        rtas_st(rets, 0, -1);
        return;
    }
    size = rtas_ld(args, 1);
    addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
    val = rtas_read_pci_config_do(dev, addr, pci_config_size(dev), size);
    rtas_st(rets, 0, 0);
    rtas_st(rets, 1, val);
}

static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
                                      uint32_t token, uint32_t nargs,
                                      target_ulong args,
                                      uint32_t nret, target_ulong rets)
{
    uint32_t val, size, addr;
    uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
    PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));

    if (!dev) {
        rtas_st(rets, 0, -1);
        return;
    }
    val = rtas_ld(args, 4);
    size = rtas_ld(args, 3);
    addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
    rtas_write_pci_config_do(dev, addr, pci_config_size(dev), val, size);
    rtas_st(rets, 0, 0);
}

static void rtas_write_pci_config(sPAPREnvironment *spapr,
                                  uint32_t token, uint32_t nargs,
                                  target_ulong args,
                                  uint32_t nret, target_ulong rets)
{
    uint32_t val, size, addr;
    PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));

    if (!dev) {
        rtas_st(rets, 0, -1);
        return;
    }
    val = rtas_ld(args, 2);
    size = rtas_ld(args, 1);
    addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
    rtas_write_pci_config_do(dev, addr, pci_config_size(dev), val, size);
    rtas_st(rets, 0, 0);
}

static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
{
    /*
     * Here we need to convert pci_dev + irq_num to some unique value
     * which is less than number of IRQs on the specific bus (now it
     * is 16).  At the moment irq_num == device_id (number of the
     * slot?)
     * FIXME: we should swizzle in fn and irq_num
     */
    return (pci_dev->devfn >> 3) % SPAPR_PCI_NUM_LSI;
}

static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
{
    /*
     * Here we use the number returned by pci_spapr_map_irq to find a
     * corresponding qemu_irq.
     */
    sPAPRPHBState *phb = opaque;

    qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
}

static int spapr_phb_init(SysBusDevice *s)
{
    sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
    int i;

    /* Initialize the LSI table */
    for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) {
        qemu_irq qirq;
        uint32_t num;

        qirq = spapr_allocate_irq(0, &num);
        if (!qirq) {
            return -1;
        }

        phb->lsi_table[i].dt_irq = num;
        phb->lsi_table[i].qirq = qirq;
    }

    return 0;
}

static int spapr_main_pci_host_init(PCIDevice *d)
{
    return 0;
}

static void spapr_main_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = spapr_main_pci_host_init;
}

static TypeInfo spapr_main_pci_host_info = {
    .name          = "spapr-pci-host-bridge-pci",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init    = spapr_main_pci_host_class_init,
};

static void spapr_phb_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);

    sdc->init = spapr_phb_init;
}

static TypeInfo spapr_phb_info = {
    .name          = "spapr-pci-host-bridge",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(sPAPRPHBState),
    .class_init    = spapr_phb_class_init,
};

static void spapr_register_types(void)
{
    type_register_static(&spapr_phb_info);
    type_register_static(&spapr_main_pci_host_info);
}

type_init(spapr_register_types)

static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
                              unsigned size)
{
    switch (size) {
    case 1:
        return cpu_inb(addr);
    case 2:
        return cpu_inw(addr);
    case 4:
        return cpu_inl(addr);
    }
    assert(0);
}

static void spapr_io_write(void *opaque, target_phys_addr_t addr,
                           uint64_t data, unsigned size)
{
    switch (size) {
    case 1:
        cpu_outb(addr, data);
        return;
    case 2:
        cpu_outw(addr, data);
        return;
    case 4:
        cpu_outl(addr, data);
        return;
    }
    assert(0);
}

static MemoryRegionOps spapr_io_ops = {
    .endianness = DEVICE_LITTLE_ENDIAN,
    .read = spapr_io_read,
    .write = spapr_io_write
};

void spapr_create_phb(sPAPREnvironment *spapr,
                      const char *busname, uint64_t buid,
                      uint64_t mem_win_addr, uint64_t mem_win_size,
                      uint64_t io_win_addr)
{
    DeviceState *dev;
    SysBusDevice *s;
    sPAPRPHBState *phb;
    PCIBus *bus;
    char namebuf[strlen(busname)+11];

    dev = qdev_create(NULL, "spapr-pci-host-bridge");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    phb = FROM_SYSBUS(sPAPRPHBState, s);

    phb->mem_win_addr = mem_win_addr;

    sprintf(namebuf, "%s-mem", busname);
    memory_region_init(&phb->memspace, namebuf, INT64_MAX);

    sprintf(namebuf, "%s-memwindow", busname);
    memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
                             SPAPR_PCI_MEM_WIN_BUS_OFFSET, mem_win_size);
    memory_region_add_subregion(get_system_memory(), mem_win_addr,
                                &phb->memwindow);

    phb->io_win_addr = io_win_addr;

    /* On ppc, we only have MMIO no specific IO space from the CPU
     * perspective.  In theory we ought to be able to embed the PCI IO
     * memory region direction in the system memory space.  However,
     * if any of the IO BAR subregions use the old_portio mechanism,
     * that won't be processed properly unless accessed from the
     * system io address space.  This hack to bounce things via
     * system_io works around the problem until all the users of
     * old_portion are updated */
    sprintf(namebuf, "%s-io", busname);
    memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
    /* FIXME: fix to support multiple PHBs */
    memory_region_add_subregion(get_system_io(), 0, &phb->iospace);

    sprintf(namebuf, "%s-iowindow", busname);
    memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
                          namebuf, SPAPR_PCI_IO_WIN_SIZE);
    memory_region_add_subregion(get_system_memory(), io_win_addr,
                                &phb->iowindow);

    phb->host_state.bus = bus = pci_register_bus(&phb->busdev.qdev, busname,
                                                 pci_spapr_set_irq,
                                                 pci_spapr_map_irq,
                                                 phb,
                                                 &phb->memspace, &phb->iospace,
                                                 PCI_DEVFN(0, 0),
                                                 SPAPR_PCI_NUM_LSI);

    spapr_rtas_register("read-pci-config", rtas_read_pci_config);
    spapr_rtas_register("write-pci-config", rtas_write_pci_config);
    spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
    spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);

    QLIST_INSERT_HEAD(&spapr->phbs, phb, list);

    /* pci_bus_set_mem_base(bus, mem_va_start - SPAPR_PCI_MEM_BAR_START); */
}

/* Macros to operate with address in OF binding to PCI */
#define b_x(x, p, l)    (((x) & ((1<<(l))-1)) << (p))
#define b_n(x)          b_x((x), 31, 1) /* 0 if relocatable */
#define b_p(x)          b_x((x), 30, 1) /* 1 if prefetchable */
#define b_t(x)          b_x((x), 29, 1) /* 1 if the address is aliased */
#define b_ss(x)         b_x((x), 24, 2) /* the space code */
#define b_bbbbbbbb(x)   b_x((x), 16, 8) /* bus number */
#define b_ddddd(x)      b_x((x), 11, 5) /* device number */
#define b_fff(x)        b_x((x), 8, 3)  /* function number */
#define b_rrrrrrrr(x)   b_x((x), 0, 8)  /* register number */

int spapr_populate_pci_devices(sPAPRPHBState *phb,
                               uint32_t xics_phandle,
                               void *fdt)
{
    PCIBus *bus = phb->host_state.bus;
    int bus_off, i;
    char nodename[256];
    uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
    struct {
        uint32_t hi;
        uint64_t child;
        uint64_t parent;
        uint64_t size;
    } __attribute__((packed)) ranges[] = {
        {
            cpu_to_be32(b_ss(1)), cpu_to_be64(0),
            cpu_to_be64(phb->io_win_addr),
            cpu_to_be64(memory_region_size(&phb->iospace)),
        },
        {
            cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
            cpu_to_be64(phb->mem_win_addr),
            cpu_to_be64(memory_region_size(&phb->memwindow)),
        },
    };
    uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
    uint32_t interrupt_map_mask[] = {
        cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, 0x0};
    uint32_t interrupt_map[bus->nirq][7];

    /* Start populating the FDT */
    sprintf(nodename, "pci@%" PRIx64, phb->buid);
    bus_off = fdt_add_subnode(fdt, 0, nodename);
    if (bus_off < 0) {
        return bus_off;
    }

#define _FDT(exp) \
    do { \
        int ret = (exp);                                           \
        if (ret < 0) {                                             \
            return ret;                                            \
        }                                                          \
    } while (0)

    /* Write PHB properties */
    _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
    _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
    _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
    _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
    _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
    _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
    _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
    _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
    _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
    _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));

    /* Build the interrupt-map, this must matches what is done
     * in pci_spapr_map_irq
     */
    _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
                     &interrupt_map_mask, sizeof(interrupt_map_mask)));
    for (i = 0; i < 7; i++) {
        uint32_t *irqmap = interrupt_map[i];
        irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
        irqmap[1] = 0;
        irqmap[2] = 0;
        irqmap[3] = 0;
        irqmap[4] = cpu_to_be32(xics_phandle);
        irqmap[5] = cpu_to_be32(phb->lsi_table[i % SPAPR_PCI_NUM_LSI].dt_irq);
        irqmap[6] = cpu_to_be32(0x8);
    }
    /* Write interrupt map */
    _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
                     7 * sizeof(interrupt_map[0])));

    return 0;
}
Commit	Line	Data
3384f95c DG	1	/*
	2	* QEMU sPAPR PCI host originated from Uninorth PCI host
	3	*
	4	* Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
	5	* Copyright (C) 2011 David Gibson, IBM Corporation.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include "hw.h"
	26	#include "pci.h"
	27	#include "pci_host.h"
	28	#include "hw/spapr.h"
	29	#include "hw/spapr_pci.h"
	30	#include "exec-memory.h"
	31	#include <libfdt.h>
	32
	33	#include "hw/pci_internals.h"
	34
	35	static const uint32_t bars[] = {
	36	PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1,
	37	PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3,
	38	PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5
	39	/, PCI_ROM_ADDRESS/
	40	};
	41
	42	static PCIDevice find_dev(sPAPREnvironment spapr,
	43	uint64_t buid, uint32_t config_addr)
	44	{
	45	DeviceState *qdev;
	46	int devfn = (config_addr >> 8) & 0xFF;
	47	sPAPRPHBState *phb;
	48
	49	QLIST_FOREACH(phb, &spapr->phbs, list) {
	50	if (phb->buid != buid) {
	51	continue;
	52	}
	53
3a26360d	54	QTAILQ_FOREACH(qdev, &phb->host_state.bus->qbus.children, sibling) {
3384f95c DG	55	PCIDevice dev = (PCIDevice )qdev;
	56	if (dev->devfn == devfn) {
	57	return dev;
	58	}
	59	}
	60	}
	61
	62	return NULL;
	63	}
	64
3f7565c9 BH	65	static uint32_t rtas_pci_cfgaddr(uint32_t arg)
	66	{
	67	return ((arg >> 20) & 0xf00) \| (arg & 0xff);
	68	}
	69
88045ac5 AG	70	static uint32_t rtas_read_pci_config_do(PCIDevice *pci_dev, uint32_t addr,
	71	uint32_t limit, uint32_t len)
	72	{
	73	if ((addr + len) <= limit) {
	74	return pci_host_config_read_common(pci_dev, addr, limit, len);
	75	} else {
	76	return ~0x0;
	77	}
	78	}
	79
	80	static void rtas_write_pci_config_do(PCIDevice *pci_dev, uint32_t addr,
	81	uint32_t limit, uint32_t val,
	82	uint32_t len)
	83	{
	84	if ((addr + len) <= limit) {
	85	pci_host_config_write_common(pci_dev, addr, limit, val, len);
	86	}
	87	}
	88
3384f95c DG	89	static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
	90	uint32_t token, uint32_t nargs,
	91	target_ulong args,
	92	uint32_t nret, target_ulong rets)
	93	{
	94	uint32_t val, size, addr;
	95	uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) \| rtas_ld(args, 2);
	96	PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
	97
	98	if (!dev) {
	99	rtas_st(rets, 0, -1);
	100	return;
	101	}
	102	size = rtas_ld(args, 3);
3f7565c9	103	addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
88045ac5	104	val = rtas_read_pci_config_do(dev, addr, pci_config_size(dev), size);
3384f95c DG	105	rtas_st(rets, 0, 0);
	106	rtas_st(rets, 1, val);
	107	}
	108
	109	static void rtas_read_pci_config(sPAPREnvironment *spapr,
	110	uint32_t token, uint32_t nargs,
	111	target_ulong args,
	112	uint32_t nret, target_ulong rets)
	113	{
	114	uint32_t val, size, addr;
	115	PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));
	116
	117	if (!dev) {
	118	rtas_st(rets, 0, -1);
	119	return;
	120	}
	121	size = rtas_ld(args, 1);
3f7565c9	122	addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
88045ac5	123	val = rtas_read_pci_config_do(dev, addr, pci_config_size(dev), size);
3384f95c DG	124	rtas_st(rets, 0, 0);
	125	rtas_st(rets, 1, val);
	126	}
	127
	128	static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
	129	uint32_t token, uint32_t nargs,
	130	target_ulong args,
	131	uint32_t nret, target_ulong rets)
	132	{
	133	uint32_t val, size, addr;
	134	uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) \| rtas_ld(args, 2);
	135	PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
	136
	137	if (!dev) {
	138	rtas_st(rets, 0, -1);
	139	return;
	140	}
	141	val = rtas_ld(args, 4);
	142	size = rtas_ld(args, 3);
3f7565c9	143	addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
88045ac5	144	rtas_write_pci_config_do(dev, addr, pci_config_size(dev), val, size);
3384f95c DG	145	rtas_st(rets, 0, 0);
	146	}
	147
	148	static void rtas_write_pci_config(sPAPREnvironment *spapr,
	149	uint32_t token, uint32_t nargs,
	150	target_ulong args,
	151	uint32_t nret, target_ulong rets)
	152	{
	153	uint32_t val, size, addr;
	154	PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));
	155
	156	if (!dev) {
	157	rtas_st(rets, 0, -1);
	158	return;
	159	}
	160	val = rtas_ld(args, 2);
	161	size = rtas_ld(args, 1);
3f7565c9	162	addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
88045ac5	163	rtas_write_pci_config_do(dev, addr, pci_config_size(dev), val, size);
3384f95c DG	164	rtas_st(rets, 0, 0);
	165	}
	166
	167	static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
	168	{
	169	/*
	170	* Here we need to convert pci_dev + irq_num to some unique value
	171	* which is less than number of IRQs on the specific bus (now it
	172	* is 16). At the moment irq_num == device_id (number of the
	173	* slot?)
	174	* FIXME: we should swizzle in fn and irq_num
	175	*/
	176	return (pci_dev->devfn >> 3) % SPAPR_PCI_NUM_LSI;
	177	}
	178
	179	static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
	180	{
	181	/*
	182	* Here we use the number returned by pci_spapr_map_irq to find a
	183	* corresponding qemu_irq.
	184	*/
	185	sPAPRPHBState *phb = opaque;
	186
	187	qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
	188	}
	189
	190	static int spapr_phb_init(SysBusDevice *s)
	191	{
	192	sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
	193	int i;
	194
	195	/* Initialize the LSI table */
	196	for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) {
	197	qemu_irq qirq;
	198	uint32_t num;
	199
	200	qirq = spapr_allocate_irq(0, &num);
	201	if (!qirq) {
	202	return -1;
	203	}
	204
	205	phb->lsi_table[i].dt_irq = num;
	206	phb->lsi_table[i].qirq = qirq;
	207	}
	208
	209	return 0;
	210	}
	211
	212	static int spapr_main_pci_host_init(PCIDevice *d)
	213	{
	214	return 0;
	215	}
	216
40021f08 AL	217	static void spapr_main_pci_host_class_init(ObjectClass klass, void data)
	218	{
	219	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	220
	221	k->init = spapr_main_pci_host_init;
	222	}
	223
39bffca2 AL	224	static TypeInfo spapr_main_pci_host_info = {
	225	.name = "spapr-pci-host-bridge-pci",
	226	.parent = TYPE_PCI_DEVICE,
	227	.instance_size = sizeof(PCIDevice),
	228	.class_init = spapr_main_pci_host_class_init,
3384f95c DG	229	};
3384f95c DG	230
999e12bb AL	231	static void spapr_phb_class_init(ObjectClass klass, void data)
	232	{
	233	SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
	234
	235	sdc->init = spapr_phb_init;
	236	}
	237
39bffca2 AL	238	static TypeInfo spapr_phb_info = {
	239	.name = "spapr-pci-host-bridge",
	240	.parent = TYPE_SYS_BUS_DEVICE,
	241	.instance_size = sizeof(sPAPRPHBState),
	242	.class_init = spapr_phb_class_init,
999e12bb AL	243	};
999e12bb AL	244
83f7d43a	245	static void spapr_register_types(void)
3384f95c	246	{
39bffca2 AL	247	type_register_static(&spapr_phb_info);
39bffca2 AL	248	type_register_static(&spapr_main_pci_host_info);
3384f95c DG	249	}
3384f95c DG	250
83f7d43a	251	type_init(spapr_register_types)
3384f95c DG	252
	253	static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
	254	unsigned size)
	255	{
	256	switch (size) {
	257	case 1:
	258	return cpu_inb(addr);
	259	case 2:
	260	return cpu_inw(addr);
	261	case 4:
	262	return cpu_inl(addr);
	263	}
	264	assert(0);
	265	}
	266
	267	static void spapr_io_write(void *opaque, target_phys_addr_t addr,
	268	uint64_t data, unsigned size)
	269	{
	270	switch (size) {
	271	case 1:
	272	cpu_outb(addr, data);
	273	return;
	274	case 2:
	275	cpu_outw(addr, data);
	276	return;
	277	case 4:
	278	cpu_outl(addr, data);
	279	return;
	280	}
	281	assert(0);
	282	}
	283
	284	static MemoryRegionOps spapr_io_ops = {
	285	.endianness = DEVICE_LITTLE_ENDIAN,
	286	.read = spapr_io_read,
	287	.write = spapr_io_write
	288	};
	289
	290	void spapr_create_phb(sPAPREnvironment *spapr,
	291	const char *busname, uint64_t buid,
	292	uint64_t mem_win_addr, uint64_t mem_win_size,
	293	uint64_t io_win_addr)
	294	{
	295	DeviceState *dev;
	296	SysBusDevice *s;
	297	sPAPRPHBState *phb;
	298	PCIBus *bus;
	299	char namebuf[strlen(busname)+11];
	300
	301	dev = qdev_create(NULL, "spapr-pci-host-bridge");
	302	qdev_init_nofail(dev);
	303	s = sysbus_from_qdev(dev);
	304	phb = FROM_SYSBUS(sPAPRPHBState, s);
	305
	306	phb->mem_win_addr = mem_win_addr;
	307
	308	sprintf(namebuf, "%s-mem", busname);
	309	memory_region_init(&phb->memspace, namebuf, INT64_MAX);
	310
	311	sprintf(namebuf, "%s-memwindow", busname);
	312	memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
	313	SPAPR_PCI_MEM_WIN_BUS_OFFSET, mem_win_size);
	314	memory_region_add_subregion(get_system_memory(), mem_win_addr,
	315	&phb->memwindow);
316
317	phb->io_win_addr = io_win_addr;
318
319	/* On ppc, we only have MMIO no specific IO space from the CPU
320	* perspective. In theory we ought to be able to embed the PCI IO
321	* memory region direction in the system memory space. However,
322	* if any of the IO BAR subregions use the old_portio mechanism,
323	* that won't be processed properly unless accessed from the
324	* system io address space. This hack to bounce things via
325	* system_io works around the problem until all the users of
326	* old_portion are updated */
327	sprintf(namebuf, "%s-io", busname);
328	memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
329	/* FIXME: fix to support multiple PHBs */
330	memory_region_add_subregion(get_system_io(), 0, &phb->iospace);
331
332	sprintf(namebuf, "%s-iowindow", busname);
333	memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
334	namebuf, SPAPR_PCI_IO_WIN_SIZE);
335	memory_region_add_subregion(get_system_memory(), io_win_addr,
336	&phb->iowindow);
337
338	phb->host_state.bus = bus = pci_register_bus(&phb->busdev.qdev, busname,
339	pci_spapr_set_irq,
340	pci_spapr_map_irq,
341	phb,
342	&phb->memspace, &phb->iospace,
343	PCI_DEVFN(0, 0),
344	SPAPR_PCI_NUM_LSI);
345
346	spapr_rtas_register("read-pci-config", rtas_read_pci_config);
347	spapr_rtas_register("write-pci-config", rtas_write_pci_config);
348	spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
349	spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
350
351	QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
352
353	/* pci_bus_set_mem_base(bus, mem_va_start - SPAPR_PCI_MEM_BAR_START); */
354	}
355
356	/* Macros to operate with address in OF binding to PCI */
357	#define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
358	#define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
359	#define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
360	#define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
361	#define b_ss(x) b_x((x), 24, 2) /* the space code */
362	#define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
363	#define b_ddddd(x) b_x((x), 11, 5) /* device number */
364	#define b_fff(x) b_x((x), 8, 3) /* function number */
365	#define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
366
3384f95c DG	367	int spapr_populate_pci_devices(sPAPRPHBState *phb,
	368	uint32_t xics_phandle,
	369	void *fdt)
	370	{
	371	PCIBus *bus = phb->host_state.bus;
4d8d5467	372	int bus_off, i;
3384f95c	373	char nodename[256];
3384f95c DG	374	uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
	375	struct {
	376	uint32_t hi;
	377	uint64_t child;
	378	uint64_t parent;
	379	uint64_t size;
	380	} __attribute__((packed)) ranges[] = {
	381	{
	382	cpu_to_be32(b_ss(1)), cpu_to_be64(0),
	383	cpu_to_be64(phb->io_win_addr),
	384	cpu_to_be64(memory_region_size(&phb->iospace)),
	385	},
	386	{
	387	cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
	388	cpu_to_be64(phb->mem_win_addr),
	389	cpu_to_be64(memory_region_size(&phb->memwindow)),
	390	},
	391	};
	392	uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
	393	uint32_t interrupt_map_mask[] = {
4d8d5467	394	cpu_to_be32(b_ddddd(-1)\|b_fff(0)), 0x0, 0x0, 0x0};
3384f95c DG	395	uint32_t interrupt_map[bus->nirq][7];
	396
	397	/* Start populating the FDT */
	398	sprintf(nodename, "pci@%" PRIx64, phb->buid);
	399	bus_off = fdt_add_subnode(fdt, 0, nodename);
	400	if (bus_off < 0) {
	401	return bus_off;
	402	}
	403
	404	#define _FDT(exp) \
	405	do { \
	406	int ret = (exp); \
	407	if (ret < 0) { \
	408	return ret; \
	409	} \
	410	} while (0)
	411
	412	/* Write PHB properties */
	413	_FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
	414	_FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
	415	_FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
	416	_FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
	417	_FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
	418	_FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
	419	_FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
	420	_FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
	421	_FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
3f7565c9	422	_FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
3384f95c	423
4d8d5467 BH	424	/* Build the interrupt-map, this must matches what is done
	425	* in pci_spapr_map_irq
	426	*/
	427	_FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
	428	&interrupt_map_mask, sizeof(interrupt_map_mask)));
	429	for (i = 0; i < 7; i++) {
	430	uint32_t *irqmap = interrupt_map[i];
	431	irqmap[0] = cpu_to_be32(b_ddddd(i)\|b_fff(0));
3384f95c DG	432	irqmap[1] = 0;
	433	irqmap[2] = 0;
	434	irqmap[3] = 0;
	435	irqmap[4] = cpu_to_be32(xics_phandle);
4d8d5467	436	irqmap[5] = cpu_to_be32(phb->lsi_table[i % SPAPR_PCI_NUM_LSI].dt_irq);
3384f95c	437	irqmap[6] = cpu_to_be32(0x8);
3384f95c	438	}
3384f95c DG	439	/* Write interrupt map */
3384f95c DG	440	_FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
4d8d5467	441	7 * sizeof(interrupt_map[0])));
3384f95c DG	442
	443	return 0;
	444	}