[qemu.git] / include / hw / i386 / ich9.h

#ifndef HW_ICH9_H
#define HW_ICH9_H

#include "hw/hw.h"
#include "hw/isa/isa.h"
#include "hw/sysbus.h"
#include "hw/i386/pc.h"
#include "hw/isa/apm.h"
#include "hw/i386/ioapic.h"
#include "hw/pci/pci.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci/pci_bridge.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/ich9.h"
#include "hw/pci/pci_bus.h"

void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);

void ich9_generate_smi(void);
void ich9_generate_nmi(void);

#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */

#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
#define ICH9_LPC_DEVICE(obj) \
     OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)

typedef struct ICH9LPCState {
    /* ICH9 LPC PCI to ISA bridge */
    PCIDevice d;

    /* (pci device, intx) -> pirq
     * In real chipset case, the unused slots are never used
     * as ICH9 supports only D25-D31 irq routing.
     * On the other hand in qemu case, any slot/function can be populated
     * via command line option.
     * So fallback interrupt routing for any devices in any slots is necessary.
    */
    uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];

    APMState apm;
    ICH9LPCPMRegs pm;
    uint32_t sci_level; /* track sci level */
    uint8_t sci_gsi;

    /* 2.24 Pin Straps */
    struct {
        bool spkr_hi;
    } pin_strap;

    /* 10.1 Chipset Configuration registers(Memory Space)
     which is pointed by RCBA */
    uint8_t chip_config[ICH9_CC_SIZE];

    /*
     * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
     *
     * register contents and IO memory region
     */
    uint8_t rst_cnt;
    MemoryRegion rst_cnt_mem;

    /* isa bus */
    ISABus *isa_bus;
    MemoryRegion rcrb_mem; /* root complex register block */
    Notifier machine_ready;

    qemu_irq gsi[GSI_NUM_PINS];
} ICH9LPCState;

Object *ich9_lpc_find(void);

#define Q35_MASK(bit, ms_bit, ls_bit) \
((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))

/* ICH9: Chipset Configuration Registers */
#define ICH9_CC_ADDR_MASK                       (ICH9_CC_SIZE - 1)

#define ICH9_CC
#define ICH9_CC_D28IP                           0x310C
#define ICH9_CC_D28IP_SHIFT                     4
#define ICH9_CC_D28IP_MASK                      0xf
#define ICH9_CC_D28IP_DEFAULT                   0x00214321
#define ICH9_CC_D31IR                           0x3140
#define ICH9_CC_D30IR                           0x3142
#define ICH9_CC_D29IR                           0x3144
#define ICH9_CC_D28IR                           0x3146
#define ICH9_CC_D27IR                           0x3148
#define ICH9_CC_D26IR                           0x314C
#define ICH9_CC_D25IR                           0x3150
#define ICH9_CC_DIR_DEFAULT                     0x3210
#define ICH9_CC_D30IR_DEFAULT                   0x0
#define ICH9_CC_DIR_SHIFT                       4
#define ICH9_CC_DIR_MASK                        0x7
#define ICH9_CC_OIC                             0x31FF
#define ICH9_CC_OIC_AEN                         0x1
#define ICH9_CC_GCS                             0x3410
#define ICH9_CC_GCS_DEFAULT                     0x00000020
#define ICH9_CC_GCS_NO_REBOOT                   (1 << 5)

/* D28:F[0-5] */
#define ICH9_PCIE_DEV                           28
#define ICH9_PCIE_FUNC_MAX                      6


/* D29:F0 USB UHCI Controller #1 */
#define ICH9_USB_UHCI1_DEV                      29
#define ICH9_USB_UHCI1_FUNC                     0

/* D30:F0 DMI-to-PCI bridge */
#define ICH9_D2P_BRIDGE                         "ICH9 D2P BRIDGE"
#define ICH9_D2P_BRIDGE_SAVEVM_VERSION          0

#define ICH9_D2P_BRIDGE_DEV                     30
#define ICH9_D2P_BRIDGE_FUNC                    0

#define ICH9_D2P_SECONDARY_DEFAULT              (256 - 8)

#define ICH9_D2P_A2_REVISION                    0x92

/* D31:F0 LPC Processor Interface */
#define ICH9_RST_CNT_IOPORT                     0xCF9

/* D31:F1 LPC controller */
#define ICH9_A2_LPC                             "ICH9 A2 LPC"
#define ICH9_A2_LPC_SAVEVM_VERSION              0

#define ICH9_LPC_DEV                            31
#define ICH9_LPC_FUNC                           0

#define ICH9_A2_LPC_REVISION                    0x2
#define ICH9_LPC_NB_PIRQS                       8       /* PCI A-H */

#define ICH9_LPC_PMBASE                         0x40
#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK       Q35_MASK(32, 15, 7)
#define ICH9_LPC_PMBASE_RTE                     0x1
#define ICH9_LPC_PMBASE_DEFAULT                 0x1
#define ICH9_LPC_ACPI_CTRL                      0x44
#define ICH9_LPC_ACPI_CTRL_ACPI_EN              0x80
#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK     Q35_MASK(8, 2, 0)
#define ICH9_LPC_ACPI_CTRL_9                    0x0
#define ICH9_LPC_ACPI_CTRL_10                   0x1
#define ICH9_LPC_ACPI_CTRL_11                   0x2
#define ICH9_LPC_ACPI_CTRL_20                   0x4
#define ICH9_LPC_ACPI_CTRL_21                   0x5
#define ICH9_LPC_ACPI_CTRL_DEFAULT              0x0

#define ICH9_LPC_PIRQA_ROUT                     0x60
#define ICH9_LPC_PIRQB_ROUT                     0x61
#define ICH9_LPC_PIRQC_ROUT                     0x62
#define ICH9_LPC_PIRQD_ROUT                     0x63

#define ICH9_LPC_PIRQE_ROUT                     0x68
#define ICH9_LPC_PIRQF_ROUT                     0x69
#define ICH9_LPC_PIRQG_ROUT                     0x6a
#define ICH9_LPC_PIRQH_ROUT                     0x6b

#define ICH9_LPC_PIRQ_ROUT_IRQEN                0x80
#define ICH9_LPC_PIRQ_ROUT_MASK                 Q35_MASK(8, 3, 0)
#define ICH9_LPC_PIRQ_ROUT_DEFAULT              0x80

#define ICH9_LPC_GEN_PMCON_1                    0xa0
#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK           (1 << 4)
#define ICH9_LPC_GEN_PMCON_2                    0xa2
#define ICH9_LPC_GEN_PMCON_3                    0xa4
#define ICH9_LPC_GEN_PMCON_LOCK                 0xa6

#define ICH9_LPC_RCBA                           0xf0
#define ICH9_LPC_RCBA_BA_MASK                   Q35_MASK(32, 31, 14)
#define ICH9_LPC_RCBA_EN                        0x1
#define ICH9_LPC_RCBA_DEFAULT                   0x0

#define ICH9_LPC_PIC_NUM_PINS                   16
#define ICH9_LPC_IOAPIC_NUM_PINS                24

#define ICH9_GPIO_GSI "gsi"

/* D31:F2 SATA Controller #1 */
#define ICH9_SATA1_DEV                          31
#define ICH9_SATA1_FUNC                         2

/* D31:F0 power management I/O registers
   offset from the address ICH9_LPC_PMBASE */

/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
#define ICH9_PMIO_SIZE                          128
#define ICH9_PMIO_MASK                          (ICH9_PMIO_SIZE - 1)

#define ICH9_PMIO_PM1_STS                       0x00
#define ICH9_PMIO_PM1_EN                        0x02
#define ICH9_PMIO_PM1_CNT                       0x04
#define ICH9_PMIO_PM1_TMR                       0x08
#define ICH9_PMIO_GPE0_STS                      0x20
#define ICH9_PMIO_GPE0_EN                       0x28
#define ICH9_PMIO_GPE0_LEN                      16
#define ICH9_PMIO_SMI_EN                        0x30
#define ICH9_PMIO_SMI_EN_APMC_EN                (1 << 5)
#define ICH9_PMIO_SMI_EN_TCO_EN                 (1 << 13)
#define ICH9_PMIO_SMI_STS                       0x34
#define ICH9_PMIO_TCO_RLD                       0x60
#define ICH9_PMIO_TCO_LEN                       32

/* FADT ACPI_ENABLE/ACPI_DISABLE */
#define ICH9_APM_ACPI_ENABLE                    0x2
#define ICH9_APM_ACPI_DISABLE                   0x3


/* D31:F3 SMBus controller */
#define TYPE_ICH9_SMB_DEVICE "ICH9 SMB"

#define ICH9_A2_SMB_REVISION                    0x02
#define ICH9_SMB_PI                             0x00

#define ICH9_SMB_SMBMBAR0                       0x10
#define ICH9_SMB_SMBMBAR1                       0x14
#define ICH9_SMB_SMBM_BAR                       0
#define ICH9_SMB_SMBM_SIZE                      (1 << 8)
#define ICH9_SMB_SMB_BASE                       0x20
#define ICH9_SMB_SMB_BASE_BAR                   4
#define ICH9_SMB_SMB_BASE_SIZE                  (1 << 5)
#define ICH9_SMB_HOSTC                          0x40
#define ICH9_SMB_HOSTC_SSRESET                  ((uint8_t)(1 << 3))
#define ICH9_SMB_HOSTC_I2C_EN                   ((uint8_t)(1 << 2))
#define ICH9_SMB_HOSTC_SMB_SMI_EN               ((uint8_t)(1 << 1))
#define ICH9_SMB_HOSTC_HST_EN                   ((uint8_t)(1 << 0))

/* D31:F3 SMBus I/O and memory mapped I/O registers */
#define ICH9_SMB_DEV                            31
#define ICH9_SMB_FUNC                           3

#define ICH9_SMB_HST_STS                        0x00
#define ICH9_SMB_HST_CNT                        0x02
#define ICH9_SMB_HST_CMD                        0x03
#define ICH9_SMB_XMIT_SLVA                      0x04
#define ICH9_SMB_HST_D0                         0x05
#define ICH9_SMB_HST_D1                         0x06
#define ICH9_SMB_HOST_BLOCK_DB                  0x07

#endif /* HW_ICH9_H */
Commit	Line	Data
e516572f JB	1	#ifndef HW_ICH9_H
	2	#define HW_ICH9_H
	3
83c9f4ca	4	#include "hw/hw.h"
0d09e41a	5	#include "hw/isa/isa.h"
83c9f4ca	6	#include "hw/sysbus.h"
0d09e41a PB	7	#include "hw/i386/pc.h"
	8	#include "hw/isa/apm.h"
	9	#include "hw/i386/ioapic.h"
83c9f4ca PB	10	#include "hw/pci/pci.h"
	11	#include "hw/pci/pcie_host.h"
	12	#include "hw/pci/pci_bridge.h"
0d09e41a PB	13	#include "hw/acpi/acpi.h"
0d09e41a PB	14	#include "hw/acpi/ich9.h"
83c9f4ca	15	#include "hw/pci/pci_bus.h"
e516572f JB	16
	17	void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
	18	int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
91c3f2f0	19	PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
18d6abae	20	void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
a5c82852	21	I2CBus ich9_smb_init(PCIBus bus, int devfn, uint32_t smb_io_base);
e516572f	22
92055797 PA	23	void ich9_generate_smi(void);
	24	void ich9_generate_nmi(void);
	25
7335a95a	26	#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */
e516572f	27
292b1634	28	#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
e516572f JB	29	#define ICH9_LPC_DEVICE(obj) \
	30	OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)
	31
	32	typedef struct ICH9LPCState {
	33	/* ICH9 LPC PCI to ISA bridge */
	34	PCIDevice d;
	35
	36	/* (pci device, intx) -> pirq
	37	* In real chipset case, the unused slots are never used
0668a06b	38	* as ICH9 supports only D25-D31 irq routing.
e516572f JB	39	* On the other hand in qemu case, any slot/function can be populated
	40	* via command line option.
	41	* So fallback interrupt routing for any devices in any slots is necessary.
	42	*/
	43	uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
	44
	45	APMState apm;
	46	ICH9LPCPMRegs pm;
	47	uint32_t sci_level; /* track sci level */
8f242cb7	48	uint8_t sci_gsi;
e516572f	49
5add35be PA	50	/* 2.24 Pin Straps */
	51	struct {
	52	bool spkr_hi;
	53	} pin_strap;
	54
e516572f JB	55	/* 10.1 Chipset Configuration registers(Memory Space)
	56	which is pointed by RCBA */
	57	uint8_t chip_config[ICH9_CC_SIZE];
0e98b436 LE	58
	59	/*
	60	* 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
	61	*
	62	* register contents and IO memory region
	63	*/
	64	uint8_t rst_cnt;
	65	MemoryRegion rst_cnt_mem;
	66
e516572f JB	67	/* isa bus */
e516572f JB	68	ISABus *isa_bus;
7335a95a	69	MemoryRegion rcrb_mem; /* root complex register block */
3f5bc9e8	70	Notifier machine_ready;
e516572f	71
f999c0de	72	qemu_irq gsi[GSI_NUM_PINS];
e516572f JB	73	} ICH9LPCState;
e516572f JB	74
6f1426ab MT	75	Object *ich9_lpc_find(void);
6f1426ab MT	76
e516572f JB	77	#define Q35_MASK(bit, ms_bit, ls_bit) \
	78	((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
	79
	80	/* ICH9: Chipset Configuration Registers */
	81	#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
	82
	83	#define ICH9_CC
	84	#define ICH9_CC_D28IP 0x310C
	85	#define ICH9_CC_D28IP_SHIFT 4
	86	#define ICH9_CC_D28IP_MASK 0xf
	87	#define ICH9_CC_D28IP_DEFAULT 0x00214321
	88	#define ICH9_CC_D31IR 0x3140
	89	#define ICH9_CC_D30IR 0x3142
	90	#define ICH9_CC_D29IR 0x3144
	91	#define ICH9_CC_D28IR 0x3146
	92	#define ICH9_CC_D27IR 0x3148
	93	#define ICH9_CC_D26IR 0x314C
	94	#define ICH9_CC_D25IR 0x3150
	95	#define ICH9_CC_DIR_DEFAULT 0x3210
	96	#define ICH9_CC_D30IR_DEFAULT 0x0
	97	#define ICH9_CC_DIR_SHIFT 4
	98	#define ICH9_CC_DIR_MASK 0x7
	99	#define ICH9_CC_OIC 0x31FF
	100	#define ICH9_CC_OIC_AEN 0x1
92055797 PA	101	#define ICH9_CC_GCS 0x3410
	102	#define ICH9_CC_GCS_DEFAULT 0x00000020
	103	#define ICH9_CC_GCS_NO_REBOOT (1 << 5)
e516572f JB	104
	105	/* D28:F[0-5] */
	106	#define ICH9_PCIE_DEV 28
	107	#define ICH9_PCIE_FUNC_MAX 6
	108
	109
	110	/* D29:F0 USB UHCI Controller #1 */
	111	#define ICH9_USB_UHCI1_DEV 29
	112	#define ICH9_USB_UHCI1_FUNC 0
	113
263cf436	114	/* D30:F0 DMI-to-PCI bridge */
e516572f JB	115	#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
	116	#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
	117
	118	#define ICH9_D2P_BRIDGE_DEV 30
	119	#define ICH9_D2P_BRIDGE_FUNC 0
	120
	121	#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8)
	122
	123	#define ICH9_D2P_A2_REVISION 0x92
	124
0e98b436 LE	125	/* D31:F0 LPC Processor Interface */
0e98b436 LE	126	#define ICH9_RST_CNT_IOPORT 0xCF9
e516572f JB	127
	128	/* D31:F1 LPC controller */
	129	#define ICH9_A2_LPC "ICH9 A2 LPC"
	130	#define ICH9_A2_LPC_SAVEVM_VERSION 0
	131
	132	#define ICH9_LPC_DEV 31
	133	#define ICH9_LPC_FUNC 0
	134
	135	#define ICH9_A2_LPC_REVISION 0x2
	136	#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
	137
	138	#define ICH9_LPC_PMBASE 0x40
	139	#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
	140	#define ICH9_LPC_PMBASE_RTE 0x1
	141	#define ICH9_LPC_PMBASE_DEFAULT 0x1
	142	#define ICH9_LPC_ACPI_CTRL 0x44
	143	#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
	144	#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
	145	#define ICH9_LPC_ACPI_CTRL_9 0x0
	146	#define ICH9_LPC_ACPI_CTRL_10 0x1
	147	#define ICH9_LPC_ACPI_CTRL_11 0x2
	148	#define ICH9_LPC_ACPI_CTRL_20 0x4
	149	#define ICH9_LPC_ACPI_CTRL_21 0x5
	150	#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
	151
	152	#define ICH9_LPC_PIRQA_ROUT 0x60
	153	#define ICH9_LPC_PIRQB_ROUT 0x61
	154	#define ICH9_LPC_PIRQC_ROUT 0x62
	155	#define ICH9_LPC_PIRQD_ROUT 0x63
	156
	157	#define ICH9_LPC_PIRQE_ROUT 0x68
	158	#define ICH9_LPC_PIRQF_ROUT 0x69
	159	#define ICH9_LPC_PIRQG_ROUT 0x6a
	160	#define ICH9_LPC_PIRQH_ROUT 0x6b
	161
	162	#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
	163	#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
	164	#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
	165
11e66a15 GH	166	#define ICH9_LPC_GEN_PMCON_1 0xa0
	167	#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4)
	168	#define ICH9_LPC_GEN_PMCON_2 0xa2
	169	#define ICH9_LPC_GEN_PMCON_3 0xa4
	170	#define ICH9_LPC_GEN_PMCON_LOCK 0xa6
	171
e516572f JB	172	#define ICH9_LPC_RCBA 0xf0
	173	#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
	174	#define ICH9_LPC_RCBA_EN 0x1
	175	#define ICH9_LPC_RCBA_DEFAULT 0x0
	176
	177	#define ICH9_LPC_PIC_NUM_PINS 16
	178	#define ICH9_LPC_IOAPIC_NUM_PINS 24
	179
f999c0de EV	180	#define ICH9_GPIO_GSI "gsi"
f999c0de EV	181
e516572f JB	182	/* D31:F2 SATA Controller #1 */
	183	#define ICH9_SATA1_DEV 31
	184	#define ICH9_SATA1_FUNC 2
	185
0668a06b	186	/* D31:F0 power management I/O registers
e516572f JB	187	offset from the address ICH9_LPC_PMBASE */
	188
	189	/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
	190	#define ICH9_PMIO_SIZE 128
	191	#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
	192
	193	#define ICH9_PMIO_PM1_STS 0x00
	194	#define ICH9_PMIO_PM1_EN 0x02
	195	#define ICH9_PMIO_PM1_CNT 0x04
	196	#define ICH9_PMIO_PM1_TMR 0x08
	197	#define ICH9_PMIO_GPE0_STS 0x20
	198	#define ICH9_PMIO_GPE0_EN 0x28
	199	#define ICH9_PMIO_GPE0_LEN 16
	200	#define ICH9_PMIO_SMI_EN 0x30
	201	#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
92055797	202	#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13)
e516572f	203	#define ICH9_PMIO_SMI_STS 0x34
92055797 PA	204	#define ICH9_PMIO_TCO_RLD 0x60
92055797 PA	205	#define ICH9_PMIO_TCO_LEN 32
e516572f JB	206
	207	/* FADT ACPI_ENABLE/ACPI_DISABLE */
	208	#define ICH9_APM_ACPI_ENABLE 0x2
	209	#define ICH9_APM_ACPI_DISABLE 0x3
	210
	211
	212	/* D31:F3 SMBus controller */
f2dd8ebd EV	213	#define TYPE_ICH9_SMB_DEVICE "ICH9 SMB"
f2dd8ebd EV	214
e516572f JB	215	#define ICH9_A2_SMB_REVISION 0x02
	216	#define ICH9_SMB_PI 0x00
	217
	218	#define ICH9_SMB_SMBMBAR0 0x10
	219	#define ICH9_SMB_SMBMBAR1 0x14
	220	#define ICH9_SMB_SMBM_BAR 0
	221	#define ICH9_SMB_SMBM_SIZE (1 << 8)
	222	#define ICH9_SMB_SMB_BASE 0x20
	223	#define ICH9_SMB_SMB_BASE_BAR 4
	224	#define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
	225	#define ICH9_SMB_HOSTC 0x40
	226	#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
	227	#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
	228	#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
	229	#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
	230
	231	/* D31:F3 SMBus I/O and memory mapped I/O registers */
	232	#define ICH9_SMB_DEV 31
	233	#define ICH9_SMB_FUNC 3
	234
	235	#define ICH9_SMB_HST_STS 0x00
	236	#define ICH9_SMB_HST_CNT 0x02
	237	#define ICH9_SMB_HST_CMD 0x03
	238	#define ICH9_SMB_XMIT_SLVA 0x04
	239	#define ICH9_SMB_HST_D0 0x05
	240	#define ICH9_SMB_HST_D1 0x06
	241	#define ICH9_SMB_HOST_BLOCK_DB 0x07
	242
	243	#endif /* HW_ICH9_H */