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Commit | Line | Data |
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4c9649a9 | 1 | /* |
c3082755 | 2 | * Helpers for loads and stores |
5fafdf24 | 3 | * |
4c9649a9 JM |
4 | * Copyright (c) 2007 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
4c9649a9 JM |
18 | */ |
19 | ||
3e457172 | 20 | #include "cpu.h" |
a7812ae4 | 21 | #include "helper.h" |
4c9649a9 | 22 | |
4c9649a9 | 23 | |
4c9649a9 | 24 | /* Softmmu support */ |
c3082755 RH |
25 | #ifndef CONFIG_USER_ONLY |
26 | ||
fdfba1a2 | 27 | uint64_t helper_ldl_phys(CPUAlphaState *env, uint64_t p) |
8bb6e981 | 28 | { |
d2810ffd | 29 | CPUState *cs = CPU(alpha_env_get_cpu(env)); |
fdfba1a2 | 30 | return (int32_t)ldl_phys(cs->as, p); |
8bb6e981 AJ |
31 | } |
32 | ||
2c17449b | 33 | uint64_t helper_ldq_phys(CPUAlphaState *env, uint64_t p) |
8bb6e981 | 34 | { |
d2810ffd | 35 | CPUState *cs = CPU(alpha_env_get_cpu(env)); |
2c17449b | 36 | return ldq_phys(cs->as, p); |
8bb6e981 AJ |
37 | } |
38 | ||
c3082755 | 39 | uint64_t helper_ldl_l_phys(CPUAlphaState *env, uint64_t p) |
8bb6e981 | 40 | { |
d2810ffd | 41 | CPUState *cs = CPU(alpha_env_get_cpu(env)); |
2374e73e | 42 | env->lock_addr = p; |
fdfba1a2 | 43 | return env->lock_value = (int32_t)ldl_phys(cs->as, p); |
8bb6e981 AJ |
44 | } |
45 | ||
c3082755 | 46 | uint64_t helper_ldq_l_phys(CPUAlphaState *env, uint64_t p) |
8bb6e981 | 47 | { |
d2810ffd | 48 | CPUState *cs = CPU(alpha_env_get_cpu(env)); |
2374e73e | 49 | env->lock_addr = p; |
2c17449b | 50 | return env->lock_value = ldq_phys(cs->as, p); |
8bb6e981 AJ |
51 | } |
52 | ||
ab1da857 | 53 | void helper_stl_phys(CPUAlphaState *env, uint64_t p, uint64_t v) |
8bb6e981 | 54 | { |
d2810ffd | 55 | CPUState *cs = CPU(alpha_env_get_cpu(env)); |
ab1da857 | 56 | stl_phys(cs->as, p, v); |
8bb6e981 AJ |
57 | } |
58 | ||
f606604f | 59 | void helper_stq_phys(CPUAlphaState *env, uint64_t p, uint64_t v) |
8bb6e981 | 60 | { |
d2810ffd | 61 | CPUState *cs = CPU(alpha_env_get_cpu(env)); |
f606604f | 62 | stq_phys(cs->as, p, v); |
8bb6e981 AJ |
63 | } |
64 | ||
c3082755 | 65 | uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v) |
8bb6e981 | 66 | { |
d2810ffd | 67 | CPUState *cs = CPU(alpha_env_get_cpu(env)); |
2374e73e | 68 | uint64_t ret = 0; |
8bb6e981 | 69 | |
2374e73e | 70 | if (p == env->lock_addr) { |
fdfba1a2 | 71 | int32_t old = ldl_phys(cs->as, p); |
2374e73e | 72 | if (old == (int32_t)env->lock_value) { |
ab1da857 | 73 | stl_phys(cs->as, p, v); |
2374e73e RH |
74 | ret = 1; |
75 | } | |
76 | } | |
77 | env->lock_addr = -1; | |
8bb6e981 AJ |
78 | |
79 | return ret; | |
80 | } | |
81 | ||
c3082755 | 82 | uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v) |
8bb6e981 | 83 | { |
d2810ffd | 84 | CPUState *cs = CPU(alpha_env_get_cpu(env)); |
2374e73e | 85 | uint64_t ret = 0; |
8bb6e981 | 86 | |
2374e73e | 87 | if (p == env->lock_addr) { |
2c17449b | 88 | uint64_t old = ldq_phys(cs->as, p); |
2374e73e | 89 | if (old == env->lock_value) { |
f606604f | 90 | stq_phys(cs->as, p, v); |
2374e73e RH |
91 | ret = 1; |
92 | } | |
93 | } | |
94 | env->lock_addr = -1; | |
8bb6e981 AJ |
95 | |
96 | return ret; | |
4c9649a9 JM |
97 | } |
98 | ||
c3082755 | 99 | static void do_unaligned_access(CPUAlphaState *env, target_ulong addr, |
20503968 | 100 | int is_write, int is_user, uintptr_t retaddr) |
5b450407 | 101 | { |
27103424 AF |
102 | AlphaCPU *cpu = alpha_env_get_cpu(env); |
103 | CPUState *cs = CPU(cpu); | |
5b450407 RH |
104 | uint64_t pc; |
105 | uint32_t insn; | |
106 | ||
a8a826a3 | 107 | if (retaddr) { |
3f38f309 | 108 | cpu_restore_state(cs, retaddr); |
a8a826a3 | 109 | } |
5b450407 RH |
110 | |
111 | pc = env->pc; | |
c3082755 | 112 | insn = cpu_ldl_code(env, pc); |
5b450407 RH |
113 | |
114 | env->trap_arg0 = addr; | |
115 | env->trap_arg1 = insn >> 26; /* opcode */ | |
116 | env->trap_arg2 = (insn >> 21) & 31; /* dest regno */ | |
27103424 | 117 | cs->exception_index = EXCP_UNALIGN; |
b9f0923e | 118 | env->error_code = 0; |
5638d180 | 119 | cpu_loop_exit(cs); |
5b450407 RH |
120 | } |
121 | ||
c658b94f AF |
122 | void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr, |
123 | bool is_write, bool is_exec, int unused, | |
124 | unsigned size) | |
5b450407 | 125 | { |
c658b94f AF |
126 | AlphaCPU *cpu = ALPHA_CPU(cs); |
127 | CPUAlphaState *env = &cpu->env; | |
128 | ||
5b450407 | 129 | env->trap_arg0 = addr; |
c658b94f | 130 | env->trap_arg1 = is_write ? 1 : 0; |
20503968 | 131 | dynamic_excp(env, 0, EXCP_MCHK, 0); |
5b450407 RH |
132 | } |
133 | ||
022c62cb | 134 | #include "exec/softmmu_exec.h" |
3e457172 | 135 | |
4c9649a9 | 136 | #define MMUSUFFIX _mmu |
5b450407 | 137 | #define ALIGNED_ONLY |
4c9649a9 JM |
138 | |
139 | #define SHIFT 0 | |
022c62cb | 140 | #include "exec/softmmu_template.h" |
4c9649a9 JM |
141 | |
142 | #define SHIFT 1 | |
022c62cb | 143 | #include "exec/softmmu_template.h" |
4c9649a9 JM |
144 | |
145 | #define SHIFT 2 | |
022c62cb | 146 | #include "exec/softmmu_template.h" |
4c9649a9 JM |
147 | |
148 | #define SHIFT 3 | |
022c62cb | 149 | #include "exec/softmmu_template.h" |
4c9649a9 JM |
150 | |
151 | /* try to fill the TLB and return an exception if error. If retaddr is | |
152 | NULL, it means that the function was called in C code (i.e. not | |
153 | from generated code or from helper.c) */ | |
154 | /* XXX: fix it to restore all registers */ | |
d5a11fef | 155 | void tlb_fill(CPUState *cs, target_ulong addr, int is_write, |
20503968 | 156 | int mmu_idx, uintptr_t retaddr) |
4c9649a9 | 157 | { |
4c9649a9 JM |
158 | int ret; |
159 | ||
d5a11fef | 160 | ret = alpha_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); |
2d9671d3 | 161 | if (unlikely(ret != 0)) { |
a8a826a3 | 162 | if (retaddr) { |
3f38f309 | 163 | cpu_restore_state(cs, retaddr); |
a8a826a3 | 164 | } |
4c9649a9 | 165 | /* Exception index and error code are already set */ |
5638d180 | 166 | cpu_loop_exit(cs); |
4c9649a9 | 167 | } |
4c9649a9 | 168 | } |
c3082755 | 169 | #endif /* CONFIG_USER_ONLY */ |