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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU 8253/8254 interval timer emulation | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
b6a0aa05 | 24 | #include "qemu/osdep.h" |
83c9f4ca | 25 | #include "hw/hw.h" |
0d09e41a PB |
26 | #include "hw/i386/pc.h" |
27 | #include "hw/isa/isa.h" | |
1de7afc9 | 28 | #include "qemu/timer.h" |
0d09e41a PB |
29 | #include "hw/timer/i8254.h" |
30 | #include "hw/timer/i8254_internal.h" | |
80cabfad | 31 | |
b0a21b53 FB |
32 | //#define DEBUG_PIT |
33 | ||
ec844b96 FB |
34 | #define RW_STATE_LSB 1 |
35 | #define RW_STATE_MSB 2 | |
36 | #define RW_STATE_WORD0 3 | |
37 | #define RW_STATE_WORD1 4 | |
80cabfad | 38 | |
a15d0912 AF |
39 | #define PIT_CLASS(class) OBJECT_CLASS_CHECK(PITClass, (class), TYPE_I8254) |
40 | #define PIT_GET_CLASS(obj) OBJECT_GET_CLASS(PITClass, (obj), TYPE_I8254) | |
41 | ||
42 | typedef struct PITClass { | |
43 | PITCommonClass parent_class; | |
44 | ||
45 | DeviceRealize parent_realize; | |
46 | } PITClass; | |
47 | ||
b0a21b53 FB |
48 | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time); |
49 | ||
80cabfad FB |
50 | static int pit_get_count(PITChannelState *s) |
51 | { | |
52 | uint64_t d; | |
53 | int counter; | |
54 | ||
bc72ad67 | 55 | d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->count_load_time, PIT_FREQ, |
73bcb24d | 56 | NANOSECONDS_PER_SECOND); |
80cabfad FB |
57 | switch(s->mode) { |
58 | case 0: | |
59 | case 1: | |
60 | case 4: | |
61 | case 5: | |
62 | counter = (s->count - d) & 0xffff; | |
63 | break; | |
64 | case 3: | |
65 | /* XXX: may be incorrect for odd counts */ | |
66 | counter = s->count - ((2 * d) % s->count); | |
67 | break; | |
68 | default: | |
69 | counter = s->count - (d % s->count); | |
70 | break; | |
71 | } | |
72 | return counter; | |
73 | } | |
74 | ||
80cabfad | 75 | /* val must be 0 or 1 */ |
d11e859e JK |
76 | static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc, |
77 | int val) | |
80cabfad | 78 | { |
d11e859e | 79 | switch (sc->mode) { |
80cabfad FB |
80 | default: |
81 | case 0: | |
82 | case 4: | |
83 | /* XXX: just disable/enable counting */ | |
84 | break; | |
85 | case 1: | |
86 | case 5: | |
d11e859e | 87 | if (sc->gate < val) { |
80cabfad | 88 | /* restart counting on rising edge */ |
bc72ad67 | 89 | sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
d11e859e | 90 | pit_irq_timer_update(sc, sc->count_load_time); |
80cabfad FB |
91 | } |
92 | break; | |
93 | case 2: | |
94 | case 3: | |
d11e859e | 95 | if (sc->gate < val) { |
80cabfad | 96 | /* restart counting on rising edge */ |
bc72ad67 | 97 | sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
d11e859e | 98 | pit_irq_timer_update(sc, sc->count_load_time); |
80cabfad FB |
99 | } |
100 | /* XXX: disable/enable counting */ | |
101 | break; | |
102 | } | |
d11e859e | 103 | sc->gate = val; |
fd06c375 FB |
104 | } |
105 | ||
80cabfad FB |
106 | static inline void pit_load_count(PITChannelState *s, int val) |
107 | { | |
108 | if (val == 0) | |
109 | val = 0x10000; | |
bc72ad67 | 110 | s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
80cabfad | 111 | s->count = val; |
b0a21b53 | 112 | pit_irq_timer_update(s, s->count_load_time); |
80cabfad FB |
113 | } |
114 | ||
ec844b96 FB |
115 | /* if already latched, do not latch again */ |
116 | static void pit_latch_count(PITChannelState *s) | |
117 | { | |
118 | if (!s->count_latched) { | |
119 | s->latched_count = pit_get_count(s); | |
120 | s->count_latched = s->rw_mode; | |
121 | } | |
122 | } | |
123 | ||
0505bcde AG |
124 | static void pit_ioport_write(void *opaque, hwaddr addr, |
125 | uint64_t val, unsigned size) | |
80cabfad | 126 | { |
d11e859e | 127 | PITCommonState *pit = opaque; |
80cabfad FB |
128 | int channel, access; |
129 | PITChannelState *s; | |
130 | ||
131 | addr &= 3; | |
132 | if (addr == 3) { | |
133 | channel = val >> 6; | |
ec844b96 FB |
134 | if (channel == 3) { |
135 | /* read back command */ | |
136 | for(channel = 0; channel < 3; channel++) { | |
137 | s = &pit->channels[channel]; | |
138 | if (val & (2 << channel)) { | |
139 | if (!(val & 0x20)) { | |
140 | pit_latch_count(s); | |
141 | } | |
142 | if (!(val & 0x10) && !s->status_latched) { | |
143 | /* status latch */ | |
144 | /* XXX: add BCD and null count */ | |
4aa5d285 JK |
145 | s->status = |
146 | (pit_get_out(s, | |
bc72ad67 | 147 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) << 7) | |
ec844b96 FB |
148 | (s->rw_mode << 4) | |
149 | (s->mode << 1) | | |
150 | s->bcd; | |
151 | s->status_latched = 1; | |
152 | } | |
153 | } | |
154 | } | |
155 | } else { | |
156 | s = &pit->channels[channel]; | |
157 | access = (val >> 4) & 3; | |
158 | if (access == 0) { | |
159 | pit_latch_count(s); | |
160 | } else { | |
161 | s->rw_mode = access; | |
162 | s->read_state = access; | |
163 | s->write_state = access; | |
164 | ||
165 | s->mode = (val >> 1) & 7; | |
166 | s->bcd = val & 1; | |
167 | /* XXX: update irq timer ? */ | |
168 | } | |
80cabfad FB |
169 | } |
170 | } else { | |
ec844b96 FB |
171 | s = &pit->channels[addr]; |
172 | switch(s->write_state) { | |
173 | default: | |
80cabfad FB |
174 | case RW_STATE_LSB: |
175 | pit_load_count(s, val); | |
176 | break; | |
177 | case RW_STATE_MSB: | |
178 | pit_load_count(s, val << 8); | |
179 | break; | |
180 | case RW_STATE_WORD0: | |
ec844b96 FB |
181 | s->write_latch = val; |
182 | s->write_state = RW_STATE_WORD1; | |
183 | break; | |
80cabfad | 184 | case RW_STATE_WORD1: |
ec844b96 FB |
185 | pit_load_count(s, s->write_latch | (val << 8)); |
186 | s->write_state = RW_STATE_WORD0; | |
80cabfad FB |
187 | break; |
188 | } | |
189 | } | |
190 | } | |
191 | ||
0505bcde AG |
192 | static uint64_t pit_ioport_read(void *opaque, hwaddr addr, |
193 | unsigned size) | |
80cabfad | 194 | { |
d11e859e | 195 | PITCommonState *pit = opaque; |
80cabfad FB |
196 | int ret, count; |
197 | PITChannelState *s; | |
3b46e624 | 198 | |
80cabfad | 199 | addr &= 3; |
d4862a87 PM |
200 | |
201 | if (addr == 3) { | |
202 | /* Mode/Command register is write only, read is ignored */ | |
203 | return 0; | |
204 | } | |
205 | ||
ec844b96 FB |
206 | s = &pit->channels[addr]; |
207 | if (s->status_latched) { | |
208 | s->status_latched = 0; | |
209 | ret = s->status; | |
210 | } else if (s->count_latched) { | |
211 | switch(s->count_latched) { | |
212 | default: | |
213 | case RW_STATE_LSB: | |
214 | ret = s->latched_count & 0xff; | |
215 | s->count_latched = 0; | |
216 | break; | |
217 | case RW_STATE_MSB: | |
80cabfad | 218 | ret = s->latched_count >> 8; |
ec844b96 FB |
219 | s->count_latched = 0; |
220 | break; | |
221 | case RW_STATE_WORD0: | |
80cabfad | 222 | ret = s->latched_count & 0xff; |
ec844b96 FB |
223 | s->count_latched = RW_STATE_MSB; |
224 | break; | |
225 | } | |
226 | } else { | |
227 | switch(s->read_state) { | |
228 | default: | |
229 | case RW_STATE_LSB: | |
230 | count = pit_get_count(s); | |
231 | ret = count & 0xff; | |
232 | break; | |
233 | case RW_STATE_MSB: | |
234 | count = pit_get_count(s); | |
235 | ret = (count >> 8) & 0xff; | |
236 | break; | |
237 | case RW_STATE_WORD0: | |
238 | count = pit_get_count(s); | |
239 | ret = count & 0xff; | |
240 | s->read_state = RW_STATE_WORD1; | |
241 | break; | |
242 | case RW_STATE_WORD1: | |
243 | count = pit_get_count(s); | |
244 | ret = (count >> 8) & 0xff; | |
245 | s->read_state = RW_STATE_WORD0; | |
246 | break; | |
247 | } | |
80cabfad FB |
248 | } |
249 | return ret; | |
250 | } | |
251 | ||
b0a21b53 FB |
252 | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time) |
253 | { | |
254 | int64_t expire_time; | |
255 | int irq_level; | |
256 | ||
ce967e2f | 257 | if (!s->irq_timer || s->irq_disabled) { |
b0a21b53 | 258 | return; |
ce967e2f | 259 | } |
b0a21b53 | 260 | expire_time = pit_get_next_transition_time(s, current_time); |
4aa5d285 | 261 | irq_level = pit_get_out(s, current_time); |
d537cf6c | 262 | qemu_set_irq(s->irq, irq_level); |
b0a21b53 FB |
263 | #ifdef DEBUG_PIT |
264 | printf("irq_level=%d next_delay=%f\n", | |
5fafdf24 | 265 | irq_level, |
73bcb24d | 266 | (double)(expire_time - current_time) / NANOSECONDS_PER_SECOND); |
b0a21b53 FB |
267 | #endif |
268 | s->next_transition_time = expire_time; | |
269 | if (expire_time != -1) | |
bc72ad67 | 270 | timer_mod(s->irq_timer, expire_time); |
b0a21b53 | 271 | else |
bc72ad67 | 272 | timer_del(s->irq_timer); |
b0a21b53 FB |
273 | } |
274 | ||
275 | static void pit_irq_timer(void *opaque) | |
276 | { | |
277 | PITChannelState *s = opaque; | |
278 | ||
279 | pit_irq_timer_update(s, s->next_transition_time); | |
280 | } | |
281 | ||
d11e859e | 282 | static void pit_reset(DeviceState *dev) |
b0a21b53 | 283 | { |
3afe7e14 | 284 | PITCommonState *pit = PIT_COMMON(dev); |
b0a21b53 | 285 | PITChannelState *s; |
b0a21b53 | 286 | |
d11e859e | 287 | pit_reset_common(pit); |
5122b431 | 288 | |
d11e859e JK |
289 | s = &pit->channels[0]; |
290 | if (!s->irq_disabled) { | |
bc72ad67 | 291 | timer_mod(s->irq_timer, s->next_transition_time); |
80cabfad | 292 | } |
d7d02e3c FB |
293 | } |
294 | ||
ce967e2f JK |
295 | /* When HPET is operating in legacy mode, suppress the ignored timer IRQ, |
296 | * reenable it when legacy mode is left again. */ | |
297 | static void pit_irq_control(void *opaque, int n, int enable) | |
16b29ae1 | 298 | { |
d11e859e | 299 | PITCommonState *pit = opaque; |
ce967e2f JK |
300 | PITChannelState *s = &pit->channels[0]; |
301 | ||
302 | if (enable) { | |
303 | s->irq_disabled = 0; | |
bc72ad67 | 304 | pit_irq_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
ce967e2f JK |
305 | } else { |
306 | s->irq_disabled = 1; | |
bc72ad67 | 307 | timer_del(s->irq_timer); |
ce967e2f | 308 | } |
16b29ae1 AL |
309 | } |
310 | ||
60ea6aa8 | 311 | static const MemoryRegionOps pit_ioport_ops = { |
0505bcde AG |
312 | .read = pit_ioport_read, |
313 | .write = pit_ioport_write, | |
314 | .impl = { | |
315 | .min_access_size = 1, | |
316 | .max_access_size = 1, | |
317 | }, | |
318 | .endianness = DEVICE_LITTLE_ENDIAN, | |
60ea6aa8 RH |
319 | }; |
320 | ||
3fbc1c0c JK |
321 | static void pit_post_load(PITCommonState *s) |
322 | { | |
323 | PITChannelState *sc = &s->channels[0]; | |
324 | ||
325 | if (sc->next_transition_time != -1) { | |
bc72ad67 | 326 | timer_mod(sc->irq_timer, sc->next_transition_time); |
3fbc1c0c | 327 | } else { |
bc72ad67 | 328 | timer_del(sc->irq_timer); |
3fbc1c0c JK |
329 | } |
330 | } | |
331 | ||
a7737e44 | 332 | static void pit_realizefn(DeviceState *dev, Error **errp) |
d7d02e3c | 333 | { |
a15d0912 AF |
334 | PITCommonState *pit = PIT_COMMON(dev); |
335 | PITClass *pc = PIT_GET_CLASS(dev); | |
d7d02e3c FB |
336 | PITChannelState *s; |
337 | ||
338 | s = &pit->channels[0]; | |
339 | /* the timer 0 is connected to an IRQ */ | |
bc72ad67 | 340 | s->irq_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pit_irq_timer, s); |
a15d0912 | 341 | qdev_init_gpio_out(dev, &s->irq, 1); |
80cabfad | 342 | |
853dca12 PB |
343 | memory_region_init_io(&pit->ioports, OBJECT(pit), &pit_ioport_ops, |
344 | pit, "pit", 4); | |
ce967e2f | 345 | |
a15d0912 | 346 | qdev_init_gpio_in(dev, pit_irq_control, 1); |
ca22a3a3 | 347 | |
a7737e44 | 348 | pc->parent_realize(dev, errp); |
64d7e9a4 BS |
349 | } |
350 | ||
39bffca2 | 351 | static Property pit_properties[] = { |
c7bcc85d | 352 | DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1), |
39bffca2 AL |
353 | DEFINE_PROP_END_OF_LIST(), |
354 | }; | |
355 | ||
8f04ee08 AL |
356 | static void pit_class_initfn(ObjectClass *klass, void *data) |
357 | { | |
a15d0912 | 358 | PITClass *pc = PIT_CLASS(klass); |
d11e859e | 359 | PITCommonClass *k = PIT_COMMON_CLASS(klass); |
39bffca2 | 360 | DeviceClass *dc = DEVICE_CLASS(klass); |
d11e859e | 361 | |
a15d0912 AF |
362 | pc->parent_realize = dc->realize; |
363 | dc->realize = pit_realizefn; | |
d11e859e JK |
364 | k->set_channel_gate = pit_set_channel_gate; |
365 | k->get_channel_info = pit_get_channel_info_common; | |
3fbc1c0c | 366 | k->post_load = pit_post_load; |
39bffca2 | 367 | dc->reset = pit_reset; |
39bffca2 | 368 | dc->props = pit_properties; |
8f04ee08 AL |
369 | } |
370 | ||
8c43a6f0 | 371 | static const TypeInfo pit_info = { |
3afe7e14 | 372 | .name = TYPE_I8254, |
d11e859e JK |
373 | .parent = TYPE_PIT_COMMON, |
374 | .instance_size = sizeof(PITCommonState), | |
39bffca2 | 375 | .class_init = pit_class_initfn, |
a15d0912 | 376 | .class_size = sizeof(PITClass), |
64d7e9a4 BS |
377 | }; |
378 | ||
83f7d43a | 379 | static void pit_register_types(void) |
64d7e9a4 | 380 | { |
39bffca2 | 381 | type_register_static(&pit_info); |
80cabfad | 382 | } |
83f7d43a AF |
383 | |
384 | type_init(pit_register_types) |