[qemu.git] / linux-user / vm86.c

/*
 *  vm86 linux syscall support
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
 */
#include "qemu/osdep.h"

#include "qemu.h"

//#define DEBUG_VM86

#ifdef DEBUG_VM86
#  define LOG_VM86(...) qemu_log(__VA_ARGS__);
#else
#  define LOG_VM86(...) do { } while (0)
#endif


#define set_flags(X,new,mask) \
((X) = ((X) & ~(mask)) | ((new) & (mask)))

#define SAFE_MASK	(0xDD5)
#define RETURN_MASK	(0xDFF)

static inline int is_revectored(int nr, struct target_revectored_struct *bitmap)
{
    return (((uint8_t *)bitmap)[nr >> 3] >> (nr & 7)) & 1;
}

static inline void vm_putw(CPUX86State *env, uint32_t segptr,
                           unsigned int reg16, unsigned int val)
{
    cpu_stw_data(env, segptr + (reg16 & 0xffff), val);
}

static inline void vm_putl(CPUX86State *env, uint32_t segptr,
                           unsigned int reg16, unsigned int val)
{
    cpu_stl_data(env, segptr + (reg16 & 0xffff), val);
}

static inline unsigned int vm_getb(CPUX86State *env,
                                   uint32_t segptr, unsigned int reg16)
{
    return cpu_ldub_data(env, segptr + (reg16 & 0xffff));
}

static inline unsigned int vm_getw(CPUX86State *env,
                                   uint32_t segptr, unsigned int reg16)
{
    return cpu_lduw_data(env, segptr + (reg16 & 0xffff));
}

static inline unsigned int vm_getl(CPUX86State *env,
                                   uint32_t segptr, unsigned int reg16)
{
    return cpu_ldl_data(env, segptr + (reg16 & 0xffff));
}

void save_v86_state(CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;
    struct target_vm86plus_struct * target_v86;

    if (!lock_user_struct(VERIFY_WRITE, target_v86, ts->target_v86, 0))
        /* FIXME - should return an error */
        return;
    /* put the VM86 registers in the userspace register structure */
    target_v86->regs.eax = tswap32(env->regs[R_EAX]);
    target_v86->regs.ebx = tswap32(env->regs[R_EBX]);
    target_v86->regs.ecx = tswap32(env->regs[R_ECX]);
    target_v86->regs.edx = tswap32(env->regs[R_EDX]);
    target_v86->regs.esi = tswap32(env->regs[R_ESI]);
    target_v86->regs.edi = tswap32(env->regs[R_EDI]);
    target_v86->regs.ebp = tswap32(env->regs[R_EBP]);
    target_v86->regs.esp = tswap32(env->regs[R_ESP]);
    target_v86->regs.eip = tswap32(env->eip);
    target_v86->regs.cs = tswap16(env->segs[R_CS].selector);
    target_v86->regs.ss = tswap16(env->segs[R_SS].selector);
    target_v86->regs.ds = tswap16(env->segs[R_DS].selector);
    target_v86->regs.es = tswap16(env->segs[R_ES].selector);
    target_v86->regs.fs = tswap16(env->segs[R_FS].selector);
    target_v86->regs.gs = tswap16(env->segs[R_GS].selector);
    set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask);
    target_v86->regs.eflags = tswap32(env->eflags);
    unlock_user_struct(target_v86, ts->target_v86, 1);
    LOG_VM86("save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
             env->eflags, env->segs[R_CS].selector, env->eip);

    /* restore 32 bit registers */
    env->regs[R_EAX] = ts->vm86_saved_regs.eax;
    env->regs[R_EBX] = ts->vm86_saved_regs.ebx;
    env->regs[R_ECX] = ts->vm86_saved_regs.ecx;
    env->regs[R_EDX] = ts->vm86_saved_regs.edx;
    env->regs[R_ESI] = ts->vm86_saved_regs.esi;
    env->regs[R_EDI] = ts->vm86_saved_regs.edi;
    env->regs[R_EBP] = ts->vm86_saved_regs.ebp;
    env->regs[R_ESP] = ts->vm86_saved_regs.esp;
    env->eflags = ts->vm86_saved_regs.eflags;
    env->eip = ts->vm86_saved_regs.eip;

    cpu_x86_load_seg(env, R_CS, ts->vm86_saved_regs.cs);
    cpu_x86_load_seg(env, R_SS, ts->vm86_saved_regs.ss);
    cpu_x86_load_seg(env, R_DS, ts->vm86_saved_regs.ds);
    cpu_x86_load_seg(env, R_ES, ts->vm86_saved_regs.es);
    cpu_x86_load_seg(env, R_FS, ts->vm86_saved_regs.fs);
    cpu_x86_load_seg(env, R_GS, ts->vm86_saved_regs.gs);
}

/* return from vm86 mode to 32 bit. The vm86() syscall will return
   'retval' */
static inline void return_to_32bit(CPUX86State *env, int retval)
{
    LOG_VM86("return_to_32bit: ret=0x%x\n", retval);
    save_v86_state(env);
    env->regs[R_EAX] = retval;
}

static inline int set_IF(CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;

    ts->v86flags |= VIF_MASK;
    if (ts->v86flags & VIP_MASK) {
        return_to_32bit(env, TARGET_VM86_STI);
        return 1;
    }
    return 0;
}

static inline void clear_IF(CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;

    ts->v86flags &= ~VIF_MASK;
}

static inline void clear_TF(CPUX86State *env)
{
    env->eflags &= ~TF_MASK;
}

static inline void clear_AC(CPUX86State *env)
{
    env->eflags &= ~AC_MASK;
}

static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;

    set_flags(ts->v86flags, eflags, ts->v86mask);
    set_flags(env->eflags, eflags, SAFE_MASK);
    if (eflags & IF_MASK)
        return set_IF(env);
    else
        clear_IF(env);
    return 0;
}

static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;

    set_flags(ts->v86flags, flags, ts->v86mask & 0xffff);
    set_flags(env->eflags, flags, SAFE_MASK);
    if (flags & IF_MASK)
        return set_IF(env);
    else
        clear_IF(env);
    return 0;
}

static inline unsigned int get_vflags(CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;
    unsigned int flags;

    flags = env->eflags & RETURN_MASK;
    if (ts->v86flags & VIF_MASK)
        flags |= IF_MASK;
    flags |= IOPL_MASK;
    return flags | (ts->v86flags & ts->v86mask);
}

#define ADD16(reg, val) reg = (reg & ~0xffff) | ((reg + (val)) & 0xffff)

/* handle VM86 interrupt (NOTE: the CPU core currently does not
   support TSS interrupt revectoring, so this code is always executed) */
static void do_int(CPUX86State *env, int intno)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;
    uint32_t int_addr, segoffs, ssp;
    unsigned int sp;

    if (env->segs[R_CS].selector == TARGET_BIOSSEG)
        goto cannot_handle;
    if (is_revectored(intno, &ts->vm86plus.int_revectored))
        goto cannot_handle;
    if (intno == 0x21 && is_revectored((env->regs[R_EAX] >> 8) & 0xff,
                                       &ts->vm86plus.int21_revectored))
        goto cannot_handle;
    int_addr = (intno << 2);
    segoffs = cpu_ldl_data(env, int_addr);
    if ((segoffs >> 16) == TARGET_BIOSSEG)
        goto cannot_handle;
    LOG_VM86("VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
             intno, segoffs >> 16, segoffs & 0xffff);
    /* save old state */
    ssp = env->segs[R_SS].selector << 4;
    sp = env->regs[R_ESP] & 0xffff;
    vm_putw(env, ssp, sp - 2, get_vflags(env));
    vm_putw(env, ssp, sp - 4, env->segs[R_CS].selector);
    vm_putw(env, ssp, sp - 6, env->eip);
    ADD16(env->regs[R_ESP], -6);
    /* goto interrupt handler */
    env->eip = segoffs & 0xffff;
    cpu_x86_load_seg(env, R_CS, segoffs >> 16);
    clear_TF(env);
    clear_IF(env);
    clear_AC(env);
    return;
 cannot_handle:
    LOG_VM86("VM86: return to 32 bits int 0x%x\n", intno);
    return_to_32bit(env, TARGET_VM86_INTx | (intno << 8));
}

void handle_vm86_trap(CPUX86State *env, int trapno)
{
    if (trapno == 1 || trapno == 3) {
        return_to_32bit(env, TARGET_VM86_TRAP + (trapno << 8));
    } else {
        do_int(env, trapno);
    }
}

#define CHECK_IF_IN_TRAP() \
      if ((ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) && \
          (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_TFpendig)) \
		newflags |= TF_MASK

#define VM86_FAULT_RETURN \
        if ((ts->vm86plus.vm86plus.flags & TARGET_force_return_for_pic) && \
            (ts->v86flags & (IF_MASK | VIF_MASK))) \
            return_to_32bit(env, TARGET_VM86_PICRETURN); \
        return

void handle_vm86_fault(CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;
    uint32_t csp, ssp;
    unsigned int ip, sp, newflags, newip, newcs, opcode, intno;
    int data32, pref_done;

    csp = env->segs[R_CS].selector << 4;
    ip = env->eip & 0xffff;

    ssp = env->segs[R_SS].selector << 4;
    sp = env->regs[R_ESP] & 0xffff;

    LOG_VM86("VM86 exception %04x:%08x\n",
             env->segs[R_CS].selector, env->eip);

    data32 = 0;
    pref_done = 0;
    do {
        opcode = vm_getb(env, csp, ip);
        ADD16(ip, 1);
        switch (opcode) {
        case 0x66:      /* 32-bit data */     data32=1; break;
        case 0x67:      /* 32-bit address */  break;
        case 0x2e:      /* CS */              break;
        case 0x3e:      /* DS */              break;
        case 0x26:      /* ES */              break;
        case 0x36:      /* SS */              break;
        case 0x65:      /* GS */              break;
        case 0x64:      /* FS */              break;
        case 0xf2:      /* repnz */	      break;
        case 0xf3:      /* rep */             break;
        default: pref_done = 1;
        }
    } while (!pref_done);

    /* VM86 mode */
    switch(opcode) {
    case 0x9c: /* pushf */
        if (data32) {
            vm_putl(env, ssp, sp - 4, get_vflags(env));
            ADD16(env->regs[R_ESP], -4);
        } else {
            vm_putw(env, ssp, sp - 2, get_vflags(env));
            ADD16(env->regs[R_ESP], -2);
        }
        env->eip = ip;
        VM86_FAULT_RETURN;

    case 0x9d: /* popf */
        if (data32) {
            newflags = vm_getl(env, ssp, sp);
            ADD16(env->regs[R_ESP], 4);
        } else {
            newflags = vm_getw(env, ssp, sp);
            ADD16(env->regs[R_ESP], 2);
        }
        env->eip = ip;
        CHECK_IF_IN_TRAP();
        if (data32) {
            if (set_vflags_long(newflags, env))
                return;
        } else {
            if (set_vflags_short(newflags, env))
                return;
        }
        VM86_FAULT_RETURN;

    case 0xcd: /* int */
        intno = vm_getb(env, csp, ip);
        ADD16(ip, 1);
        env->eip = ip;
        if (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) {
            if ( (ts->vm86plus.vm86plus.vm86dbg_intxxtab[intno >> 3] >>
                  (intno &7)) & 1) {
                return_to_32bit(env, TARGET_VM86_INTx + (intno << 8));
                return;
            }
        }
        do_int(env, intno);
        break;

    case 0xcf: /* iret */
        if (data32) {
            newip = vm_getl(env, ssp, sp) & 0xffff;
            newcs = vm_getl(env, ssp, sp + 4) & 0xffff;
            newflags = vm_getl(env, ssp, sp + 8);
            ADD16(env->regs[R_ESP], 12);
        } else {
            newip = vm_getw(env, ssp, sp);
            newcs = vm_getw(env, ssp, sp + 2);
            newflags = vm_getw(env, ssp, sp + 4);
            ADD16(env->regs[R_ESP], 6);
        }
        env->eip = newip;
        cpu_x86_load_seg(env, R_CS, newcs);
        CHECK_IF_IN_TRAP();
        if (data32) {
            if (set_vflags_long(newflags, env))
                return;
        } else {
            if (set_vflags_short(newflags, env))
                return;
        }
        VM86_FAULT_RETURN;

    case 0xfa: /* cli */
        env->eip = ip;
        clear_IF(env);
        VM86_FAULT_RETURN;

    case 0xfb: /* sti */
        env->eip = ip;
        if (set_IF(env))
            return;
        VM86_FAULT_RETURN;

    default:
        /* real VM86 GPF exception */
        return_to_32bit(env, TARGET_VM86_UNKNOWN);
        break;
    }
}

int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;
    struct target_vm86plus_struct * target_v86;
    int ret;

    switch (subfunction) {
    case TARGET_VM86_REQUEST_IRQ:
    case TARGET_VM86_FREE_IRQ:
    case TARGET_VM86_GET_IRQ_BITS:
    case TARGET_VM86_GET_AND_RESET_IRQ:
        gemu_log("qemu: unsupported vm86 subfunction (%ld)\n", subfunction);
        ret = -TARGET_EINVAL;
        goto out;
    case TARGET_VM86_PLUS_INSTALL_CHECK:
        /* NOTE: on old vm86 stuff this will return the error
           from verify_area(), because the subfunction is
           interpreted as (invalid) address to vm86_struct.
           So the installation check works.
            */
        ret = 0;
        goto out;
    }

    /* save current CPU regs */
    ts->vm86_saved_regs.eax = 0; /* default vm86 syscall return code */
    ts->vm86_saved_regs.ebx = env->regs[R_EBX];
    ts->vm86_saved_regs.ecx = env->regs[R_ECX];
    ts->vm86_saved_regs.edx = env->regs[R_EDX];
    ts->vm86_saved_regs.esi = env->regs[R_ESI];
    ts->vm86_saved_regs.edi = env->regs[R_EDI];
    ts->vm86_saved_regs.ebp = env->regs[R_EBP];
    ts->vm86_saved_regs.esp = env->regs[R_ESP];
    ts->vm86_saved_regs.eflags = env->eflags;
    ts->vm86_saved_regs.eip  = env->eip;
    ts->vm86_saved_regs.cs = env->segs[R_CS].selector;
    ts->vm86_saved_regs.ss = env->segs[R_SS].selector;
    ts->vm86_saved_regs.ds = env->segs[R_DS].selector;
    ts->vm86_saved_regs.es = env->segs[R_ES].selector;
    ts->vm86_saved_regs.fs = env->segs[R_FS].selector;
    ts->vm86_saved_regs.gs = env->segs[R_GS].selector;

    ts->target_v86 = vm86_addr;
    if (!lock_user_struct(VERIFY_READ, target_v86, vm86_addr, 1))
        return -TARGET_EFAULT;
    /* build vm86 CPU state */
    ts->v86flags = tswap32(target_v86->regs.eflags);
    env->eflags = (env->eflags & ~SAFE_MASK) |
        (tswap32(target_v86->regs.eflags) & SAFE_MASK) | VM_MASK;

    ts->vm86plus.cpu_type = tswapal(target_v86->cpu_type);
    switch (ts->vm86plus.cpu_type) {
    case TARGET_CPU_286:
        ts->v86mask = 0;
        break;
    case TARGET_CPU_386:
        ts->v86mask = NT_MASK | IOPL_MASK;
        break;
    case TARGET_CPU_486:
        ts->v86mask = AC_MASK | NT_MASK | IOPL_MASK;
        break;
    default:
        ts->v86mask = ID_MASK | AC_MASK | NT_MASK | IOPL_MASK;
        break;
    }

    env->regs[R_EBX] = tswap32(target_v86->regs.ebx);
    env->regs[R_ECX] = tswap32(target_v86->regs.ecx);
    env->regs[R_EDX] = tswap32(target_v86->regs.edx);
    env->regs[R_ESI] = tswap32(target_v86->regs.esi);
    env->regs[R_EDI] = tswap32(target_v86->regs.edi);
    env->regs[R_EBP] = tswap32(target_v86->regs.ebp);
    env->regs[R_ESP] = tswap32(target_v86->regs.esp);
    env->eip = tswap32(target_v86->regs.eip);
    cpu_x86_load_seg(env, R_CS, tswap16(target_v86->regs.cs));
    cpu_x86_load_seg(env, R_SS, tswap16(target_v86->regs.ss));
    cpu_x86_load_seg(env, R_DS, tswap16(target_v86->regs.ds));
    cpu_x86_load_seg(env, R_ES, tswap16(target_v86->regs.es));
    cpu_x86_load_seg(env, R_FS, tswap16(target_v86->regs.fs));
    cpu_x86_load_seg(env, R_GS, tswap16(target_v86->regs.gs));
    ret = tswap32(target_v86->regs.eax); /* eax will be restored at
                                            the end of the syscall */
    memcpy(&ts->vm86plus.int_revectored,
           &target_v86->int_revectored, 32);
    memcpy(&ts->vm86plus.int21_revectored,
           &target_v86->int21_revectored, 32);
    ts->vm86plus.vm86plus.flags = tswapal(target_v86->vm86plus.flags);
    memcpy(&ts->vm86plus.vm86plus.vm86dbg_intxxtab,
           target_v86->vm86plus.vm86dbg_intxxtab, 32);
    unlock_user_struct(target_v86, vm86_addr, 0);

    LOG_VM86("do_vm86: cs:ip=%04x:%04x\n",
             env->segs[R_CS].selector, env->eip);
    /* now the virtual CPU is ready for vm86 execution ! */
 out:
    return ret;
}
Commit	Line	Data
46ddf551 FB	1	/*
46ddf551 FB	2	* vm86 linux syscall support
5fafdf24	3	*
46ddf551 FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
8167ee88	17	* along with this program; if not, see <http://www.gnu.org/licenses/>.
46ddf551	18	*/
d39594e9	19	#include "qemu/osdep.h"
46ddf551 FB	20
	21	#include "qemu.h"
	22
	23	//#define DEBUG_VM86
	24
d12d51d5	25	#ifdef DEBUG_VM86
93fcfe39	26	# define LOG_VM86(...) qemu_log(__VA_ARGS__);
d12d51d5 AL	27	#else
	28	# define LOG_VM86(...) do { } while (0)
	29	#endif
	30
	31
46ddf551 FB	32	#define set_flags(X,new,mask) \
	33	((X) = ((X) & ~(mask)) \| ((new) & (mask)))
	34
	35	#define SAFE_MASK (0xDD5)
	36	#define RETURN_MASK (0xDFF)
	37
	38	static inline int is_revectored(int nr, struct target_revectored_struct *bitmap)
	39	{
b333af06	40	return (((uint8_t *)bitmap)[nr >> 3] >> (nr & 7)) & 1;
46ddf551 FB	41	}
46ddf551 FB	42
5899d6d0 PM	43	static inline void vm_putw(CPUX86State *env, uint32_t segptr,
5899d6d0 PM	44	unsigned int reg16, unsigned int val)
46ddf551	45	{
5899d6d0	46	cpu_stw_data(env, segptr + (reg16 & 0xffff), val);
46ddf551 FB	47	}
46ddf551 FB	48
5899d6d0 PM	49	static inline void vm_putl(CPUX86State *env, uint32_t segptr,
5899d6d0 PM	50	unsigned int reg16, unsigned int val)
46ddf551	51	{
5899d6d0	52	cpu_stl_data(env, segptr + (reg16 & 0xffff), val);
46ddf551 FB	53	}
46ddf551 FB	54
5899d6d0 PM	55	static inline unsigned int vm_getb(CPUX86State *env,
5899d6d0 PM	56	uint32_t segptr, unsigned int reg16)
1455bf48	57	{
5899d6d0	58	return cpu_ldub_data(env, segptr + (reg16 & 0xffff));
1455bf48 FB	59	}
1455bf48 FB	60
5899d6d0 PM	61	static inline unsigned int vm_getw(CPUX86State *env,
5899d6d0 PM	62	uint32_t segptr, unsigned int reg16)
46ddf551	63	{
5899d6d0	64	return cpu_lduw_data(env, segptr + (reg16 & 0xffff));
46ddf551 FB	65	}
46ddf551 FB	66
5899d6d0 PM	67	static inline unsigned int vm_getl(CPUX86State *env,
5899d6d0 PM	68	uint32_t segptr, unsigned int reg16)
46ddf551	69	{
5899d6d0	70	return cpu_ldl_data(env, segptr + (reg16 & 0xffff));
46ddf551 FB	71	}
	72
	73	void save_v86_state(CPUX86State *env)
	74	{
0429a971 AF	75	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	76	TaskState *ts = cs->opaque;
53a5960a	77	struct target_vm86plus_struct * target_v86;
46ddf551	78
579a97f7 FB	79	if (!lock_user_struct(VERIFY_WRITE, target_v86, ts->target_v86, 0))
	80	/* FIXME - should return an error */
	81	return;
46ddf551	82	/* put the VM86 registers in the userspace register structure */
53a5960a PB	83	target_v86->regs.eax = tswap32(env->regs[R_EAX]);
	84	target_v86->regs.ebx = tswap32(env->regs[R_EBX]);
	85	target_v86->regs.ecx = tswap32(env->regs[R_ECX]);
	86	target_v86->regs.edx = tswap32(env->regs[R_EDX]);
	87	target_v86->regs.esi = tswap32(env->regs[R_ESI]);
	88	target_v86->regs.edi = tswap32(env->regs[R_EDI]);
	89	target_v86->regs.ebp = tswap32(env->regs[R_EBP]);
	90	target_v86->regs.esp = tswap32(env->regs[R_ESP]);
	91	target_v86->regs.eip = tswap32(env->eip);
	92	target_v86->regs.cs = tswap16(env->segs[R_CS].selector);
	93	target_v86->regs.ss = tswap16(env->segs[R_SS].selector);
	94	target_v86->regs.ds = tswap16(env->segs[R_DS].selector);
	95	target_v86->regs.es = tswap16(env->segs[R_ES].selector);
	96	target_v86->regs.fs = tswap16(env->segs[R_FS].selector);
	97	target_v86->regs.gs = tswap16(env->segs[R_GS].selector);
46ddf551	98	set_flags(env->eflags, ts->v86flags, VIF_MASK \| ts->v86mask);
53a5960a PB	99	target_v86->regs.eflags = tswap32(env->eflags);
53a5960a PB	100	unlock_user_struct(target_v86, ts->target_v86, 1);
d12d51d5 AL	101	LOG_VM86("save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
d12d51d5 AL	102	env->eflags, env->segs[R_CS].selector, env->eip);
46ddf551 FB	103
	104	/* restore 32 bit registers */
	105	env->regs[R_EAX] = ts->vm86_saved_regs.eax;
	106	env->regs[R_EBX] = ts->vm86_saved_regs.ebx;
	107	env->regs[R_ECX] = ts->vm86_saved_regs.ecx;
	108	env->regs[R_EDX] = ts->vm86_saved_regs.edx;
	109	env->regs[R_ESI] = ts->vm86_saved_regs.esi;
	110	env->regs[R_EDI] = ts->vm86_saved_regs.edi;
	111	env->regs[R_EBP] = ts->vm86_saved_regs.ebp;
	112	env->regs[R_ESP] = ts->vm86_saved_regs.esp;
	113	env->eflags = ts->vm86_saved_regs.eflags;
	114	env->eip = ts->vm86_saved_regs.eip;
	115
	116	cpu_x86_load_seg(env, R_CS, ts->vm86_saved_regs.cs);
	117	cpu_x86_load_seg(env, R_SS, ts->vm86_saved_regs.ss);
	118	cpu_x86_load_seg(env, R_DS, ts->vm86_saved_regs.ds);
	119	cpu_x86_load_seg(env, R_ES, ts->vm86_saved_regs.es);
	120	cpu_x86_load_seg(env, R_FS, ts->vm86_saved_regs.fs);
	121	cpu_x86_load_seg(env, R_GS, ts->vm86_saved_regs.gs);
	122	}
	123
	124	/* return from vm86 mode to 32 bit. The vm86() syscall will return
	125	'retval' */
	126	static inline void return_to_32bit(CPUX86State *env, int retval)
	127	{
d12d51d5	128	LOG_VM86("return_to_32bit: ret=0x%x\n", retval);
46ddf551 FB	129	save_v86_state(env);
	130	env->regs[R_EAX] = retval;
	131	}
	132
	133	static inline int set_IF(CPUX86State *env)
	134	{
0429a971 AF	135	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	136	TaskState *ts = cs->opaque;
3b46e624	137
46ddf551 FB	138	ts->v86flags \|= VIF_MASK;
	139	if (ts->v86flags & VIP_MASK) {
	140	return_to_32bit(env, TARGET_VM86_STI);
	141	return 1;
	142	}
	143	return 0;
	144	}
	145
	146	static inline void clear_IF(CPUX86State *env)
	147	{
0429a971 AF	148	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	149	TaskState *ts = cs->opaque;
46ddf551 FB	150
	151	ts->v86flags &= ~VIF_MASK;
	152	}
	153
	154	static inline void clear_TF(CPUX86State *env)
	155	{
	156	env->eflags &= ~TF_MASK;
	157	}
	158
226c9132 FB	159	static inline void clear_AC(CPUX86State *env)
	160	{
	161	env->eflags &= ~AC_MASK;
	162	}
	163
46ddf551 FB	164	static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
46ddf551 FB	165	{
0429a971 AF	166	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	167	TaskState *ts = cs->opaque;
46ddf551 FB	168
	169	set_flags(ts->v86flags, eflags, ts->v86mask);
	170	set_flags(env->eflags, eflags, SAFE_MASK);
	171	if (eflags & IF_MASK)
	172	return set_IF(env);
226c9132 FB	173	else
226c9132 FB	174	clear_IF(env);
46ddf551 FB	175	return 0;
	176	}
	177
	178	static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
	179	{
0429a971 AF	180	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	181	TaskState *ts = cs->opaque;
46ddf551 FB	182
	183	set_flags(ts->v86flags, flags, ts->v86mask & 0xffff);
	184	set_flags(env->eflags, flags, SAFE_MASK);
	185	if (flags & IF_MASK)
	186	return set_IF(env);
226c9132 FB	187	else
226c9132 FB	188	clear_IF(env);
46ddf551 FB	189	return 0;
	190	}
	191
	192	static inline unsigned int get_vflags(CPUX86State *env)
	193	{
0429a971 AF	194	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	195	TaskState *ts = cs->opaque;
46ddf551 FB	196	unsigned int flags;
	197
	198	flags = env->eflags & RETURN_MASK;
	199	if (ts->v86flags & VIF_MASK)
	200	flags \|= IF_MASK;
c05bab77	201	flags \|= IOPL_MASK;
46ddf551 FB	202	return flags \| (ts->v86flags & ts->v86mask);
	203	}
	204
	205	#define ADD16(reg, val) reg = (reg & ~0xffff) \| ((reg + (val)) & 0xffff)
	206
	207	/* handle VM86 interrupt (NOTE: the CPU core currently does not
	208	support TSS interrupt revectoring, so this code is always executed) */
447db213	209	static void do_int(CPUX86State *env, int intno)
46ddf551	210	{
0429a971 AF	211	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	212	TaskState *ts = cs->opaque;
1455bf48	213	uint32_t int_addr, segoffs, ssp;
46ddf551 FB	214	unsigned int sp;
46ddf551 FB	215
c05bab77	216	if (env->segs[R_CS].selector == TARGET_BIOSSEG)
46ddf551	217	goto cannot_handle;
b333af06	218	if (is_revectored(intno, &ts->vm86plus.int_revectored))
46ddf551	219	goto cannot_handle;
5fafdf24	220	if (intno == 0x21 && is_revectored((env->regs[R_EAX] >> 8) & 0xff,
b333af06	221	&ts->vm86plus.int21_revectored))
46ddf551	222	goto cannot_handle;
1455bf48	223	int_addr = (intno << 2);
5899d6d0	224	segoffs = cpu_ldl_data(env, int_addr);
46ddf551 FB	225	if ((segoffs >> 16) == TARGET_BIOSSEG)
46ddf551 FB	226	goto cannot_handle;
d12d51d5 AL	227	LOG_VM86("VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
d12d51d5 AL	228	intno, segoffs >> 16, segoffs & 0xffff);
46ddf551	229	/* save old state */
1455bf48	230	ssp = env->segs[R_SS].selector << 4;
46ddf551	231	sp = env->regs[R_ESP] & 0xffff;
5899d6d0 PM	232	vm_putw(env, ssp, sp - 2, get_vflags(env));
	233	vm_putw(env, ssp, sp - 4, env->segs[R_CS].selector);
	234	vm_putw(env, ssp, sp - 6, env->eip);
46ddf551 FB	235	ADD16(env->regs[R_ESP], -6);
	236	/* goto interrupt handler */
	237	env->eip = segoffs & 0xffff;
	238	cpu_x86_load_seg(env, R_CS, segoffs >> 16);
	239	clear_TF(env);
	240	clear_IF(env);
226c9132	241	clear_AC(env);
46ddf551 FB	242	return;
46ddf551 FB	243	cannot_handle:
d12d51d5	244	LOG_VM86("VM86: return to 32 bits int 0x%x\n", intno);
46ddf551 FB	245	return_to_32bit(env, TARGET_VM86_INTx \| (intno << 8));
	246	}
	247
447db213 FB	248	void handle_vm86_trap(CPUX86State *env, int trapno)
	249	{
	250	if (trapno == 1 \|\| trapno == 3) {
	251	return_to_32bit(env, TARGET_VM86_TRAP + (trapno << 8));
	252	} else {
	253	do_int(env, trapno);
	254	}
	255	}
	256
b333af06 FB	257	#define CHECK_IF_IN_TRAP() \
	258	if ((ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) && \
	259	(ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_TFpendig)) \
	260	newflags \|= TF_MASK
46ddf551 FB	261
46ddf551 FB	262	#define VM86_FAULT_RETURN \
b333af06	263	if ((ts->vm86plus.vm86plus.flags & TARGET_force_return_for_pic) && \
46ddf551 FB	264	(ts->v86flags & (IF_MASK \| VIF_MASK))) \
	265	return_to_32bit(env, TARGET_VM86_PICRETURN); \
	266	return
	267
	268	void handle_vm86_fault(CPUX86State *env)
	269	{
0429a971 AF	270	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	271	TaskState *ts = cs->opaque;
1455bf48	272	uint32_t csp, ssp;
b333af06 FB	273	unsigned int ip, sp, newflags, newip, newcs, opcode, intno;
b333af06 FB	274	int data32, pref_done;
46ddf551	275
1455bf48	276	csp = env->segs[R_CS].selector << 4;
46ddf551	277	ip = env->eip & 0xffff;
3b46e624	278
1455bf48	279	ssp = env->segs[R_SS].selector << 4;
46ddf551 FB	280	sp = env->regs[R_ESP] & 0xffff;
46ddf551 FB	281
d12d51d5 AL	282	LOG_VM86("VM86 exception %04x:%08x\n",
d12d51d5 AL	283	env->segs[R_CS].selector, env->eip);
46ddf551	284
b333af06 FB	285	data32 = 0;
	286	pref_done = 0;
	287	do {
5899d6d0	288	opcode = vm_getb(env, csp, ip);
b333af06 FB	289	ADD16(ip, 1);
	290	switch (opcode) {
	291	case 0x66: /* 32-bit data */ data32=1; break;
	292	case 0x67: /* 32-bit address */ break;
	293	case 0x2e: /* CS */ break;
	294	case 0x3e: /* DS */ break;
	295	case 0x26: /* ES */ break;
	296	case 0x36: /* SS */ break;
	297	case 0x65: /* GS */ break;
	298	case 0x64: /* FS */ break;
	299	case 0xf2: /* repnz */ break;
	300	case 0xf3: /* rep */ break;
	301	default: pref_done = 1;
	302	}
	303	} while (!pref_done);
	304
46ddf551	305	/* VM86 mode */
b333af06 FB	306	switch(opcode) {
b333af06 FB	307	case 0x9c: /* pushf */
b333af06	308	if (data32) {
5899d6d0	309	vm_putl(env, ssp, sp - 4, get_vflags(env));
b333af06 FB	310	ADD16(env->regs[R_ESP], -4);
b333af06 FB	311	} else {
5899d6d0	312	vm_putw(env, ssp, sp - 2, get_vflags(env));
b333af06 FB	313	ADD16(env->regs[R_ESP], -2);
	314	}
	315	env->eip = ip;
	316	VM86_FAULT_RETURN;
46ddf551	317
b333af06 FB	318	case 0x9d: /* popf */
b333af06 FB	319	if (data32) {
5899d6d0	320	newflags = vm_getl(env, ssp, sp);
46ddf551	321	ADD16(env->regs[R_ESP], 4);
b333af06	322	} else {
5899d6d0	323	newflags = vm_getw(env, ssp, sp);
b333af06 FB	324	ADD16(env->regs[R_ESP], 2);
	325	}
	326	env->eip = ip;
	327	CHECK_IF_IN_TRAP();
	328	if (data32) {
	329	if (set_vflags_long(newflags, env))
46ddf551	330	return;
b333af06 FB	331	} else {
b333af06 FB	332	if (set_vflags_short(newflags, env))
46ddf551	333	return;
46ddf551	334	}
46ddf551 FB	335	VM86_FAULT_RETURN;
	336
	337	case 0xcd: /* int */
5899d6d0	338	intno = vm_getb(env, csp, ip);
b333af06 FB	339	ADD16(ip, 1);
	340	env->eip = ip;
	341	if (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) {
5fafdf24	342	if ( (ts->vm86plus.vm86plus.vm86dbg_intxxtab[intno >> 3] >>
b333af06 FB	343	(intno &7)) & 1) {
	344	return_to_32bit(env, TARGET_VM86_INTx + (intno << 8));
	345	return;
	346	}
	347	}
	348	do_int(env, intno);
46ddf551 FB	349	break;
	350
	351	case 0xcf: /* iret */
b333af06	352	if (data32) {
5899d6d0 PM	353	newip = vm_getl(env, ssp, sp) & 0xffff;
	354	newcs = vm_getl(env, ssp, sp + 4) & 0xffff;
	355	newflags = vm_getl(env, ssp, sp + 8);
b333af06 FB	356	ADD16(env->regs[R_ESP], 12);
b333af06 FB	357	} else {
5899d6d0 PM	358	newip = vm_getw(env, ssp, sp);
	359	newcs = vm_getw(env, ssp, sp + 2);
	360	newflags = vm_getw(env, ssp, sp + 4);
b333af06 FB	361	ADD16(env->regs[R_ESP], 6);
	362	}
	363	env->eip = newip;
	364	cpu_x86_load_seg(env, R_CS, newcs);
	365	CHECK_IF_IN_TRAP();
	366	if (data32) {
	367	if (set_vflags_long(newflags, env))
	368	return;
	369	} else {
	370	if (set_vflags_short(newflags, env))
	371	return;
	372	}
46ddf551	373	VM86_FAULT_RETURN;
3b46e624	374
46ddf551	375	case 0xfa: /* cli */
b333af06	376	env->eip = ip;
46ddf551 FB	377	clear_IF(env);
46ddf551 FB	378	VM86_FAULT_RETURN;
3b46e624	379
46ddf551	380	case 0xfb: /* sti */
b333af06	381	env->eip = ip;
46ddf551 FB	382	if (set_IF(env))
	383	return;
	384	VM86_FAULT_RETURN;
	385
	386	default:
46ddf551 FB	387	/* real VM86 GPF exception */
	388	return_to_32bit(env, TARGET_VM86_UNKNOWN);
	389	break;
	390	}
	391	}
	392
992f48a0	393	int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr)
46ddf551	394	{
0429a971 AF	395	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	396	TaskState *ts = cs->opaque;
53a5960a	397	struct target_vm86plus_struct * target_v86;
46ddf551	398	int ret;
3b46e624	399
46ddf551 FB	400	switch (subfunction) {
	401	case TARGET_VM86_REQUEST_IRQ:
	402	case TARGET_VM86_FREE_IRQ:
	403	case TARGET_VM86_GET_IRQ_BITS:
	404	case TARGET_VM86_GET_AND_RESET_IRQ:
	405	gemu_log("qemu: unsupported vm86 subfunction (%ld)\n", subfunction);
6c30b07f	406	ret = -TARGET_EINVAL;
46ddf551 FB	407	goto out;
	408	case TARGET_VM86_PLUS_INSTALL_CHECK:
	409	/* NOTE: on old vm86 stuff this will return the error
	410	from verify_area(), because the subfunction is
	411	interpreted as (invalid) address to vm86_struct.
	412	So the installation check works.
	413	*/
	414	ret = 0;
	415	goto out;
	416	}
	417
46ddf551 FB	418	/* save current CPU regs */
	419	ts->vm86_saved_regs.eax = 0; /* default vm86 syscall return code */
	420	ts->vm86_saved_regs.ebx = env->regs[R_EBX];
	421	ts->vm86_saved_regs.ecx = env->regs[R_ECX];
	422	ts->vm86_saved_regs.edx = env->regs[R_EDX];
	423	ts->vm86_saved_regs.esi = env->regs[R_ESI];
	424	ts->vm86_saved_regs.edi = env->regs[R_EDI];
	425	ts->vm86_saved_regs.ebp = env->regs[R_EBP];
	426	ts->vm86_saved_regs.esp = env->regs[R_ESP];
	427	ts->vm86_saved_regs.eflags = env->eflags;
	428	ts->vm86_saved_regs.eip = env->eip;
c05bab77 FB	429	ts->vm86_saved_regs.cs = env->segs[R_CS].selector;
	430	ts->vm86_saved_regs.ss = env->segs[R_SS].selector;
	431	ts->vm86_saved_regs.ds = env->segs[R_DS].selector;
	432	ts->vm86_saved_regs.es = env->segs[R_ES].selector;
	433	ts->vm86_saved_regs.fs = env->segs[R_FS].selector;
	434	ts->vm86_saved_regs.gs = env->segs[R_GS].selector;
46ddf551	435
53a5960a	436	ts->target_v86 = vm86_addr;
579a97f7	437	if (!lock_user_struct(VERIFY_READ, target_v86, vm86_addr, 1))
6c30b07f	438	return -TARGET_EFAULT;
46ddf551 FB	439	/* build vm86 CPU state */
46ddf551 FB	440	ts->v86flags = tswap32(target_v86->regs.eflags);
5fafdf24	441	env->eflags = (env->eflags & ~SAFE_MASK) \|
46ddf551	442	(tswap32(target_v86->regs.eflags) & SAFE_MASK) \| VM_MASK;
b333af06	443
cbb21eed	444	ts->vm86plus.cpu_type = tswapal(target_v86->cpu_type);
b333af06 FB	445	switch (ts->vm86plus.cpu_type) {
	446	case TARGET_CPU_286:
	447	ts->v86mask = 0;
	448	break;
	449	case TARGET_CPU_386:
	450	ts->v86mask = NT_MASK \| IOPL_MASK;
	451	break;
	452	case TARGET_CPU_486:
	453	ts->v86mask = AC_MASK \| NT_MASK \| IOPL_MASK;
	454	break;
	455	default:
	456	ts->v86mask = ID_MASK \| AC_MASK \| NT_MASK \| IOPL_MASK;
	457	break;
	458	}
46ddf551 FB	459
	460	env->regs[R_EBX] = tswap32(target_v86->regs.ebx);
	461	env->regs[R_ECX] = tswap32(target_v86->regs.ecx);
	462	env->regs[R_EDX] = tswap32(target_v86->regs.edx);
	463	env->regs[R_ESI] = tswap32(target_v86->regs.esi);
	464	env->regs[R_EDI] = tswap32(target_v86->regs.edi);
	465	env->regs[R_EBP] = tswap32(target_v86->regs.ebp);
	466	env->regs[R_ESP] = tswap32(target_v86->regs.esp);
	467	env->eip = tswap32(target_v86->regs.eip);
	468	cpu_x86_load_seg(env, R_CS, tswap16(target_v86->regs.cs));
	469	cpu_x86_load_seg(env, R_SS, tswap16(target_v86->regs.ss));
	470	cpu_x86_load_seg(env, R_DS, tswap16(target_v86->regs.ds));
	471	cpu_x86_load_seg(env, R_ES, tswap16(target_v86->regs.es));
	472	cpu_x86_load_seg(env, R_FS, tswap16(target_v86->regs.fs));
	473	cpu_x86_load_seg(env, R_GS, tswap16(target_v86->regs.gs));
	474	ret = tswap32(target_v86->regs.eax); /* eax will be restored at
	475	the end of the syscall */
5fafdf24	476	memcpy(&ts->vm86plus.int_revectored,
b333af06	477	&target_v86->int_revectored, 32);
5fafdf24	478	memcpy(&ts->vm86plus.int21_revectored,
b333af06	479	&target_v86->int21_revectored, 32);
cbb21eed	480	ts->vm86plus.vm86plus.flags = tswapal(target_v86->vm86plus.flags);
5fafdf24	481	memcpy(&ts->vm86plus.vm86plus.vm86dbg_intxxtab,
b333af06	482	target_v86->vm86plus.vm86dbg_intxxtab, 32);
53a5960a	483	unlock_user_struct(target_v86, vm86_addr, 0);
3b46e624	484
d12d51d5 AL	485	LOG_VM86("do_vm86: cs:ip=%04x:%04x\n",
d12d51d5 AL	486	env->segs[R_CS].selector, env->eip);
46ddf551 FB	487	/* now the virtual CPU is ready for vm86 execution ! */
	488	out:
	489	return ret;
	490	}