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1d0cb67d AF |
1 | /* |
2 | * QEMU PowerPC CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see | |
18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
19 | */ | |
20 | #ifndef QEMU_PPC_CPU_QOM_H | |
21 | #define QEMU_PPC_CPU_QOM_H | |
22 | ||
14cccb61 | 23 | #include "qom/cpu.h" |
1d0cb67d AF |
24 | #include "cpu.h" |
25 | ||
26 | #ifdef TARGET_PPC64 | |
27 | #define TYPE_POWERPC_CPU "powerpc64-cpu" | |
28 | #elif defined(TARGET_PPCEMB) | |
29 | #define TYPE_POWERPC_CPU "embedded-powerpc-cpu" | |
30 | #else | |
31 | #define TYPE_POWERPC_CPU "powerpc-cpu" | |
32 | #endif | |
33 | ||
34 | #define POWERPC_CPU_CLASS(klass) \ | |
35 | OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU) | |
36 | #define POWERPC_CPU(obj) \ | |
37 | OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU) | |
38 | #define POWERPC_CPU_GET_CLASS(obj) \ | |
39 | OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU) | |
40 | ||
d0e39c5d AF |
41 | typedef struct PowerPCCPU PowerPCCPU; |
42 | ||
1d0cb67d AF |
43 | /** |
44 | * PowerPCCPUClass: | |
4776ce60 | 45 | * @parent_realize: The parent class' realize handler. |
1d0cb67d AF |
46 | * @parent_reset: The parent class' reset handler. |
47 | * | |
48 | * A PowerPC CPU model. | |
49 | */ | |
50 | typedef struct PowerPCCPUClass { | |
51 | /*< private >*/ | |
52 | CPUClass parent_class; | |
53 | /*< public >*/ | |
54 | ||
4776ce60 | 55 | DeviceRealize parent_realize; |
1d0cb67d | 56 | void (*parent_reset)(CPUState *cpu); |
2985b86b | 57 | |
cfe34f44 | 58 | uint32_t pvr; |
3bc9ccc0 | 59 | uint32_t pvr_mask; |
cfe34f44 AF |
60 | uint32_t svr; |
61 | uint64_t insns_flags; | |
62 | uint64_t insns_flags2; | |
63 | uint64_t msr_mask; | |
64 | powerpc_mmu_t mmu_model; | |
65 | powerpc_excp_t excp_model; | |
66 | powerpc_input_t bus_model; | |
67 | uint32_t flags; | |
68 | int bfd_mach; | |
0cbad81f | 69 | uint32_t l1_dcache_size, l1_icache_size; |
cfe34f44 AF |
70 | #if defined(TARGET_PPC64) |
71 | const struct ppc_segment_page_sizes *sps; | |
72 | #endif | |
73 | void (*init_proc)(CPUPPCState *env); | |
74 | int (*check_pow)(CPUPPCState *env); | |
b632a148 | 75 | #if defined(CONFIG_SOFTMMU) |
d0e39c5d | 76 | int (*handle_mmu_fault)(PowerPCCPU *cpu, target_ulong eaddr, int rwx, |
b632a148 DG |
77 | int mmu_idx); |
78 | #endif | |
1d0cb67d AF |
79 | } PowerPCCPUClass; |
80 | ||
81 | /** | |
82 | * PowerPCCPU: | |
83 | * @env: #CPUPPCState | |
0ce470cd | 84 | * @cpu_dt_id: CPU index used in the device tree. KVM uses this index too |
1d0cb67d AF |
85 | * |
86 | * A PowerPC CPU. | |
87 | */ | |
d0e39c5d | 88 | struct PowerPCCPU { |
1d0cb67d AF |
89 | /*< private >*/ |
90 | CPUState parent_obj; | |
91 | /*< public >*/ | |
92 | ||
93 | CPUPPCState env; | |
0ce470cd | 94 | int cpu_dt_id; |
d0e39c5d | 95 | }; |
1d0cb67d AF |
96 | |
97 | static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env) | |
98 | { | |
6e42be7c | 99 | return container_of(env, PowerPCCPU, env); |
1d0cb67d AF |
100 | } |
101 | ||
102 | #define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e)) | |
103 | ||
fadf9825 | 104 | #define ENV_OFFSET offsetof(PowerPCCPU, env) |
2985b86b | 105 | |
fadf9825 | 106 | PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); |
3bc9ccc0 | 107 | PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr); |
1d0cb67d | 108 | |
97a8ea5a | 109 | void ppc_cpu_do_interrupt(CPUState *cpu); |
878096ee AF |
110 | void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, |
111 | int flags); | |
112 | void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f, | |
113 | fprintf_function cpu_fprintf, int flags); | |
00b941e5 | 114 | hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
5b50e790 AF |
115 | int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); |
116 | int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
e62fbc54 AK |
117 | int ppc64_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, |
118 | CPUState *cpu, void *opaque); | |
119 | int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, | |
120 | int cpuid, void *opaque); | |
a90db158 AK |
121 | #ifndef CONFIG_USER_ONLY |
122 | extern const struct VMStateDescription vmstate_ppc_cpu; | |
98a8b524 AK |
123 | |
124 | typedef struct PPCTimebase { | |
125 | uint64_t guest_timebase; | |
126 | int64_t time_of_the_day_ns; | |
127 | } PPCTimebase; | |
128 | ||
129 | extern const struct VMStateDescription vmstate_ppc_timebase; | |
130 | ||
131 | #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \ | |
132 | .name = (stringify(_field)), \ | |
133 | .version_id = (_version), \ | |
134 | .size = sizeof(PPCTimebase), \ | |
135 | .vmsd = &vmstate_ppc_timebase, \ | |
136 | .flags = VMS_STRUCT, \ | |
137 | .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ | |
138 | } | |
a90db158 AK |
139 | #endif |
140 | ||
1d0cb67d | 141 | #endif |