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qemu-file: Add fast ftell code path
[qemu.git] / hw / pci / pci.c
CommitLineData
69b91039
FB		 1/*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5fafdf24 5 *
69b91039
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
c759b24f
MT		 24#include "hw/hw.h"
25#include "hw/pci/pci.h"
26#include "hw/pci/pci_bridge.h"
06aac7bd 27#include "hw/pci/pci_bus.h"
568f0690 28#include "hw/pci/pci_host.h"
83c9089e 29#include "monitor/monitor.h"
1422e32d 30#include "net/net.h"
9c17d615 31#include "sysemu/sysemu.h"
c759b24f 32#include "hw/loader.h"
1de7afc9 33#include "qemu/range.h"
79627472 34#include "qmp-commands.h"
7828d750 35#include "trace.h"
c759b24f
MT		 36#include "hw/pci/msi.h"
37#include "hw/pci/msix.h"
022c62cb 38#include "exec/address-spaces.h"
5e954943 39#include "hw/hotplug.h"
69b91039
FB		 40
41//#define DEBUG_PCI
d8d2e079 42#ifdef DEBUG_PCI
2e49d64a 43# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
d8d2e079
IY		 44#else
45# define PCI_DPRINTF(format, ...) do { } while (0)
46#endif
69b91039 47
10c4c98a 48static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
4f43c1ff 49static char *pcibus_get_dev_path(DeviceState *dev);
5e0259e7 50static char *pcibus_get_fw_dev_path(DeviceState *dev);
dcc20931 51static void pcibus_reset(BusState *qbus);
10c4c98a 52
3cb75a7c
PB		 53static Property pci_props[] = {
54 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
55 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
56 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
57 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
58 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
59 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
60 QEMU_PCI_CAP_SERR_BITNR, true),
61 DEFINE_PROP_END_OF_LIST()
62};
63
d2f69df7
BD		 64static const VMStateDescription vmstate_pcibus = {
65 .name = "PCIBUS",
66 .version_id = 1,
67 .minimum_version_id = 1,
d49805ae 68 .fields = (VMStateField[]) {
d2f69df7
BD		 69 VMSTATE_INT32_EQUAL(nirq, PCIBus),
70 VMSTATE_VARRAY_INT32(irq_count, PCIBus,
71 nirq, 0, vmstate_info_int32,
72 int32_t),
73 VMSTATE_END_OF_LIST()
74 }
75};
76
77static void pci_bus_realize(BusState *qbus, Error **errp)
78{
79 PCIBus *bus = PCI_BUS(qbus);
80
81 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
82}
83
84static void pci_bus_unrealize(BusState *qbus, Error **errp)
85{
86 PCIBus *bus = PCI_BUS(qbus);
87
88 vmstate_unregister(NULL, &vmstate_pcibus, bus);
89}
90
0d936928
AL		 91static void pci_bus_class_init(ObjectClass *klass, void *data)
92{
93 BusClass *k = BUS_CLASS(klass);
94
95 k->print_dev = pcibus_dev_print;
96 k->get_dev_path = pcibus_get_dev_path;
97 k->get_fw_dev_path = pcibus_get_fw_dev_path;
d2f69df7
BD		 98 k->realize = pci_bus_realize;
99 k->unrealize = pci_bus_unrealize;
0d936928
AL		 100 k->reset = pcibus_reset;
101}
102
103static const TypeInfo pci_bus_info = {
104 .name = TYPE_PCI_BUS,
105 .parent = TYPE_BUS,
106 .instance_size = sizeof(PCIBus),
107 .class_init = pci_bus_class_init,
30468f78 108};
69b91039 109
3a861c46
AW		 110static const TypeInfo pcie_bus_info = {
111 .name = TYPE_PCIE_BUS,
112 .parent = TYPE_PCI_BUS,
113};
114
d662210a 115static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
1941d19c 116static void pci_update_mappings(PCIDevice *d);
d98f08f5 117static void pci_irq_handler(void *opaque, int irq_num, int level);
ab85ceb1 118static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
230741dc 119static void pci_del_option_rom(PCIDevice *pdev);
1941d19c 120
d350d97d
AL		 121static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
122static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
e822a52a 123
7588e2b0 124static QLIST_HEAD(, PCIHostState) pci_host_bridges;
30468f78 125
b3b11697 126static int pci_bar(PCIDevice *d, int reg)
5330de09 127{
b3b11697
IY		 128 uint8_t type;
129
130 if (reg != PCI_ROM_SLOT)
131 return PCI_BASE_ADDRESS_0 + reg * 4;
132
133 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
134 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
5330de09
MT		 135}
136
d036bb21
MT		 137static inline int pci_irq_state(PCIDevice *d, int irq_num)
138{
139 return (d->irq_state >> irq_num) & 0x1;
140}
141
142static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
143{
144 d->irq_state &= ~(0x1 << irq_num);
145 d->irq_state |= level << irq_num;
146}
147
148static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
149{
150 PCIBus *bus;
151 for (;;) {
152 bus = pci_dev->bus;
153 irq_num = bus->map_irq(pci_dev, irq_num);
154 if (bus->set_irq)
155 break;
156 pci_dev = bus->parent_dev;
157 }
158 bus->irq_count[irq_num] += change;
159 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
160}
161
9ddf8437
IY		 162int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
163{
164 assert(irq_num >= 0);
165 assert(irq_num < bus->nirq);
166 return !!bus->irq_count[irq_num];
167}
168
f9bf77dd
MT		 169/* Update interrupt status bit in config space on interrupt
170 * state change. */
171static void pci_update_irq_status(PCIDevice *dev)
172{
173 if (dev->irq_state) {
174 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
175 } else {
176 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
177 }
178}
179
4c92325b
IY		 180void pci_device_deassert_intx(PCIDevice *dev)
181{
182 int i;
183 for (i = 0; i < PCI_NUM_PINS; ++i) {
d98f08f5 184 pci_irq_handler(dev, i, 0);
4c92325b
IY		 185 }
186}
187
dcc20931 188static void pci_do_device_reset(PCIDevice *dev)
5330de09 189{
c0b1905b 190 int r;
6fc4925b 191
4c92325b 192 pci_device_deassert_intx(dev);
58b59014
CR		 193 assert(dev->irq_state == 0);
194
ebabb67a 195 /* Clear all writable bits */
99443c21 196 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
f9aebe2e
MT		 197 pci_get_word(dev->wmask + PCI_COMMAND) |
198 pci_get_word(dev->w1cmask + PCI_COMMAND));
89d437df
IY		 199 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
200 pci_get_word(dev->wmask + PCI_STATUS) |
201 pci_get_word(dev->w1cmask + PCI_STATUS));
c0b1905b
MT		 202 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
203 dev->config[PCI_INTERRUPT_LINE] = 0x0;
204 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
71ebd6dc
IY		 205 PCIIORegion *region = &dev->io_regions[r];
206 if (!region->size) {
c0b1905b
MT		 207 continue;
208 }
71ebd6dc
IY		 209
210 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
211 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
212 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
213 } else {
214 pci_set_long(dev->config + pci_bar(dev, r), region->type);
215 }
c0b1905b
MT		 216 }
217 pci_update_mappings(dev);
cbd2d434
JK		 218
219 msi_reset(dev);
220 msix_reset(dev);
5330de09
MT		 221}
222
dcc20931
PB		 223/*
224 * This function is called on #RST and FLR.
225 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
226 */
227void pci_device_reset(PCIDevice *dev)
228{
229 qdev_reset_all(&dev->qdev);
230 pci_do_device_reset(dev);
231}
232
9bb33586
IY		 233/*
234 * Trigger pci bus reset under a given bus.
dcc20931
PB		 235 * Called via qbus_reset_all on RST# assert, after the devices
236 * have been reset qdev_reset_all-ed already.
9bb33586 237 */
dcc20931 238static void pcibus_reset(BusState *qbus)
6eaa6847 239{
81e3e75b 240 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
6eaa6847
GN		 241 int i;
242
5330de09
MT		 243 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
244 if (bus->devices[i]) {
dcc20931 245 pci_do_device_reset(bus->devices[i]);
5330de09 246 }
6eaa6847 247 }
9bb33586 248
9bdbbfc3
PB		 249 for (i = 0; i < bus->nirq; i++) {
250 assert(bus->irq_count[i] == 0);
251 }
9bb33586
IY		 252}
253
7588e2b0 254static void pci_host_bus_register(PCIBus *bus, DeviceState *parent)
e822a52a 255{
7588e2b0
DG		 256 PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent);
257
258 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
e822a52a
IY		 259}
260
1ef7a2a2 261PCIBus *pci_find_primary_bus(void)
e822a52a 262{
9bc47305 263 PCIBus *primary_bus = NULL;
7588e2b0 264 PCIHostState *host;
e822a52a 265
7588e2b0 266 QLIST_FOREACH(host, &pci_host_bridges, next) {
9bc47305
DG		 267 if (primary_bus) {
268 /* We have multiple root buses, refuse to select a primary */
269 return NULL;
e822a52a 270 }
9bc47305 271 primary_bus = host->bus;
e822a52a
IY		 272 }
273
9bc47305 274 return primary_bus;
e822a52a
IY		 275}
276
c473d18d 277PCIBus *pci_device_root_bus(const PCIDevice *d)
e075e788 278{
c473d18d 279 PCIBus *bus = d->bus;
e075e788 280
e075e788
IY		 281 while ((d = bus->parent_dev) != NULL) {
282 bus = d->bus;
283 }
284
c473d18d
DG		 285 return bus;
286}
287
568f0690 288const char *pci_root_bus_path(PCIDevice *dev)
c473d18d 289{
568f0690
DG		 290 PCIBus *rootbus = pci_device_root_bus(dev);
291 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
292 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
c473d18d 293
568f0690
DG		 294 assert(!rootbus->parent_dev);
295 assert(host_bridge->bus == rootbus);
296
297 if (hc->root_bus_path) {
298 return (*hc->root_bus_path)(host_bridge, rootbus);
e075e788
IY		 299 }
300
568f0690 301 return rootbus->qbus.name;
e075e788
IY		 302}
303
4fec6404 304static void pci_bus_init(PCIBus *bus, DeviceState *parent,
1e39101c 305 const char *name,
aee97b84
AK		 306 MemoryRegion *address_space_mem,
307 MemoryRegion *address_space_io,
1e39101c 308 uint8_t devfn_min)
30468f78 309{
6fa84913 310 assert(PCI_FUNC(devfn_min) == 0);
502a5395 311 bus->devfn_min = devfn_min;
5968eca3
AK		 312 bus->address_space_mem = address_space_mem;
313 bus->address_space_io = address_space_io;
e822a52a
IY		 314
315 /* host bridge */
316 QLIST_INIT(&bus->child);
2b8cc89a 317
7588e2b0 318 pci_host_bus_register(bus, parent);
21eea4b3
GH		 319}
320
8c0bf9e2
AW		 321bool pci_bus_is_express(PCIBus *bus)
322{
323 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
324}
325
0889464a
AW		 326bool pci_bus_is_root(PCIBus *bus)
327{
328 return !bus->parent_dev;
329}
330
dd301ca6 331void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
4fec6404
PB		 332 const char *name,
333 MemoryRegion *address_space_mem,
334 MemoryRegion *address_space_io,
60a0e443 335 uint8_t devfn_min, const char *typename)
4fec6404 336{
fb17dfe0 337 qbus_create_inplace(bus, bus_size, typename, parent, name);
4fec6404
PB		 338 pci_bus_init(bus, parent, name, address_space_mem,
339 address_space_io, devfn_min);
340}
341
1e39101c 342PCIBus *pci_bus_new(DeviceState *parent, const char *name,
aee97b84
AK		 343 MemoryRegion *address_space_mem,
344 MemoryRegion *address_space_io,
60a0e443 345 uint8_t devfn_min, const char *typename)
21eea4b3
GH		 346{
347 PCIBus *bus;
348
60a0e443 349 bus = PCI_BUS(qbus_create(typename, parent, name));
4fec6404
PB		 350 pci_bus_init(bus, parent, name, address_space_mem,
351 address_space_io, devfn_min);
21eea4b3
GH		 352 return bus;
353}
354
355void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
356 void *irq_opaque, int nirq)
357{
358 bus->set_irq = set_irq;
359 bus->map_irq = map_irq;
360 bus->irq_opaque = irq_opaque;
361 bus->nirq = nirq;
7267c094 362 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
21eea4b3
GH		 363}
364
365PCIBus *pci_register_bus(DeviceState *parent, const char *name,
366 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
1e39101c 367 void *irq_opaque,
aee97b84
AK		 368 MemoryRegion *address_space_mem,
369 MemoryRegion *address_space_io,
60a0e443 370 uint8_t devfn_min, int nirq, const char *typename)
21eea4b3
GH		 371{
372 PCIBus *bus;
373
aee97b84 374 bus = pci_bus_new(parent, name, address_space_mem,
60a0e443 375 address_space_io, devfn_min, typename);
21eea4b3 376 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
30468f78
FB		 377 return bus;
378}
69b91039 379
502a5395
PB		 380int pci_bus_num(PCIBus *s)
381{
0889464a 382 if (pci_bus_is_root(s))
e94ff650
IY		 383 return 0; /* pci host bridge */
384 return s->parent_dev->config[PCI_SECONDARY_BUS];
502a5395
PB		 385}
386
73534f2f 387static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
30ca2aab 388{
73534f2f 389 PCIDevice *s = container_of(pv, PCIDevice, config);
e78e9ae4 390 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
a9f49946 391 uint8_t *config;
52fc1d83
AZ		 392 int i;
393
a9f49946 394 assert(size == pci_config_size(s));
7267c094 395 config = g_malloc(size);
a9f49946
IY		 396
397 qemu_get_buffer(f, config, size);
398 for (i = 0; i < size; ++i) {
f9aebe2e
MT		 399 if ((config[i] ^ s->config[i]) &
400 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
7267c094 401 g_free(config);
bd4b65ee 402 return -EINVAL;
a9f49946
IY		 403 }
404 }
405 memcpy(s->config, config, size);
bd4b65ee 406
1941d19c 407 pci_update_mappings(s);
e78e9ae4 408 if (pc->is_bridge) {
f055e96b 409 PCIBridge *b = PCI_BRIDGE(s);
e78e9ae4
DK		 410 pci_bridge_update_mappings(b);
411 }
52fc1d83 412
4ea375bf
GH		 413 memory_region_set_enabled(&s->bus_master_enable_region,
414 pci_get_word(s->config + PCI_COMMAND)
415 & PCI_COMMAND_MASTER);
416
7267c094 417 g_free(config);
30ca2aab
FB		 418 return 0;
419}
420
73534f2f 421/* just put buffer */
84e2e3eb 422static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
73534f2f 423{
dbe73d7f 424 const uint8_t **v = pv;
a9f49946 425 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
dbe73d7f 426 qemu_put_buffer(f, *v, size);
73534f2f
JQ		 427}
428
429static VMStateInfo vmstate_info_pci_config = {
430 .name = "pci config",
431 .get = get_pci_config_device,
432 .put = put_pci_config_device,
433};
434
d036bb21
MT		 435static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
436{
c3f8f611 437 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
d036bb21
MT		 438 uint32_t irq_state[PCI_NUM_PINS];
439 int i;
440 for (i = 0; i < PCI_NUM_PINS; ++i) {
441 irq_state[i] = qemu_get_be32(f);
442 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
443 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
444 irq_state[i]);
445 return -EINVAL;
446 }
447 }
448
449 for (i = 0; i < PCI_NUM_PINS; ++i) {
450 pci_set_irq_state(s, i, irq_state[i]);
451 }
452
453 return 0;
454}
455
456static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
457{
458 int i;
c3f8f611 459 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
d036bb21
MT		 460
461 for (i = 0; i < PCI_NUM_PINS; ++i) {
462 qemu_put_be32(f, pci_irq_state(s, i));
463 }
464}
465
466static VMStateInfo vmstate_info_pci_irq_state = {
467 .name = "pci irq state",
468 .get = get_pci_irq_state,
469 .put = put_pci_irq_state,
470};
471
73534f2f
JQ		 472const VMStateDescription vmstate_pci_device = {
473 .name = "PCIDevice",
474 .version_id = 2,
475 .minimum_version_id = 1,
d49805ae 476 .fields = (VMStateField[]) {
3476436a 477 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
a9f49946
IY		 478 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
479 vmstate_info_pci_config,
480 PCI_CONFIG_SPACE_SIZE),
d036bb21
MT		 481 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
482 vmstate_info_pci_irq_state,
483 PCI_NUM_PINS * sizeof(int32_t)),
a9f49946
IY		 484 VMSTATE_END_OF_LIST()
485 }
486};
487
488const VMStateDescription vmstate_pcie_device = {
1de53459 489 .name = "PCIEDevice",
a9f49946
IY		 490 .version_id = 2,
491 .minimum_version_id = 1,
d49805ae 492 .fields = (VMStateField[]) {
3476436a 493 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
a9f49946
IY		 494 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
495 vmstate_info_pci_config,
496 PCIE_CONFIG_SPACE_SIZE),
d036bb21
MT		 497 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
498 vmstate_info_pci_irq_state,
499 PCI_NUM_PINS * sizeof(int32_t)),
73534f2f
JQ		 500 VMSTATE_END_OF_LIST()
501 }
502};
503
a9f49946
IY		 504static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
505{
506 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
507}
508
73534f2f
JQ		 509void pci_device_save(PCIDevice *s, QEMUFile *f)
510{
f9bf77dd
MT		 511 /* Clear interrupt status bit: it is implicit
512 * in irq_state which we are saving.
513 * This makes us compatible with old devices
514 * which never set or clear this bit. */
515 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
a9f49946 516 vmstate_save_state(f, pci_get_vmstate(s), s);
f9bf77dd
MT		 517 /* Restore the interrupt status bit. */
518 pci_update_irq_status(s);
73534f2f
JQ		 519}
520
521int pci_device_load(PCIDevice *s, QEMUFile *f)
522{
f9bf77dd
MT		 523 int ret;
524 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
525 /* Restore the interrupt status bit. */
526 pci_update_irq_status(s);
527 return ret;
73534f2f
JQ		 528}
529
5e434f4e 530static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
d350d97d 531{
5e434f4e
IY		 532 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
533 pci_default_sub_vendor_id);
534 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
535 pci_default_sub_device_id);
d350d97d
AL		 536}
537
880345c4 538/*
43c945f1
IY		 539 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
540 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
880345c4 541 */
6ac363b5 542int pci_parse_devaddr(const char *addr, int *domp, int *busp,
43c945f1 543 unsigned int *slotp, unsigned int *funcp)
880345c4
AL		 544{
545 const char *p;
546 char *e;
547 unsigned long val;
548 unsigned long dom = 0, bus = 0;
43c945f1
IY		 549 unsigned int slot = 0;
550 unsigned int func = 0;
880345c4
AL		 551
552 p = addr;
553 val = strtoul(p, &e, 16);
554 if (e == p)
555 return -1;
556 if (*e == ':') {
557 bus = val;
558 p = e + 1;
559 val = strtoul(p, &e, 16);
560 if (e == p)
561 return -1;
562 if (*e == ':') {
563 dom = bus;
564 bus = val;
565 p = e + 1;
566 val = strtoul(p, &e, 16);
567 if (e == p)
568 return -1;
569 }
570 }
571
880345c4
AL		 572 slot = val;
573
43c945f1
IY		 574 if (funcp != NULL) {
575 if (*e != '.')
576 return -1;
577
578 p = e + 1;
579 val = strtoul(p, &e, 16);
580 if (e == p)
581 return -1;
582
583 func = val;
584 }
585
586 /* if funcp == NULL func is 0 */
587 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
588 return -1;
589
880345c4
AL		 590 if (*e)
591 return -1;
592
880345c4
AL		 593 *domp = dom;
594 *busp = bus;
595 *slotp = slot;
43c945f1
IY		 596 if (funcp != NULL)
597 *funcp = func;
880345c4
AL		 598 return 0;
599}
600
85c6e4fa 601PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr)
5607c388
MA		 602{
603 int dom, bus;
604 unsigned slot;
605
1ef7a2a2
DG		 606 if (!root) {
607 fprintf(stderr, "No primary PCI bus\n");
608 return NULL;
609 }
610
b645000e
S		 611 assert(!root->parent_dev);
612
5607c388
MA		 613 if (!devaddr) {
614 *devfnp = -1;
1ef7a2a2 615 return pci_find_bus_nr(root, 0);
5607c388
MA		 616 }
617
43c945f1 618 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
5607c388
MA		 619 return NULL;
620 }
621
1ef7a2a2
DG		 622 if (dom != 0) {
623 fprintf(stderr, "No support for non-zero PCI domains\n");
624 return NULL;
625 }
626
6ff534b6 627 *devfnp = PCI_DEVFN(slot, 0);
1ef7a2a2 628 return pci_find_bus_nr(root, bus);
5607c388
MA		 629}
630
bd4b65ee
MT		 631static void pci_init_cmask(PCIDevice *dev)
632{
633 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
634 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
635 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
636 dev->cmask[PCI_REVISION_ID] = 0xff;
637 dev->cmask[PCI_CLASS_PROG] = 0xff;
638 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
639 dev->cmask[PCI_HEADER_TYPE] = 0xff;
640 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
641}
642
b7ee1603
MT		 643static void pci_init_wmask(PCIDevice *dev)
644{
a9f49946
IY		 645 int config_size = pci_config_size(dev);
646
b7ee1603
MT		 647 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
648 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
67a51b48 649 pci_set_word(dev->wmask + PCI_COMMAND,
a7b15a5c
MT		 650 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
651 PCI_COMMAND_INTX_DISABLE);
b1aeb926
IY		 652 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
653 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
654 }
3e21ffc9
IY		 655
656 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
657 config_size - PCI_CONFIG_HEADER_SIZE);
b7ee1603
MT		 658}
659
89d437df
IY		 660static void pci_init_w1cmask(PCIDevice *dev)
661{
662 /*
f6bdfcc9 663 * Note: It's okay to set w1cmask even for readonly bits as
89d437df
IY		 664 * long as their value is hardwired to 0.
665 */
666 pci_set_word(dev->w1cmask + PCI_STATUS,
667 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
668 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
669 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
670}
671
d5f27e88 672static void pci_init_mask_bridge(PCIDevice *d)
fb231628
IY		 673{
674 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
675 PCI_SEC_LETENCY_TIMER */
676 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
677
678 /* base and limit */
679 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
680 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
681 pci_set_word(d->wmask + PCI_MEMORY_BASE,
682 PCI_MEMORY_RANGE_MASK & 0xffff);
683 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
684 PCI_MEMORY_RANGE_MASK & 0xffff);
685 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
686 PCI_PREF_RANGE_MASK & 0xffff);
687 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
688 PCI_PREF_RANGE_MASK & 0xffff);
689
690 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
691 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
692
d5f27e88 693 /* Supported memory and i/o types */
68917102
MT		 694 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
695 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
d5f27e88
MT		 696 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
697 PCI_PREF_RANGE_TYPE_64);
698 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
699 PCI_PREF_RANGE_TYPE_64);
700
45eb768c
MT		 701 /*
702 * TODO: Bridges default to 10-bit VGA decoding but we currently only
703 * implement 16-bit decoding (no alias support).
704 */
f6bdfcc9
MT		 705 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
706 PCI_BRIDGE_CTL_PARITY |
707 PCI_BRIDGE_CTL_SERR |
708 PCI_BRIDGE_CTL_ISA |
709 PCI_BRIDGE_CTL_VGA |
710 PCI_BRIDGE_CTL_VGA_16BIT |
711 PCI_BRIDGE_CTL_MASTER_ABORT |
712 PCI_BRIDGE_CTL_BUS_RESET |
713 PCI_BRIDGE_CTL_FAST_BACK |
714 PCI_BRIDGE_CTL_DISCARD |
715 PCI_BRIDGE_CTL_SEC_DISCARD |
f6bdfcc9
MT		 716 PCI_BRIDGE_CTL_DISCARD_SERR);
717 /* Below does not do anything as we never set this bit, put here for
718 * completeness. */
719 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
720 PCI_BRIDGE_CTL_DISCARD_STATUS);
d5f27e88 721 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
15ab7a75 722 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
d5f27e88
MT		 723 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
724 PCI_PREF_RANGE_TYPE_MASK);
15ab7a75
MT		 725 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
726 PCI_PREF_RANGE_TYPE_MASK);
fb231628
IY		 727}
728
6eab3de1
IY		 729static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
730{
731 uint8_t slot = PCI_SLOT(dev->devfn);
732 uint8_t func;
733
734 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
735 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
736 }
737
738 /*
b0cd712c 739 * multifunction bit is interpreted in two ways as follows.
6eab3de1
IY		 740 * - all functions must set the bit to 1.
741 * Example: Intel X53
742 * - function 0 must set the bit, but the rest function (> 0)
743 * is allowed to leave the bit to 0.
744 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
745 *
746 * So OS (at least Linux) checks the bit of only function 0,
747 * and doesn't see the bit of function > 0.
748 *
749 * The below check allows both interpretation.
750 */
751 if (PCI_FUNC(dev->devfn)) {
752 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
753 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
754 /* function 0 should set multifunction bit */
755 error_report("PCI: single function device can't be populated "
756 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
757 return -1;
758 }
759 return 0;
760 }
761
762 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
763 return 0;
764 }
765 /* function 0 indicates single function, so function > 0 must be NULL */
766 for (func = 1; func < PCI_FUNC_MAX; ++func) {
767 if (bus->devices[PCI_DEVFN(slot, func)]) {
768 error_report("PCI: %x.0 indicates single function, "
769 "but %x.%x is already populated.",
770 slot, slot, func);
771 return -1;
772 }
773 }
774 return 0;
775}
776
a9f49946
IY		 777static void pci_config_alloc(PCIDevice *pci_dev)
778{
779 int config_size = pci_config_size(pci_dev);
780
7267c094
AL		 781 pci_dev->config = g_malloc0(config_size);
782 pci_dev->cmask = g_malloc0(config_size);
783 pci_dev->wmask = g_malloc0(config_size);
784 pci_dev->w1cmask = g_malloc0(config_size);
785 pci_dev->used = g_malloc0(config_size);
a9f49946
IY		 786}
787
788static void pci_config_free(PCIDevice *pci_dev)
789{
7267c094
AL		 790 g_free(pci_dev->config);
791 g_free(pci_dev->cmask);
792 g_free(pci_dev->wmask);
793 g_free(pci_dev->w1cmask);
794 g_free(pci_dev->used);
a9f49946
IY		 795}
796
30607764
MA		 797static void do_pci_unregister_device(PCIDevice *pci_dev)
798{
799 pci_dev->bus->devices[pci_dev->devfn] = NULL;
800 pci_config_free(pci_dev);
801
802 address_space_destroy(&pci_dev->bus_master_as);
30607764
MA		 803}
804
69b91039 805/* -1 for devfn means auto assign */
6b1b92d3 806static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
40021f08 807 const char *name, int devfn)
69b91039 808{
40021f08
AL		 809 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
810 PCIConfigReadFunc *config_read = pc->config_read;
811 PCIConfigWriteFunc *config_write = pc->config_write;
e00387d5 812 AddressSpace *dma_as;
113f89df 813
69b91039 814 if (devfn < 0) {
b47b0706 815 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
6fa84913 816 devfn += PCI_FUNC_MAX) {
30468f78 817 if (!bus->devices[devfn])
69b91039
FB		 818 goto found;
819 }
3709c1b7 820 error_report("PCI: no slot/function available for %s, all in use", name);
09e3acc6 821 return NULL;
69b91039 822 found: ;
07b7d053 823 } else if (bus->devices[devfn]) {
3709c1b7
DB		 824 error_report("PCI: slot %d function %d not available for %s, in use by %s",
825 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
09e3acc6 826 return NULL;
69b91039 827 }
e00387d5 828
30468f78 829 pci_dev->bus = bus;
efc8188e 830 pci_dev->devfn = devfn;
9eda7d37 831 dma_as = pci_device_iommu_address_space(pci_dev);
24addbc7 832
40c5dce9
PB		 833 memory_region_init_alias(&pci_dev->bus_master_enable_region,
834 OBJECT(pci_dev), "bus master",
e00387d5
AK		 835 dma_as->root, 0, memory_region_size(dma_as->root));
836 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
7dca8043
AK		 837 address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region,
838 name);
e00387d5 839
69b91039 840 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
d036bb21 841 pci_dev->irq_state = 0;
a9f49946 842 pci_config_alloc(pci_dev);
fb231628 843
40021f08
AL		 844 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
845 pci_config_set_device_id(pci_dev->config, pc->device_id);
846 pci_config_set_revision(pci_dev->config, pc->revision);
847 pci_config_set_class(pci_dev->config, pc->class_id);
113f89df 848
40021f08
AL		 849 if (!pc->is_bridge) {
850 if (pc->subsystem_vendor_id || pc->subsystem_id) {
113f89df 851 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
40021f08 852 pc->subsystem_vendor_id);
113f89df 853 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
40021f08 854 pc->subsystem_id);
113f89df
IY		 855 } else {
856 pci_set_default_subsystem_id(pci_dev);
857 }
858 } else {
859 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
40021f08
AL		 860 assert(!pc->subsystem_vendor_id);
861 assert(!pc->subsystem_id);
fb231628 862 }
bd4b65ee 863 pci_init_cmask(pci_dev);
b7ee1603 864 pci_init_wmask(pci_dev);
89d437df 865 pci_init_w1cmask(pci_dev);
40021f08 866 if (pc->is_bridge) {
d5f27e88 867 pci_init_mask_bridge(pci_dev);
fb231628 868 }
6eab3de1 869 if (pci_init_multifunction(bus, pci_dev)) {
30607764 870 do_pci_unregister_device(pci_dev);
6eab3de1
IY		 871 return NULL;
872 }
0ac32c83
FB		 873
874 if (!config_read)
875 config_read = pci_default_read_config;
876 if (!config_write)
877 config_write = pci_default_write_config;
69b91039
FB		 878 pci_dev->config_read = config_read;
879 pci_dev->config_write = config_write;
30468f78 880 bus->devices[devfn] = pci_dev;
f16c4abf 881 pci_dev->version_id = 2; /* Current pci device vmstate version */
69b91039
FB		 882 return pci_dev;
883}
884
5851e08c
AL		 885static void pci_unregister_io_regions(PCIDevice *pci_dev)
886{
887 PCIIORegion *r;
888 int i;
889
890 for(i = 0; i < PCI_NUM_REGIONS; i++) {
891 r = &pci_dev->io_regions[i];
182f9c8a 892 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
5851e08c 893 continue;
03952339 894 memory_region_del_subregion(r->address_space, r->memory);
5851e08c 895 }
e01fd687
AW		 896
897 pci_unregister_vga(pci_dev);
5851e08c
AL		 898}
899
a36a344d 900static int pci_unregister_device(DeviceState *dev)
5851e08c 901{
40021f08
AL		 902 PCIDevice *pci_dev = PCI_DEVICE(dev);
903 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
5851e08c
AL		 904
905 pci_unregister_io_regions(pci_dev);
230741dc 906 pci_del_option_rom(pci_dev);
7cf1b0fd 907
f90c2bcd
AW		 908 if (pc->exit) {
909 pc->exit(pci_dev);
910 }
5851e08c 911
925fe64a 912 do_pci_unregister_device(pci_dev);
5851e08c
AL		 913 return 0;
914}
915
e824b2cc
AK		 916void pci_register_bar(PCIDevice *pci_dev, int region_num,
917 uint8_t type, MemoryRegion *memory)
69b91039
FB		 918{
919 PCIIORegion *r;
d7ce493a 920 uint32_t addr;
5a9ff381 921 uint64_t wmask;
cfc0be25 922 pcibus_t size = memory_region_size(memory);
a4c20c6a 923
2bbb9c2f
IY		 924 assert(region_num >= 0);
925 assert(region_num < PCI_NUM_REGIONS);
a4c20c6a
AL		 926 if (size & (size-1)) {
927 fprintf(stderr, "ERROR: PCI region size must be pow2 "
89e8b13c 928 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
a4c20c6a
AL		 929 exit(1);
930 }
931
69b91039 932 r = &pci_dev->io_regions[region_num];
182f9c8a 933 r->addr = PCI_BAR_UNMAPPED;
69b91039
FB		 934 r->size = size;
935 r->type = type;
79ff8cb0 936 r->memory = NULL;
b7ee1603
MT		 937
938 wmask = ~(size - 1);
b3b11697 939 addr = pci_bar(pci_dev, region_num);
d7ce493a 940 if (region_num == PCI_ROM_SLOT) {
ebabb67a 941 /* ROM enable bit is writable */
5330de09 942 wmask |= PCI_ROM_ADDRESS_ENABLE;
d7ce493a 943 }
b0ff8eb2 944 pci_set_long(pci_dev->config + addr, type);
14421258
IY		 945 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
946 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
947 pci_set_quad(pci_dev->wmask + addr, wmask);
948 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
949 } else {
950 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
951 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
952 }
79ff8cb0 953 pci_dev->io_regions[region_num].memory = memory;
5968eca3 954 pci_dev->io_regions[region_num].address_space
cfc0be25 955 = type & PCI_BASE_ADDRESS_SPACE_IO
5968eca3
AK		 956 ? pci_dev->bus->address_space_io
957 : pci_dev->bus->address_space_mem;
79ff8cb0
AK		 958}
959
e01fd687
AW		 960static void pci_update_vga(PCIDevice *pci_dev)
961{
962 uint16_t cmd;
963
964 if (!pci_dev->has_vga) {
965 return;
966 }
967
968 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
969
970 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
971 cmd & PCI_COMMAND_MEMORY);
972 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
973 cmd & PCI_COMMAND_IO);
974 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
975 cmd & PCI_COMMAND_IO);
976}
977
978void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
979 MemoryRegion *io_lo, MemoryRegion *io_hi)
980{
981 assert(!pci_dev->has_vga);
982
983 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
984 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
985 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem,
986 QEMU_PCI_VGA_MEM_BASE, mem, 1);
987
988 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
989 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
990 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
991 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
992
993 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
994 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
995 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
996 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
997 pci_dev->has_vga = true;
998
999 pci_update_vga(pci_dev);
1000}
1001
1002void pci_unregister_vga(PCIDevice *pci_dev)
1003{
1004 if (!pci_dev->has_vga) {
1005 return;
1006 }
1007
1008 memory_region_del_subregion(pci_dev->bus->address_space_mem,
1009 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1010 memory_region_del_subregion(pci_dev->bus->address_space_io,
1011 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1012 memory_region_del_subregion(pci_dev->bus->address_space_io,
1013 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1014 pci_dev->has_vga = false;
1015}
1016
16a96f28
AK		 1017pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1018{
1019 return pci_dev->io_regions[region_num].addr;
1020}
1021
876a350d
MT		 1022static pcibus_t pci_bar_address(PCIDevice *d,
1023 int reg, uint8_t type, pcibus_t size)
1024{
1025 pcibus_t new_addr, last_addr;
1026 int bar = pci_bar(d, reg);
1027 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1028
1029 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1030 if (!(cmd & PCI_COMMAND_IO)) {
1031 return PCI_BAR_UNMAPPED;
1032 }
1033 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1034 last_addr = new_addr + size - 1;
9f1a029a
HP		 1035 /* Check if 32 bit BAR wraps around explicitly.
1036 * TODO: make priorities correct and remove this work around.
1037 */
1038 if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX) {
876a350d
MT		 1039 return PCI_BAR_UNMAPPED;
1040 }
1041 return new_addr;
1042 }
1043
1044 if (!(cmd & PCI_COMMAND_MEMORY)) {
1045 return PCI_BAR_UNMAPPED;
1046 }
1047 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1048 new_addr = pci_get_quad(d->config + bar);
1049 } else {
1050 new_addr = pci_get_long(d->config + bar);
1051 }
1052 /* the ROM slot has a specific enable bit */
1053 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1054 return PCI_BAR_UNMAPPED;
1055 }
1056 new_addr &= ~(size - 1);
1057 last_addr = new_addr + size - 1;
1058 /* NOTE: we do not support wrapping */
1059 /* XXX: as we cannot support really dynamic
1060 mappings, we handle specific values as invalid
1061 mappings. */
1062 if (last_addr <= new_addr || new_addr == 0 ||
1063 last_addr == PCI_BAR_UNMAPPED) {
1064 return PCI_BAR_UNMAPPED;
1065 }
1066
1067 /* Now pcibus_t is 64bit.
1068 * Check if 32 bit BAR wraps around explicitly.
1069 * Without this, PC ide doesn't work well.
1070 * TODO: remove this work around.
1071 */
1072 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1073 return PCI_BAR_UNMAPPED;
1074 }
1075
1076 /*
1077 * OS is allowed to set BAR beyond its addressable
1078 * bits. For example, 32 bit OS can set 64bit bar
1079 * to >4G. Check it. TODO: we might need to support
1080 * it in the future for e.g. PAE.
1081 */
a8170e5e 1082 if (last_addr >= HWADDR_MAX) {
876a350d
MT		 1083 return PCI_BAR_UNMAPPED;
1084 }
1085
1086 return new_addr;
1087}
1088
0ac32c83
FB		 1089static void pci_update_mappings(PCIDevice *d)
1090{
1091 PCIIORegion *r;
876a350d 1092 int i;
7df32ca0 1093 pcibus_t new_addr;
3b46e624 1094
8a8696a3 1095 for(i = 0; i < PCI_NUM_REGIONS; i++) {
0ac32c83 1096 r = &d->io_regions[i];
a9688570
IY		 1097
1098 /* this region isn't registered */
ec503442 1099 if (!r->size)
a9688570
IY		 1100 continue;
1101
876a350d 1102 new_addr = pci_bar_address(d, i, r->type, r->size);
a9688570
IY		 1103
1104 /* This bar isn't changed */
7df32ca0 1105 if (new_addr == r->addr)
a9688570
IY		 1106 continue;
1107
1108 /* now do the real mapping */
1109 if (r->addr != PCI_BAR_UNMAPPED) {
7828d750
DK		 1110 trace_pci_update_mappings_del(d, pci_bus_num(d->bus),
1111 PCI_FUNC(d->devfn),
1112 PCI_SLOT(d->devfn),
1113 i, r->addr, r->size);
03952339 1114 memory_region_del_subregion(r->address_space, r->memory);
0ac32c83 1115 }
a9688570
IY		 1116 r->addr = new_addr;
1117 if (r->addr != PCI_BAR_UNMAPPED) {
7828d750
DK		 1118 trace_pci_update_mappings_add(d, pci_bus_num(d->bus),
1119 PCI_FUNC(d->devfn),
1120 PCI_SLOT(d->devfn),
1121 i, r->addr, r->size);
8b881e77
AK		 1122 memory_region_add_subregion_overlap(r->address_space,
1123 r->addr, r->memory, 1);
a9688570 1124 }
0ac32c83 1125 }
e01fd687
AW		 1126
1127 pci_update_vga(d);
0ac32c83
FB		 1128}
1129
a7b15a5c
MT		 1130static inline int pci_irq_disabled(PCIDevice *d)
1131{
1132 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1133}
1134
1135/* Called after interrupt disabled field update in config space,
1136 * assert/deassert interrupts if necessary.
1137 * Gets original interrupt disable bit value (before update). */
1138static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1139{
1140 int i, disabled = pci_irq_disabled(d);
1141 if (disabled == was_irq_disabled)
1142 return;
1143 for (i = 0; i < PCI_NUM_PINS; ++i) {
1144 int state = pci_irq_state(d, i);
1145 pci_change_irq_level(d, i, disabled ? -state : state);
1146 }
1147}
1148
5fafdf24 1149uint32_t pci_default_read_config(PCIDevice *d,
0ac32c83 1150 uint32_t address, int len)
69b91039 1151{
5029fe12 1152 uint32_t val = 0;
42e4126b 1153
5029fe12
IY		 1154 memcpy(&val, d->config + address, len);
1155 return le32_to_cpu(val);
0ac32c83
FB		 1156}
1157
d7efb7e0 1158void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
0ac32c83 1159{
a7b15a5c 1160 int i, was_irq_disabled = pci_irq_disabled(d);
d7efb7e0 1161 uint32_t val = val_in;
0ac32c83 1162
42e4126b 1163 for (i = 0; i < l; val >>= 8, ++i) {
91011d4f 1164 uint8_t wmask = d->wmask[addr + i];
92ba5f51
IY		 1165 uint8_t w1cmask = d->w1cmask[addr + i];
1166 assert(!(wmask & w1cmask));
91011d4f 1167 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
92ba5f51 1168 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
0ac32c83 1169 }
260c0cd3 1170 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
edb00035
IY		 1171 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1172 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
260c0cd3 1173 range_covers_byte(addr, l, PCI_COMMAND))
0ac32c83 1174 pci_update_mappings(d);
a7b15a5c 1175
1c380f94 1176 if (range_covers_byte(addr, l, PCI_COMMAND)) {
a7b15a5c 1177 pci_update_irq_disabled(d, was_irq_disabled);
1c380f94
AK		 1178 memory_region_set_enabled(&d->bus_master_enable_region,
1179 pci_get_word(d->config + PCI_COMMAND)
1180 & PCI_COMMAND_MASTER);
1181 }
95d65800 1182
d7efb7e0
KO		 1183 msi_write_config(d, addr, val_in, l);
1184 msix_write_config(d, addr, val_in, l);
69b91039
FB		 1185}
1186
502a5395
PB		 1187/***********************************************************/
1188/* generic PCI irq support */
30468f78 1189
502a5395 1190/* 0 <= irq_num <= 3. level must be 0 or 1 */
d98f08f5 1191static void pci_irq_handler(void *opaque, int irq_num, int level)
69b91039 1192{
a60380a5 1193 PCIDevice *pci_dev = opaque;
80b3ada7 1194 int change;
3b46e624 1195
d036bb21 1196 change = level - pci_irq_state(pci_dev, irq_num);
80b3ada7
PB		 1197 if (!change)
1198 return;
d2b59317 1199
d036bb21 1200 pci_set_irq_state(pci_dev, irq_num, level);
f9bf77dd 1201 pci_update_irq_status(pci_dev);
a7b15a5c
MT		 1202 if (pci_irq_disabled(pci_dev))
1203 return;
d036bb21 1204 pci_change_irq_level(pci_dev, irq_num, change);
69b91039
FB		 1205}
1206
d98f08f5
MA		 1207static inline int pci_intx(PCIDevice *pci_dev)
1208{
1209 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1210}
1211
1212qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1213{
1214 int intx = pci_intx(pci_dev);
1215
1216 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1217}
1218
1219void pci_set_irq(PCIDevice *pci_dev, int level)
1220{
1221 int intx = pci_intx(pci_dev);
1222 pci_irq_handler(pci_dev, intx, level);
1223}
1224
3afa9bb4
MT		 1225/* Special hooks used by device assignment */
1226void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1227{
0889464a 1228 assert(pci_bus_is_root(bus));
3afa9bb4
MT		 1229 bus->route_intx_to_irq = route_intx_to_irq;
1230}
1231
1232PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1233{
1234 PCIBus *bus;
1235
1236 do {
1237 bus = dev->bus;
1238 pin = bus->map_irq(dev, pin);
1239 dev = bus->parent_dev;
1240 } while (dev);
05c0621e
AW		 1241
1242 if (!bus->route_intx_to_irq) {
312fd5f2 1243 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
05c0621e
AW		 1244 object_get_typename(OBJECT(bus->qbus.parent)));
1245 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1246 }
1247
3afa9bb4 1248 return bus->route_intx_to_irq(bus->irq_opaque, pin);
0ae16251
JK		 1249}
1250
d6e65d54
AW		 1251bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1252{
1253 return old->mode != new->mode || old->irq != new->irq;
1254}
1255
0ae16251
JK		 1256void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1257{
1258 PCIDevice *dev;
1259 PCIBus *sec;
1260 int i;
1261
1262 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1263 dev = bus->devices[i];
1264 if (dev && dev->intx_routing_notifier) {
1265 dev->intx_routing_notifier(dev);
1266 }
e5368f0d
AW		 1267 }
1268
1269 QLIST_FOREACH(sec, &bus->child, sibling) {
1270 pci_bus_fire_intx_routing_notifier(sec);
0ae16251
JK		 1271 }
1272}
1273
1274void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1275 PCIINTxRoutingNotifier notifier)
1276{
1277 dev->intx_routing_notifier = notifier;
69b91039
FB		 1278}
1279
91e56159
IY		 1280/*
1281 * PCI-to-PCI bridge specification
1282 * 9.1: Interrupt routing. Table 9-1
1283 *
1284 * the PCI Express Base Specification, Revision 2.1
1285 * 2.2.8.1: INTx interrutp signaling - Rules
1286 * the Implementation Note
1287 * Table 2-20
1288 */
1289/*
1290 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1291 * 0-origin unlike PCI interrupt pin register.
1292 */
1293int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1294{
1295 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
1296}
1297
502a5395
PB		 1298/***********************************************************/
1299/* monitor info on PCI */
0ac32c83 1300
6650ee6d
PB		 1301typedef struct {
1302 uint16_t class;
1303 const char *desc;
5e0259e7
GN		 1304 const char *fw_name;
1305 uint16_t fw_ign_bits;
6650ee6d
PB		 1306} pci_class_desc;
1307
09bc878a 1308static const pci_class_desc pci_class_descriptions[] =
6650ee6d 1309{
5e0259e7
GN		 1310 { 0x0001, "VGA controller", "display"},
1311 { 0x0100, "SCSI controller", "scsi"},
1312 { 0x0101, "IDE controller", "ide"},
1313 { 0x0102, "Floppy controller", "fdc"},
1314 { 0x0103, "IPI controller", "ipi"},
1315 { 0x0104, "RAID controller", "raid"},
dcb5b19a
TS		 1316 { 0x0106, "SATA controller"},
1317 { 0x0107, "SAS controller"},
1318 { 0x0180, "Storage controller"},
5e0259e7
GN		 1319 { 0x0200, "Ethernet controller", "ethernet"},
1320 { 0x0201, "Token Ring controller", "token-ring"},
1321 { 0x0202, "FDDI controller", "fddi"},
1322 { 0x0203, "ATM controller", "atm"},
dcb5b19a 1323 { 0x0280, "Network controller"},
5e0259e7 1324 { 0x0300, "VGA controller", "display", 0x00ff},
dcb5b19a
TS		 1325 { 0x0301, "XGA controller"},
1326 { 0x0302, "3D controller"},
1327 { 0x0380, "Display controller"},
5e0259e7
GN		 1328 { 0x0400, "Video controller", "video"},
1329 { 0x0401, "Audio controller", "sound"},
dcb5b19a 1330 { 0x0402, "Phone"},
602ef4d9 1331 { 0x0403, "Audio controller", "sound"},
dcb5b19a 1332 { 0x0480, "Multimedia controller"},
5e0259e7
GN		 1333 { 0x0500, "RAM controller", "memory"},
1334 { 0x0501, "Flash controller", "flash"},
dcb5b19a 1335 { 0x0580, "Memory controller"},
5e0259e7
GN		 1336 { 0x0600, "Host bridge", "host"},
1337 { 0x0601, "ISA bridge", "isa"},
1338 { 0x0602, "EISA bridge", "eisa"},
1339 { 0x0603, "MC bridge", "mca"},
4c41425d 1340 { 0x0604, "PCI bridge", "pci-bridge"},
5e0259e7
GN		 1341 { 0x0605, "PCMCIA bridge", "pcmcia"},
1342 { 0x0606, "NUBUS bridge", "nubus"},
1343 { 0x0607, "CARDBUS bridge", "cardbus"},
dcb5b19a
TS		 1344 { 0x0608, "RACEWAY bridge"},
1345 { 0x0680, "Bridge"},
5e0259e7
GN		 1346 { 0x0700, "Serial port", "serial"},
1347 { 0x0701, "Parallel port", "parallel"},
1348 { 0x0800, "Interrupt controller", "interrupt-controller"},
1349 { 0x0801, "DMA controller", "dma-controller"},
1350 { 0x0802, "Timer", "timer"},
1351 { 0x0803, "RTC", "rtc"},
1352 { 0x0900, "Keyboard", "keyboard"},
1353 { 0x0901, "Pen", "pen"},
1354 { 0x0902, "Mouse", "mouse"},
1355 { 0x0A00, "Dock station", "dock", 0x00ff},
1356 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1357 { 0x0c00, "Fireware contorller", "fireware"},
1358 { 0x0c01, "Access bus controller", "access-bus"},
1359 { 0x0c02, "SSA controller", "ssa"},
1360 { 0x0c03, "USB controller", "usb"},
1361 { 0x0c04, "Fibre channel controller", "fibre-channel"},
f7748569 1362 { 0x0c05, "SMBus"},
6650ee6d
PB		 1363 { 0, NULL}
1364};
1365
163c8a59 1366static void pci_for_each_device_under_bus(PCIBus *bus,
7aa8cbb9
AP		 1367 void (*fn)(PCIBus *b, PCIDevice *d,
1368 void *opaque),
1369 void *opaque)
30468f78 1370{
163c8a59
LC		 1371 PCIDevice *d;
1372 int devfn;
30468f78 1373
163c8a59
LC		 1374 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1375 d = bus->devices[devfn];
1376 if (d) {
7aa8cbb9 1377 fn(bus, d, opaque);
163c8a59
LC		 1378 }
1379 }
1380}
1381
1382void pci_for_each_device(PCIBus *bus, int bus_num,
7aa8cbb9
AP		 1383 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1384 void *opaque)
163c8a59 1385{
d662210a 1386 bus = pci_find_bus_nr(bus, bus_num);
163c8a59
LC		 1387
1388 if (bus) {
7aa8cbb9 1389 pci_for_each_device_under_bus(bus, fn, opaque);
163c8a59
LC		 1390 }
1391}
1392
79627472 1393static const pci_class_desc *get_class_desc(int class)
163c8a59 1394{
79627472 1395 const pci_class_desc *desc;
163c8a59 1396
79627472
LC		 1397 desc = pci_class_descriptions;
1398 while (desc->desc && class != desc->class) {
1399 desc++;
30468f78 1400 }
b4dccd8d 1401
79627472
LC		 1402 return desc;
1403}
14421258 1404
79627472 1405static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
163c8a59 1406
79627472
LC		 1407static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1408{
1409 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1410 int i;
163c8a59 1411
79627472
LC		 1412 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1413 const PCIIORegion *r = &dev->io_regions[i];
1414 PciMemoryRegionList *region;
1415
1416 if (!r->size) {
1417 continue;
502a5395 1418 }
163c8a59 1419
79627472
LC		 1420 region = g_malloc0(sizeof(*region));
1421 region->value = g_malloc0(sizeof(*region->value));
163c8a59 1422
79627472
LC		 1423 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1424 region->value->type = g_strdup("io");
1425 } else {
1426 region->value->type = g_strdup("memory");
1427 region->value->has_prefetch = true;
1428 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1429 region->value->has_mem_type_64 = true;
1430 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
d5e4acf7 1431 }
163c8a59 1432
79627472
LC		 1433 region->value->bar = i;
1434 region->value->address = r->addr;
1435 region->value->size = r->size;
163c8a59 1436
79627472
LC		 1437 /* XXX: waiting for the qapi to support GSList */
1438 if (!cur_item) {
1439 head = cur_item = region;
1440 } else {
1441 cur_item->next = region;
1442 cur_item = region;
163c8a59 1443 }
80b3ada7 1444 }
384d8876 1445
79627472 1446 return head;
163c8a59
LC		 1447}
1448
79627472
LC		 1449static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1450 int bus_num)
163c8a59 1451{
79627472 1452 PciBridgeInfo *info;
163c8a59 1453
79627472 1454 info = g_malloc0(sizeof(*info));
163c8a59 1455
79627472
LC		 1456 info->bus.number = dev->config[PCI_PRIMARY_BUS];
1457 info->bus.secondary = dev->config[PCI_SECONDARY_BUS];
1458 info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS];
163c8a59 1459
79627472
LC		 1460 info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range));
1461 info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1462 info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
163c8a59 1463
79627472
LC		 1464 info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range));
1465 info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1466 info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
163c8a59 1467
79627472
LC		 1468 info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range));
1469 info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1470 info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
163c8a59 1471
79627472 1472 if (dev->config[PCI_SECONDARY_BUS] != 0) {
d662210a 1473 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
79627472
LC		 1474 if (child_bus) {
1475 info->has_devices = true;
1476 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1477 }
163c8a59
LC		 1478 }
1479
79627472 1480 return info;
163c8a59
LC		 1481}
1482
79627472
LC		 1483static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1484 int bus_num)
163c8a59 1485{
79627472
LC		 1486 const pci_class_desc *desc;
1487 PciDeviceInfo *info;
b5937f29 1488 uint8_t type;
79627472 1489 int class;
163c8a59 1490
79627472
LC		 1491 info = g_malloc0(sizeof(*info));
1492 info->bus = bus_num;
1493 info->slot = PCI_SLOT(dev->devfn);
1494 info->function = PCI_FUNC(dev->devfn);
1495
1496 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
6f88009e 1497 info->class_info.q_class = class;
79627472
LC		 1498 desc = get_class_desc(class);
1499 if (desc->desc) {
1500 info->class_info.has_desc = true;
1501 info->class_info.desc = g_strdup(desc->desc);
1502 }
1503
1504 info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1505 info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID);
1506 info->regions = qmp_query_pci_regions(dev);
1507 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
163c8a59
LC		 1508
1509 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
79627472
LC		 1510 info->has_irq = true;
1511 info->irq = dev->config[PCI_INTERRUPT_LINE];
163c8a59
LC		 1512 }
1513
b5937f29
IY		 1514 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1515 if (type == PCI_HEADER_TYPE_BRIDGE) {
79627472
LC		 1516 info->has_pci_bridge = true;
1517 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
163c8a59
LC		 1518 }
1519
79627472 1520 return info;
163c8a59
LC		 1521}
1522
79627472 1523static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
384d8876 1524{
79627472 1525 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
163c8a59 1526 PCIDevice *dev;
79627472 1527 int devfn;
163c8a59
LC		 1528
1529 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1530 dev = bus->devices[devfn];
1531 if (dev) {
79627472
LC		 1532 info = g_malloc0(sizeof(*info));
1533 info->value = qmp_query_pci_device(dev, bus, bus_num);
1534
1535 /* XXX: waiting for the qapi to support GSList */
1536 if (!cur_item) {
1537 head = cur_item = info;
1538 } else {
1539 cur_item->next = info;
1540 cur_item = info;
1541 }
163c8a59 1542 }
1074df4f 1543 }
163c8a59 1544
79627472 1545 return head;
1074df4f
IY		 1546}
1547
79627472 1548static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1074df4f 1549{
79627472
LC		 1550 PciInfo *info = NULL;
1551
d662210a 1552 bus = pci_find_bus_nr(bus, bus_num);
502a5395 1553 if (bus) {
79627472
LC		 1554 info = g_malloc0(sizeof(*info));
1555 info->bus = bus_num;
1556 info->devices = qmp_query_pci_devices(bus, bus_num);
f2aa58c6 1557 }
163c8a59 1558
79627472 1559 return info;
f2aa58c6
FB		 1560}
1561
79627472 1562PciInfoList *qmp_query_pci(Error **errp)
f2aa58c6 1563{
79627472 1564 PciInfoList *info, *head = NULL, *cur_item = NULL;
7588e2b0 1565 PCIHostState *host_bridge;
163c8a59 1566
7588e2b0 1567 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
79627472 1568 info = g_malloc0(sizeof(*info));
7588e2b0 1569 info->value = qmp_query_pci_bus(host_bridge->bus, 0);
79627472
LC		 1570
1571 /* XXX: waiting for the qapi to support GSList */
1572 if (!cur_item) {
1573 head = cur_item = info;
1574 } else {
1575 cur_item->next = info;
1576 cur_item = info;
163c8a59 1577 }
e822a52a 1578 }
163c8a59 1579
79627472 1580 return head;
77d4bc34 1581}
a41b2ff2 1582
cb457d76
AL		 1583static const char * const pci_nic_models[] = {
1584 "ne2k_pci",
1585 "i82551",
1586 "i82557b",
1587 "i82559er",
1588 "rtl8139",
1589 "e1000",
1590 "pcnet",
1591 "virtio",
1592 NULL
1593};
1594
9d07d757
PB		 1595static const char * const pci_nic_names[] = {
1596 "ne2k_pci",
1597 "i82551",
1598 "i82557b",
1599 "i82559er",
1600 "rtl8139",
1601 "e1000",
1602 "pcnet",
53c25cea 1603 "virtio-net-pci",
cb457d76
AL		 1604 NULL
1605};
1606
a41b2ff2 1607/* Initialize a PCI NIC. */
33e66b86 1608/* FIXME callers should check for failure, but don't */
29b358f9
DG		 1609PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus,
1610 const char *default_model,
5607c388 1611 const char *default_devaddr)
a41b2ff2 1612{
5607c388 1613 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
07caea31
MA		 1614 PCIBus *bus;
1615 int devfn;
5607c388 1616 PCIDevice *pci_dev;
9d07d757 1617 DeviceState *dev;
cb457d76
AL		 1618 int i;
1619
07caea31
MA		 1620 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1621 if (i < 0)
1622 return NULL;
1623
29b358f9 1624 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
07caea31 1625 if (!bus) {
1ecda02b
MA		 1626 error_report("Invalid PCI device address %s for device %s",
1627 devaddr, pci_nic_names[i]);
07caea31
MA		 1628 return NULL;
1629 }
1630
499cf102 1631 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
9ee05825 1632 dev = &pci_dev->qdev;
1cc33683 1633 qdev_set_nic_properties(dev, nd);
07caea31
MA		 1634 if (qdev_init(dev) < 0)
1635 return NULL;
9ee05825 1636 return pci_dev;
a41b2ff2
PB		 1637}
1638
29b358f9
DG		 1639PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
1640 const char *default_model,
07caea31
MA		 1641 const char *default_devaddr)
1642{
1643 PCIDevice *res;
1644
1645 if (qemu_show_nic_models(nd->model, pci_nic_models))
1646 exit(0);
1647
29b358f9 1648 res = pci_nic_init(nd, rootbus, default_model, default_devaddr);
07caea31
MA		 1649 if (!res)
1650 exit(1);
1651 return res;
1652}
1653
129d42fb
AJ		 1654PCIDevice *pci_vga_init(PCIBus *bus)
1655{
1656 switch (vga_interface_type) {
1657 case VGA_CIRRUS:
1658 return pci_create_simple(bus, -1, "cirrus-vga");
1659 case VGA_QXL:
1660 return pci_create_simple(bus, -1, "qxl-vga");
1661 case VGA_STD:
1662 return pci_create_simple(bus, -1, "VGA");
1663 case VGA_VMWARE:
1664 return pci_create_simple(bus, -1, "vmware-svga");
1665 case VGA_NONE:
1666 default: /* Other non-PCI types. Checking for unsupported types is already
1667 done in vl.c. */
1668 return NULL;
1669 }
1670}
1671
929176c3
MT		 1672/* Whether a given bus number is in range of the secondary
1673 * bus of the given bridge device. */
1674static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1675{
1676 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1677 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1678 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1679 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1680}
1681
d662210a 1682static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
3ae80618 1683{
470e6363 1684 PCIBus *sec;
3ae80618 1685
470e6363 1686 if (!bus) {
e822a52a 1687 return NULL;
470e6363 1688 }
3ae80618 1689
e822a52a
IY		 1690 if (pci_bus_num(bus) == bus_num) {
1691 return bus;
1692 }
1693
929176c3 1694 /* Consider all bus numbers in range for the host pci bridge. */
0889464a 1695 if (!pci_bus_is_root(bus) &&
929176c3
MT		 1696 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1697 return NULL;
1698 }
1699
e822a52a 1700 /* try child bus */
929176c3
MT		 1701 for (; bus; bus = sec) {
1702 QLIST_FOREACH(sec, &bus->child, sibling) {
0889464a 1703 assert(!pci_bus_is_root(sec));
929176c3
MT		 1704 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1705 return sec;
1706 }
1707 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1708 break;
c021f8e6 1709 }
e822a52a
IY		 1710 }
1711 }
1712
1713 return NULL;
3ae80618
AL		 1714}
1715
eb0acfdd
MT		 1716void pci_for_each_bus_depth_first(PCIBus *bus,
1717 void *(*begin)(PCIBus *bus, void *parent_state),
1718 void (*end)(PCIBus *bus, void *state),
1719 void *parent_state)
1720{
1721 PCIBus *sec;
1722 void *state;
1723
1724 if (!bus) {
1725 return;
1726 }
1727
1728 if (begin) {
1729 state = begin(bus, parent_state);
1730 } else {
1731 state = parent_state;
1732 }
1733
1734 QLIST_FOREACH(sec, &bus->child, sibling) {
1735 pci_for_each_bus_depth_first(sec, begin, end, state);
1736 }
1737
1738 if (end) {
1739 end(bus, state);
1740 }
1741}
1742
1743
5256d8bf 1744PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
3ae80618 1745{
d662210a 1746 bus = pci_find_bus_nr(bus, bus_num);
3ae80618
AL		 1747
1748 if (!bus)
1749 return NULL;
1750
5256d8bf 1751 return bus->devices[devfn];
3ae80618
AL		 1752}
1753
d307af79 1754static int pci_qdev_init(DeviceState *qdev)
6b1b92d3
PB		 1755{
1756 PCIDevice *pci_dev = (PCIDevice *)qdev;
40021f08 1757 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
6b1b92d3 1758 PCIBus *bus;
113f89df 1759 int rc;
ab85ceb1 1760 bool is_default_rom;
6b1b92d3 1761
a9f49946 1762 /* initialize cap_present for pci_is_express() and pci_config_size() */
40021f08 1763 if (pc->is_express) {
a9f49946
IY		 1764 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1765 }
1766
fef7fbc9 1767 bus = PCI_BUS(qdev_get_parent_bus(qdev));
6e008585
AL		 1768 pci_dev = do_pci_register_device(pci_dev, bus,
1769 object_get_typename(OBJECT(qdev)),
1770 pci_dev->devfn);
09e3acc6
GH		 1771 if (pci_dev == NULL)
1772 return -1;
2897ae02 1773
40021f08
AL		 1774 if (pc->init) {
1775 rc = pc->init(pci_dev);
c2afc922
IY		 1776 if (rc != 0) {
1777 do_pci_unregister_device(pci_dev);
1778 return rc;
1779 }
925fe64a 1780 }
8c52c8f3
GH		 1781
1782 /* rom loading */
ab85ceb1 1783 is_default_rom = false;
40021f08
AL		 1784 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
1785 pci_dev->romfile = g_strdup(pc->romfile);
ab85ceb1
SW		 1786 is_default_rom = true;
1787 }
178e785f
MA		 1788
1789 rc = pci_add_option_rom(pci_dev, is_default_rom);
1790 if (rc != 0) {
1791 pci_unregister_device(DEVICE(pci_dev));
1792 return rc;
1793 }
8c52c8f3 1794
ee995ffb
GH		 1795 return 0;
1796}
1797
49823868
IY		 1798PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1799 const char *name)
6b1b92d3
PB		 1800{
1801 DeviceState *dev;
1802
02e2da45 1803 dev = qdev_create(&bus->qbus, name);
09f1bbcd 1804 qdev_prop_set_int32(dev, "addr", devfn);
49823868 1805 qdev_prop_set_bit(dev, "multifunction", multifunction);
40021f08 1806 return PCI_DEVICE(dev);
71077c1c 1807}
6b1b92d3 1808
49823868
IY		 1809PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1810 bool multifunction,
1811 const char *name)
71077c1c 1812{
49823868 1813 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
e23a1b33 1814 qdev_init_nofail(&dev->qdev);
71077c1c 1815 return dev;
6b1b92d3 1816}
6f4cbd39 1817
49823868
IY		 1818PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1819{
1820 return pci_create_multifunction(bus, devfn, false, name);
1821}
1822
1823PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1824{
1825 return pci_create_simple_multifunction(bus, devfn, false, name);
1826}
1827
b56d701f 1828static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
6f4cbd39
MT		 1829{
1830 int offset = PCI_CONFIG_HEADER_SIZE;
1831 int i;
b56d701f 1832 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
6f4cbd39
MT		 1833 if (pdev->used[i])
1834 offset = i + 1;
1835 else if (i - offset + 1 == size)
1836 return offset;
b56d701f 1837 }
6f4cbd39
MT		 1838 return 0;
1839}
1840
1841static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1842 uint8_t *prev_p)
1843{
1844 uint8_t next, prev;
1845
1846 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1847 return 0;
1848
1849 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1850 prev = next + PCI_CAP_LIST_NEXT)
1851 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1852 break;
1853
1854 if (prev_p)
1855 *prev_p = prev;
1856 return next;
1857}
1858
c9abe111
JK		 1859static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
1860{
1861 uint8_t next, prev, found = 0;
1862
1863 if (!(pdev->used[offset])) {
1864 return 0;
1865 }
1866
1867 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
1868
1869 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1870 prev = next + PCI_CAP_LIST_NEXT) {
1871 if (next <= offset && next > found) {
1872 found = next;
1873 }
1874 }
1875 return found;
1876}
1877
ab85ceb1
SW		 1878/* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1879 This is needed for an option rom which is used for more than one device. */
1880static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1881{
1882 uint16_t vendor_id;
1883 uint16_t device_id;
1884 uint16_t rom_vendor_id;
1885 uint16_t rom_device_id;
1886 uint16_t rom_magic;
1887 uint16_t pcir_offset;
1888 uint8_t checksum;
1889
1890 /* Words in rom data are little endian (like in PCI configuration),
1891 so they can be read / written with pci_get_word / pci_set_word. */
1892
1893 /* Only a valid rom will be patched. */
1894 rom_magic = pci_get_word(ptr);
1895 if (rom_magic != 0xaa55) {
1896 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1897 return;
1898 }
1899 pcir_offset = pci_get_word(ptr + 0x18);
1900 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1901 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1902 return;
1903 }
1904
1905 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1906 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1907 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1908 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1909
1910 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1911 vendor_id, device_id, rom_vendor_id, rom_device_id);
1912
1913 checksum = ptr[6];
1914
1915 if (vendor_id != rom_vendor_id) {
1916 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1917 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1918 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1919 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1920 ptr[6] = checksum;
1921 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1922 }
1923
1924 if (device_id != rom_device_id) {
1925 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1926 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1927 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1928 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1929 ptr[6] = checksum;
1930 pci_set_word(ptr + pcir_offset + 6, device_id);
1931 }
1932}
1933
c2039bd0 1934/* Add an option rom for the device */
ab85ceb1 1935static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
c2039bd0
AL		 1936{
1937 int size;
1938 char *path;
1939 void *ptr;
1724f049 1940 char name[32];
4be9f0d1 1941 const VMStateDescription *vmsd;
c2039bd0 1942
8c52c8f3
GH		 1943 if (!pdev->romfile)
1944 return 0;
1945 if (strlen(pdev->romfile) == 0)
1946 return 0;
1947
88169ddf
GH		 1948 if (!pdev->rom_bar) {
1949 /*
1950 * Load rom via fw_cfg instead of creating a rom bar,
1951 * for 0.11 compatibility.
1952 */
1953 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
db80c7b9
MA		 1954
1955 /*
1956 * Hot-plugged devices can't use the option ROM
1957 * if the rom bar is disabled.
1958 */
1959 if (DEVICE(pdev)->hotplugged) {
1960 return -1;
1961 }
1962
88169ddf
GH		 1963 if (class == 0x0300) {
1964 rom_add_vga(pdev->romfile);
1965 } else {
2e55e842 1966 rom_add_option(pdev->romfile, -1);
88169ddf
GH		 1967 }
1968 return 0;
1969 }
1970
8c52c8f3 1971 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
c2039bd0 1972 if (path == NULL) {
7267c094 1973 path = g_strdup(pdev->romfile);
c2039bd0
AL		 1974 }
1975
1976 size = get_image_size(path);
8c52c8f3 1977 if (size < 0) {
1ecda02b 1978 error_report("%s: failed to find romfile \"%s\"",
8c7f3dd0
SH		 1979 __func__, pdev->romfile);
1980 g_free(path);
1981 return -1;
1982 } else if (size == 0) {
1983 error_report("%s: ignoring empty romfile \"%s\"",
1984 __func__, pdev->romfile);
7267c094 1985 g_free(path);
8c52c8f3
GH		 1986 return -1;
1987 }
c2039bd0
AL		 1988 if (size & (size - 1)) {
1989 size = 1 << qemu_fls(size);
1990 }
1991
4be9f0d1
AL		 1992 vmsd = qdev_get_vmsd(DEVICE(pdev));
1993
1994 if (vmsd) {
1995 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
1996 } else {
f79f2bfc 1997 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
4be9f0d1 1998 }
14caaf7f 1999 pdev->has_rom = true;
49946538 2000 memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size, &error_abort);
c5705a77 2001 vmstate_register_ram(&pdev->rom, &pdev->qdev);
14caaf7f 2002 ptr = memory_region_get_ram_ptr(&pdev->rom);
c2039bd0 2003 load_image(path, ptr);
7267c094 2004 g_free(path);
c2039bd0 2005
ab85ceb1
SW		 2006 if (is_default_rom) {
2007 /* Only the default rom images will be patched (if needed). */
2008 pci_patch_ids(pdev, ptr, size);
2009 }
2010
e824b2cc 2011 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
c2039bd0
AL		 2012
2013 return 0;
2014}
2015
230741dc
AW		 2016static void pci_del_option_rom(PCIDevice *pdev)
2017{
14caaf7f 2018 if (!pdev->has_rom)
230741dc
AW		 2019 return;
2020
c5705a77 2021 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
14caaf7f 2022 pdev->has_rom = false;
230741dc
AW		 2023}
2024
ca77089d
IY		 2025/*
2026 * if !offset
2027 * Reserve space and add capability to the linked list in pci config space
2028 *
2029 * if offset = 0,
2030 * Find and reserve space and add capability to the linked list
2031 * in pci config space */
2032int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
2033 uint8_t offset, uint8_t size)
cd9aa33e
LE		 2034{
2035 int ret;
2036 Error *local_err = NULL;
2037
2038 ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err);
2039 if (local_err) {
2040 assert(ret < 0);
2041 error_report("%s", error_get_pretty(local_err));
2042 error_free(local_err);
2043 } else {
2044 /* success implies a positive offset in config space */
2045 assert(ret > 0);
2046 }
2047 return ret;
2048}
2049
2050int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id,
2051 uint8_t offset, uint8_t size,
2052 Error **errp)
6f4cbd39 2053{
ca77089d 2054 uint8_t *config;
c9abe111
JK		 2055 int i, overlapping_cap;
2056
ca77089d
IY		 2057 if (!offset) {
2058 offset = pci_find_space(pdev, size);
2059 if (!offset) {
cd9aa33e 2060 error_setg(errp, "out of PCI config space");
ca77089d
IY		 2061 return -ENOSPC;
2062 }
c9abe111
JK		 2063 } else {
2064 /* Verify that capabilities don't overlap. Note: device assignment
2065 * depends on this check to verify that the device is not broken.
2066 * Should never trigger for emulated devices, but it's helpful
2067 * for debugging these. */
2068 for (i = offset; i < offset + size; i++) {
2069 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2070 if (overlapping_cap) {
cd9aa33e
LE		 2071 error_setg(errp, "%s:%02x:%02x.%x "
2072 "Attempt to add PCI capability %x at offset "
2073 "%x overlaps existing capability %x at offset %x",
2074 pci_root_bus_path(pdev), pci_bus_num(pdev->bus),
2075 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2076 cap_id, offset, overlapping_cap, i);
c9abe111
JK		 2077 return -EINVAL;
2078 }
2079 }
ca77089d
IY		 2080 }
2081
2082 config = pdev->config + offset;
6f4cbd39
MT		 2083 config[PCI_CAP_LIST_ID] = cap_id;
2084 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2085 pdev->config[PCI_CAPABILITY_LIST] = offset;
2086 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
e26631b7 2087 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
6f4cbd39
MT		 2088 /* Make capability read-only by default */
2089 memset(pdev->wmask + offset, 0, size);
bd4b65ee
MT		 2090 /* Check capability by default */
2091 memset(pdev->cmask + offset, 0xFF, size);
6f4cbd39
MT		 2092 return offset;
2093}
2094
2095/* Unlink capability from the pci config space. */
2096void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2097{
2098 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2099 if (!offset)
2100 return;
2101 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
ebabb67a 2102 /* Make capability writable again */
6f4cbd39 2103 memset(pdev->wmask + offset, 0xff, size);
1a4f5971 2104 memset(pdev->w1cmask + offset, 0, size);
bd4b65ee
MT		 2105 /* Clear cmask as device-specific registers can't be checked */
2106 memset(pdev->cmask + offset, 0, size);
e26631b7 2107 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
6f4cbd39
MT		 2108
2109 if (!pdev->config[PCI_CAPABILITY_LIST])
2110 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2111}
2112
6f4cbd39
MT		 2113uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2114{
2115 return pci_find_capability_list(pdev, cap_id, NULL);
2116}
10c4c98a
GH		 2117
2118static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2119{
2120 PCIDevice *d = (PCIDevice *)dev;
2121 const pci_class_desc *desc;
2122 char ctxt[64];
2123 PCIIORegion *r;
2124 int i, class;
2125
b0ff8eb2 2126 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
10c4c98a
GH		 2127 desc = pci_class_descriptions;
2128 while (desc->desc && class != desc->class)
2129 desc++;
2130 if (desc->desc) {
2131 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2132 } else {
2133 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2134 }
2135
2136 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2137 "pci id %04x:%04x (sub %04x:%04x)\n",
7f5feab4 2138 indent, "", ctxt, pci_bus_num(d->bus),
e822a52a 2139 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
b0ff8eb2
IY		 2140 pci_get_word(d->config + PCI_VENDOR_ID),
2141 pci_get_word(d->config + PCI_DEVICE_ID),
2142 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2143 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
10c4c98a
GH		 2144 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2145 r = &d->io_regions[i];
2146 if (!r->size)
2147 continue;
89e8b13c
IY		 2148 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2149 " [0x%"FMT_PCIBUS"]\n",
2150 indent, "",
0392a017 2151 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
10c4c98a
GH		 2152 r->addr, r->addr + r->size - 1);
2153 }
2154}
03587182 2155
5e0259e7
GN		 2156static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2157{
2158 PCIDevice *d = (PCIDevice *)dev;
2159 const char *name = NULL;
2160 const pci_class_desc *desc = pci_class_descriptions;
2161 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2162
2163 while (desc->desc &&
2164 (class & ~desc->fw_ign_bits) !=
2165 (desc->class & ~desc->fw_ign_bits)) {
2166 desc++;
2167 }
2168
2169 if (desc->desc) {
2170 name = desc->fw_name;
2171 }
2172
2173 if (name) {
2174 pstrcpy(buf, len, name);
2175 } else {
2176 snprintf(buf, len, "pci%04x,%04x",
2177 pci_get_word(d->config + PCI_VENDOR_ID),
2178 pci_get_word(d->config + PCI_DEVICE_ID));
2179 }
2180
2181 return buf;
2182}
2183
2184static char *pcibus_get_fw_dev_path(DeviceState *dev)
2185{
2186 PCIDevice *d = (PCIDevice *)dev;
2187 char path[50], name[33];
2188 int off;
2189
2190 off = snprintf(path, sizeof(path), "%s@%x",
2191 pci_dev_fw_name(dev, name, sizeof name),
2192 PCI_SLOT(d->devfn));
2193 if (PCI_FUNC(d->devfn))
2194 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
a5cf8262 2195 return g_strdup(path);
5e0259e7
GN		 2196}
2197
4f43c1ff
AW		 2198static char *pcibus_get_dev_path(DeviceState *dev)
2199{
a6a7005d
MT		 2200 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2201 PCIDevice *t;
2202 int slot_depth;
2203 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2204 * 00 is added here to make this format compatible with
2205 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2206 * Slot.Function list specifies the slot and function numbers for all
2207 * devices on the path from root to the specific device. */
568f0690
DG		 2208 const char *root_bus_path;
2209 int root_bus_len;
2991181a 2210 char slot[] = ":SS.F";
2991181a 2211 int slot_len = sizeof slot - 1 /* For '\0' */;
a6a7005d
MT		 2212 int path_len;
2213 char *path, *p;
2991181a 2214 int s;
a6a7005d 2215
568f0690
DG		 2216 root_bus_path = pci_root_bus_path(d);
2217 root_bus_len = strlen(root_bus_path);
2218
a6a7005d
MT		 2219 /* Calculate # of slots on path between device and root. */;
2220 slot_depth = 0;
2221 for (t = d; t; t = t->bus->parent_dev) {
2222 ++slot_depth;
2223 }
2224
568f0690 2225 path_len = root_bus_len + slot_len * slot_depth;
a6a7005d
MT		 2226
2227 /* Allocate memory, fill in the terminating null byte. */
7267c094 2228 path = g_malloc(path_len + 1 /* For '\0' */);
a6a7005d
MT		 2229 path[path_len] = '\0';
2230
568f0690 2231 memcpy(path, root_bus_path, root_bus_len);
a6a7005d
MT		 2232
2233 /* Fill in slot numbers. We walk up from device to root, so need to print
2234 * them in the reverse order, last to first. */
2235 p = path + path_len;
2236 for (t = d; t; t = t->bus->parent_dev) {
2237 p -= slot_len;
2991181a 2238 s = snprintf(slot, sizeof slot, ":%02x.%x",
4c900518 2239 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2991181a
MT		 2240 assert(s == slot_len);
2241 memcpy(p, slot, slot_len);
a6a7005d
MT		 2242 }
2243
2244 return path;
4f43c1ff
AW		 2245}
2246
f3006dd1
IY		 2247static int pci_qdev_find_recursive(PCIBus *bus,
2248 const char *id, PCIDevice **pdev)
2249{
2250 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2251 if (!qdev) {
2252 return -ENODEV;
2253 }
2254
2255 /* roughly check if given qdev is pci device */
4be9f0d1 2256 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
40021f08 2257 *pdev = PCI_DEVICE(qdev);
f3006dd1
IY		 2258 return 0;
2259 }
2260 return -EINVAL;
2261}
2262
2263int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2264{
7588e2b0 2265 PCIHostState *host_bridge;
f3006dd1
IY		 2266 int rc = -ENODEV;
2267
7588e2b0
DG		 2268 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2269 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
f3006dd1
IY		 2270 if (!tmp) {
2271 rc = 0;
2272 break;
2273 }
2274 if (tmp != -ENODEV) {
2275 rc = tmp;
2276 }
2277 }
2278
2279 return rc;
2280}
f5e6fed8
AK		 2281
2282MemoryRegion *pci_address_space(PCIDevice *dev)
2283{
2284 return dev->bus->address_space_mem;
2285}
e11d6439
RH		 2286
2287MemoryRegion *pci_address_space_io(PCIDevice *dev)
2288{
2289 return dev->bus->address_space_io;
2290}
40021f08 2291
39bffca2
AL		 2292static void pci_device_class_init(ObjectClass *klass, void *data)
2293{
2294 DeviceClass *k = DEVICE_CLASS(klass);
2295 k->init = pci_qdev_init;
39bffca2 2296 k->exit = pci_unregister_device;
0d936928 2297 k->bus_type = TYPE_PCI_BUS;
bce54474 2298 k->props = pci_props;
39bffca2
AL		 2299}
2300
9eda7d37
AK		 2301AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2302{
2303 PCIBus *bus = PCI_BUS(dev->bus);
2304
2305 if (bus->iommu_fn) {
2306 return bus->iommu_fn(bus, bus->iommu_opaque, dev->devfn);
2307 }
2308
2309 if (bus->parent_dev) {
2310 /** We are ignoring the bus master DMA bit of the bridge
2311 * as it would complicate things such as VFIO for no good reason */
2312 return pci_device_iommu_address_space(bus->parent_dev);
2313 }
2314
2315 return &address_space_memory;
2316}
2317
e00387d5 2318void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
5fa45de5 2319{
e00387d5
AK		 2320 bus->iommu_fn = fn;
2321 bus->iommu_opaque = opaque;
5fa45de5
DG		 2322}
2323
43864069
MT		 2324static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2325{
2326 Range *range = opaque;
2327 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2328 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
77d6f4ea 2329 int i;
43864069
MT		 2330
2331 if (!(cmd & PCI_COMMAND_MEMORY)) {
2332 return;
2333 }
2334
2335 if (pc->is_bridge) {
2336 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2337 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2338
2339 base = MAX(base, 0x1ULL << 32);
2340
2341 if (limit >= base) {
2342 Range pref_range;
2343 pref_range.begin = base;
2344 pref_range.end = limit + 1;
2345 range_extend(range, &pref_range);
2346 }
2347 }
77d6f4ea
MT		 2348 for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2349 PCIIORegion *r = &dev->io_regions[i];
43864069
MT		 2350 Range region_range;
2351
77d6f4ea
MT		 2352 if (!r->size ||
2353 (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2354 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2355 continue;
2356 }
2357 region_range.begin = pci_bar_address(dev, i, r->type, r->size);
2358 region_range.end = region_range.begin + r->size;
2359
2360 if (region_range.begin == PCI_BAR_UNMAPPED) {
43864069
MT		 2361 continue;
2362 }
43864069
MT		 2363
2364 region_range.begin = MAX(region_range.begin, 0x1ULL << 32);
2365
2366 if (region_range.end - 1 >= region_range.begin) {
2367 range_extend(range, &region_range);
2368 }
2369 }
2370}
2371
2372void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2373{
2374 range->begin = range->end = 0;
2375 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2376}
2377
8c43a6f0 2378static const TypeInfo pci_device_type_info = {
40021f08
AL		 2379 .name = TYPE_PCI_DEVICE,
2380 .parent = TYPE_DEVICE,
2381 .instance_size = sizeof(PCIDevice),
2382 .abstract = true,
2383 .class_size = sizeof(PCIDeviceClass),
39bffca2 2384 .class_init = pci_device_class_init,
40021f08
AL		 2385};
2386
83f7d43a 2387static void pci_register_types(void)
40021f08 2388{
0d936928 2389 type_register_static(&pci_bus_info);
3a861c46 2390 type_register_static(&pcie_bus_info);
40021f08
AL		 2391 type_register_static(&pci_device_type_info);
2392}
2393
83f7d43a 2394type_init(pci_register_types)
Empty description
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