projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 625e3dd4 PM |
1 | /* |
| 2 | * ARM translation: AArch32 Neon instructions | |
| 3 | * | |
| 4 | * Copyright (c) 2003 Fabrice Bellard | |
| 5 | * Copyright (c) 2005-2007 CodeSourcery | |
| 6 | * Copyright (c) 2007 OpenedHand, Ltd. | |
| 7 | * Copyright (c) 2020 Linaro, Ltd. | |
| 8 | * | |
| 9 | * This library is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU Lesser General Public | |
| 11 | * License as published by the Free Software Foundation; either | |
| 12 | * version 2 of the License, or (at your option) any later version. | |
| 13 | * | |
| 14 | * This library is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 17 | * Lesser General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU Lesser General Public | |
| 20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
| 21 | */ | |
| 22 | ||
| 23 | /* | |
| 24 | * This file is intended to be included from translate.c; it uses | |
| 25 | * some macros and definitions provided by that file. | |
| 26 | * It might be possible to convert it to a standalone .c file eventually. | |
| 27 | */ | |
| 28 | ||
| 29 | /* Include the generated Neon decoder */ | |
| 30 | #include "decode-neon-dp.inc.c" | |
| 31 | #include "decode-neon-ls.inc.c" | |
| 32 | #include "decode-neon-shared.inc.c" | |
| afff8de0 PM |
33 | |
| 34 | static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) | |
| 35 | { | |
| 36 | int opr_sz; | |
| 37 | TCGv_ptr fpst; | |
| 38 | gen_helper_gvec_3_ptr *fn_gvec_ptr; | |
| 39 | ||
| 40 | if (!dc_isar_feature(aa32_vcma, s) | |
| 41 | || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) { | |
| 42 | return false; | |
| 43 | } | |
| 44 | ||
| 45 | /* UNDEF accesses to D16-D31 if they don't exist. */ | |
| 46 | if (!dc_isar_feature(aa32_simd_r32, s) && | |
| 47 | ((a->vd | a->vn | a->vm) & 0x10)) { | |
| 48 | return false; | |
| 49 | } | |
| 50 | ||
| 51 | if ((a->vn | a->vm | a->vd) & a->q) { | |
| 52 | return false; | |
| 53 | } | |
| 54 | ||
| 55 | if (!vfp_access_check(s)) { | |
| 56 | return true; | |
| 57 | } | |
| 58 | ||
| 59 | opr_sz = (1 + a->q) * 8; | |
| 60 | fpst = get_fpstatus_ptr(1); | |
| 61 | fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah; | |
| 62 | tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), | |
| 63 | vfp_reg_offset(1, a->vn), | |
| 64 | vfp_reg_offset(1, a->vm), | |
| 65 | fpst, opr_sz, opr_sz, a->rot, | |
| 66 | fn_gvec_ptr); | |
| 67 | tcg_temp_free_ptr(fpst); | |
| 68 | return true; | |
| 69 | } | |
| 94d5eb7b PM |
70 | |
| 71 | static bool trans_VCADD(DisasContext *s, arg_VCADD *a) | |
| 72 | { | |
| 73 | int opr_sz; | |
| 74 | TCGv_ptr fpst; | |
| 75 | gen_helper_gvec_3_ptr *fn_gvec_ptr; | |
| 76 | ||
| 77 | if (!dc_isar_feature(aa32_vcma, s) | |
| 78 | || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) { | |
| 79 | return false; | |
| 80 | } | |
| 81 | ||
| 82 | /* UNDEF accesses to D16-D31 if they don't exist. */ | |
| 83 | if (!dc_isar_feature(aa32_simd_r32, s) && | |
| 84 | ((a->vd | a->vn | a->vm) & 0x10)) { | |
| 85 | return false; | |
| 86 | } | |
| 87 | ||
| 88 | if ((a->vn | a->vm | a->vd) & a->q) { | |
| 89 | return false; | |
| 90 | } | |
| 91 | ||
| 92 | if (!vfp_access_check(s)) { | |
| 93 | return true; | |
| 94 | } | |
| 95 | ||
| 96 | opr_sz = (1 + a->q) * 8; | |
| 97 | fpst = get_fpstatus_ptr(1); | |
| 98 | fn_gvec_ptr = a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh; | |
| 99 | tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), | |
| 100 | vfp_reg_offset(1, a->vn), | |
| 101 | vfp_reg_offset(1, a->vm), | |
| 102 | fpst, opr_sz, opr_sz, a->rot, | |
| 103 | fn_gvec_ptr); | |
| 104 | tcg_temp_free_ptr(fpst); | |
| 105 | return true; | |
| 106 | } |