projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| bb79174d SG |
1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* | |
| 3 | * Copyright (c) 2021 Loongson Technology Corporation Limited | |
| 4 | */ | |
| 5 | ||
| 6 | static bool gen_load(DisasContext *ctx, arg_rr_i *a, MemOp mop) | |
| 7 | { | |
| 8 | TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); | |
| 9 | TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); | |
| 10 | TCGv temp = NULL; | |
| 11 | ||
| 12 | if (a->imm) { | |
| 13 | temp = tcg_temp_new(); | |
| 14 | tcg_gen_addi_tl(temp, addr, a->imm); | |
| 15 | addr = temp; | |
| 16 | } | |
| 17 | ||
| 18 | tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); | |
| 19 | gen_set_gpr(a->rd, dest, EXT_NONE); | |
| 20 | ||
| 21 | if (temp) { | |
| 22 | tcg_temp_free(temp); | |
| 23 | } | |
| 24 | ||
| 25 | return true; | |
| 26 | } | |
| 27 | ||
| 28 | static bool gen_store(DisasContext *ctx, arg_rr_i *a, MemOp mop) | |
| 29 | { | |
| 30 | TCGv data = gpr_src(ctx, a->rd, EXT_NONE); | |
| 31 | TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); | |
| 32 | TCGv temp = NULL; | |
| 33 | ||
| 34 | if (a->imm) { | |
| 35 | temp = tcg_temp_new(); | |
| 36 | tcg_gen_addi_tl(temp, addr, a->imm); | |
| 37 | addr = temp; | |
| 38 | } | |
| 39 | ||
| 40 | tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop); | |
| 41 | ||
| 42 | if (temp) { | |
| 43 | tcg_temp_free(temp); | |
| 44 | } | |
| 45 | ||
| 46 | return true; | |
| 47 | } | |
| 48 | ||
| 49 | static bool gen_loadx(DisasContext *ctx, arg_rrr *a, MemOp mop) | |
| 50 | { | |
| 51 | TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); | |
| 52 | TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); | |
| 53 | TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); | |
| 54 | TCGv addr = tcg_temp_new(); | |
| 55 | ||
| 56 | tcg_gen_add_tl(addr, src1, src2); | |
| 57 | tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); | |
| 58 | gen_set_gpr(a->rd, dest, EXT_NONE); | |
| 59 | tcg_temp_free(addr); | |
| 60 | ||
| 61 | return true; | |
| 62 | } | |
| 63 | ||
| 64 | static bool gen_storex(DisasContext *ctx, arg_rrr *a, MemOp mop) | |
| 65 | { | |
| 66 | TCGv data = gpr_src(ctx, a->rd, EXT_NONE); | |
| 67 | TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); | |
| 68 | TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); | |
| 69 | TCGv addr = tcg_temp_new(); | |
| 70 | ||
| 71 | tcg_gen_add_tl(addr, src1, src2); | |
| 72 | tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop); | |
| 73 | tcg_temp_free(addr); | |
| 74 | ||
| 75 | return true; | |
| 76 | } | |
| 77 | ||
| 78 | static bool gen_load_gt(DisasContext *ctx, arg_rrr *a, MemOp mop) | |
| 79 | { | |
| 80 | TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); | |
| 81 | TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); | |
| 82 | TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); | |
| 83 | ||
| 84 | gen_helper_asrtgt_d(cpu_env, src1, src2); | |
| 85 | tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop); | |
| 86 | gen_set_gpr(a->rd, dest, EXT_NONE); | |
| 87 | ||
| 88 | return true; | |
| 89 | } | |
| 90 | ||
| 91 | static bool gen_load_le(DisasContext *ctx, arg_rrr *a, MemOp mop) | |
| 92 | { | |
| 93 | TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); | |
| 94 | TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); | |
| 95 | TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); | |
| 96 | ||
| 97 | gen_helper_asrtle_d(cpu_env, src1, src2); | |
| 98 | tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop); | |
| 99 | gen_set_gpr(a->rd, dest, EXT_NONE); | |
| 100 | ||
| 101 | return true; | |
| 102 | } | |
| 103 | ||
| 104 | static bool gen_store_gt(DisasContext *ctx, arg_rrr *a, MemOp mop) | |
| 105 | { | |
| 106 | TCGv data = gpr_src(ctx, a->rd, EXT_NONE); | |
| 107 | TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); | |
| 108 | TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); | |
| 109 | ||
| 110 | gen_helper_asrtgt_d(cpu_env, src1, src2); | |
| 111 | tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop); | |
| 112 | ||
| 113 | return true; | |
| 114 | } | |
| 115 | ||
| 116 | static bool gen_store_le(DisasContext *ctx, arg_rrr *a, MemOp mop) | |
| 117 | { | |
| 118 | TCGv data = gpr_src(ctx, a->rd, EXT_NONE); | |
| 119 | TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); | |
| 120 | TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); | |
| 121 | ||
| 122 | gen_helper_asrtle_d(cpu_env, src1, src2); | |
| 123 | tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop); | |
| 124 | ||
| 125 | return true; | |
| 126 | } | |
| 127 | ||
| 128 | static bool trans_preld(DisasContext *ctx, arg_preld *a) | |
| 129 | { | |
| 130 | return true; | |
| 131 | } | |
| 132 | ||
| 133 | static bool trans_dbar(DisasContext *ctx, arg_dbar * a) | |
| 134 | { | |
| 135 | tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); | |
| 136 | return true; | |
| 137 | } | |
| 138 | ||
| 139 | static bool trans_ibar(DisasContext *ctx, arg_ibar *a) | |
| 140 | { | |
| 141 | ctx->base.is_jmp = DISAS_STOP; | |
| 142 | return true; | |
| 143 | } | |
| 144 | ||
| 145 | static bool gen_ldptr(DisasContext *ctx, arg_rr_i *a, MemOp mop) | |
| 146 | { | |
| 147 | TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); | |
| 148 | TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); | |
| 149 | TCGv temp = NULL; | |
| 150 | ||
| 151 | if (a->imm) { | |
| 152 | temp = tcg_temp_new(); | |
| 153 | tcg_gen_addi_tl(temp, addr, a->imm); | |
| 154 | addr = temp; | |
| 155 | } | |
| 156 | ||
| 157 | tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); | |
| 158 | gen_set_gpr(a->rd, dest, EXT_NONE); | |
| 159 | ||
| 160 | if (temp) { | |
| 161 | tcg_temp_free(temp); | |
| 162 | } | |
| 163 | ||
| 164 | return true; | |
| 165 | } | |
| 166 | ||
| 167 | static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, MemOp mop) | |
| 168 | { | |
| 169 | TCGv data = gpr_src(ctx, a->rd, EXT_NONE); | |
| 170 | TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); | |
| 171 | TCGv temp = NULL; | |
| 172 | ||
| 173 | if (a->imm) { | |
| 174 | temp = tcg_temp_new(); | |
| 94b02d57 | 175 | tcg_gen_addi_tl(temp, addr, a->imm); |
| bb79174d SG |
176 | addr = temp; |
| 177 | } | |
| 178 | ||
| 179 | tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop); | |
| 180 | ||
| 181 | if (temp) { | |
| 182 | tcg_temp_free(temp); | |
| 183 | } | |
| 184 | ||
| 185 | return true; | |
| 186 | } | |
| 187 | ||
| 188 | TRANS(ld_b, gen_load, MO_SB) | |
| 189 | TRANS(ld_h, gen_load, MO_TESW) | |
| 190 | TRANS(ld_w, gen_load, MO_TESL) | |
| 191 | TRANS(ld_d, gen_load, MO_TEUQ) | |
| 192 | TRANS(st_b, gen_store, MO_UB) | |
| 193 | TRANS(st_h, gen_store, MO_TEUW) | |
| 194 | TRANS(st_w, gen_store, MO_TEUL) | |
| 195 | TRANS(st_d, gen_store, MO_TEUQ) | |
| 196 | TRANS(ld_bu, gen_load, MO_UB) | |
| 197 | TRANS(ld_hu, gen_load, MO_TEUW) | |
| 198 | TRANS(ld_wu, gen_load, MO_TEUL) | |
| 199 | TRANS(ldx_b, gen_loadx, MO_SB) | |
| 200 | TRANS(ldx_h, gen_loadx, MO_TESW) | |
| 201 | TRANS(ldx_w, gen_loadx, MO_TESL) | |
| 202 | TRANS(ldx_d, gen_loadx, MO_TEUQ) | |
| 203 | TRANS(stx_b, gen_storex, MO_UB) | |
| 204 | TRANS(stx_h, gen_storex, MO_TEUW) | |
| 205 | TRANS(stx_w, gen_storex, MO_TEUL) | |
| 206 | TRANS(stx_d, gen_storex, MO_TEUQ) | |
| 207 | TRANS(ldx_bu, gen_loadx, MO_UB) | |
| 208 | TRANS(ldx_hu, gen_loadx, MO_TEUW) | |
| 209 | TRANS(ldx_wu, gen_loadx, MO_TEUL) | |
| 210 | TRANS(ldptr_w, gen_ldptr, MO_TESL) | |
| 211 | TRANS(stptr_w, gen_stptr, MO_TEUL) | |
| 212 | TRANS(ldptr_d, gen_ldptr, MO_TEUQ) | |
| 213 | TRANS(stptr_d, gen_stptr, MO_TEUQ) | |
| 214 | TRANS(ldgt_b, gen_load_gt, MO_SB) | |
| 215 | TRANS(ldgt_h, gen_load_gt, MO_TESW) | |
| 216 | TRANS(ldgt_w, gen_load_gt, MO_TESL) | |
| 217 | TRANS(ldgt_d, gen_load_gt, MO_TEUQ) | |
| 218 | TRANS(ldle_b, gen_load_le, MO_SB) | |
| 219 | TRANS(ldle_h, gen_load_le, MO_TESW) | |
| 220 | TRANS(ldle_w, gen_load_le, MO_TESL) | |
| 221 | TRANS(ldle_d, gen_load_le, MO_TEUQ) | |
| 222 | TRANS(stgt_b, gen_store_gt, MO_UB) | |
| 223 | TRANS(stgt_h, gen_store_gt, MO_TEUW) | |
| 224 | TRANS(stgt_w, gen_store_gt, MO_TEUL) | |
| 225 | TRANS(stgt_d, gen_store_gt, MO_TEUQ) | |
| 226 | TRANS(stle_b, gen_store_le, MO_UB) | |
| 227 | TRANS(stle_h, gen_store_le, MO_TEUW) | |
| 228 | TRANS(stle_w, gen_store_le, MO_TEUL) | |
| 229 | TRANS(stle_d, gen_store_le, MO_TEUQ) |