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011d87d0 | 1 | /* |
2 | * TI OMAP2 32kHz sync timer emulation. | |
3 | * | |
4 | * Copyright (C) 2007-2008 Nokia Corporation | |
5 | * Written by Andrzej Zaborowski <[email protected]> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 or | |
10 | * (at your option) any later version of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
282bc81e | 20 | #include "qemu/osdep.h" |
83c9f4ca | 21 | #include "hw/hw.h" |
1de7afc9 | 22 | #include "qemu/timer.h" |
0d09e41a | 23 | #include "hw/arm/omap.h" |
011d87d0 | 24 | struct omap_synctimer_s { |
fcb40162 | 25 | MemoryRegion iomem; |
011d87d0 | 26 | uint32_t val; |
27 | uint16_t readh; | |
28 | }; | |
29 | ||
30 | /* 32-kHz Sync Timer of the OMAP2 */ | |
31 | static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) { | |
73bcb24d RS |
32 | return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 0x8000, |
33 | NANOSECONDS_PER_SECOND); | |
011d87d0 | 34 | } |
35 | ||
36 | void omap_synctimer_reset(struct omap_synctimer_s *s) | |
37 | { | |
38 | s->val = omap_synctimer_read(s); | |
39 | } | |
40 | ||
a8170e5e | 41 | static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr) |
011d87d0 | 42 | { |
43 | struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; | |
44 | ||
45 | switch (addr) { | |
46 | case 0x00: /* 32KSYNCNT_REV */ | |
47 | return 0x21; | |
48 | ||
49 | case 0x10: /* CR */ | |
50 | return omap_synctimer_read(s) - s->val; | |
51 | } | |
52 | ||
53 | OMAP_BAD_REG(addr); | |
54 | return 0; | |
55 | } | |
56 | ||
a8170e5e | 57 | static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr) |
011d87d0 | 58 | { |
59 | struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; | |
60 | uint32_t ret; | |
61 | ||
62 | if (addr & 2) | |
63 | return s->readh; | |
64 | else { | |
65 | ret = omap_synctimer_readw(opaque, addr); | |
66 | s->readh = ret >> 16; | |
67 | return ret & 0xffff; | |
68 | } | |
69 | } | |
70 | ||
a8170e5e | 71 | static void omap_synctimer_write(void *opaque, hwaddr addr, |
011d87d0 | 72 | uint32_t value) |
73 | { | |
74 | OMAP_BAD_REG(addr); | |
75 | } | |
76 | ||
fcb40162 AK |
77 | static const MemoryRegionOps omap_synctimer_ops = { |
78 | .old_mmio = { | |
79 | .read = { | |
80 | omap_badwidth_read32, | |
81 | omap_synctimer_readh, | |
82 | omap_synctimer_readw, | |
83 | }, | |
84 | .write = { | |
85 | omap_badwidth_write32, | |
86 | omap_synctimer_write, | |
87 | omap_synctimer_write, | |
88 | }, | |
89 | }, | |
90 | .endianness = DEVICE_NATIVE_ENDIAN, | |
011d87d0 | 91 | }; |
92 | ||
93 | struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, | |
94 | struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk) | |
95 | { | |
7267c094 | 96 | struct omap_synctimer_s *s = g_malloc0(sizeof(*s)); |
011d87d0 | 97 | |
98 | omap_synctimer_reset(s); | |
2c9b15ca | 99 | memory_region_init_io(&s->iomem, NULL, &omap_synctimer_ops, s, "omap.synctimer", |
fcb40162 | 100 | omap_l4_region_size(ta, 0)); |
f44336c5 | 101 | omap_l4_attach(ta, 0, &s->iomem); |
011d87d0 | 102 | |
103 | return s; | |
104 | } |