[qemu.git] / hw / pci-host / xilinx-pcie.c

/*
 * Xilinx PCIe host controller emulation.
 *
 * Copyright (c) 2016 Imagination Technologies
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci-host/xilinx-pcie.h"

enum root_cfg_reg {
    /* Interrupt Decode Register */
    ROOTCFG_INTDEC              = 0x138,

    /* Interrupt Mask Register */
    ROOTCFG_INTMASK             = 0x13c,
    /* INTx Interrupt Received */
#define ROOTCFG_INTMASK_INTX    (1 << 16)
    /* MSI Interrupt Received */
#define ROOTCFG_INTMASK_MSI     (1 << 17)

    /* PHY Status/Control Register */
    ROOTCFG_PSCR                = 0x144,
    /* Link Up */
#define ROOTCFG_PSCR_LINK_UP    (1 << 11)

    /* Root Port Status/Control Register */
    ROOTCFG_RPSCR               = 0x148,
    /* Bridge Enable */
#define ROOTCFG_RPSCR_BRIDGEEN  (1 << 0)
    /* Interrupt FIFO Not Empty */
#define ROOTCFG_RPSCR_INTNEMPTY (1 << 18)
    /* Interrupt FIFO Overflow */
#define ROOTCFG_RPSCR_INTOVF    (1 << 19)

    /* Root Port Interrupt FIFO Read Register 1 */
    ROOTCFG_RPIFR1              = 0x158,
#define ROOTCFG_RPIFR1_INT_LANE_SHIFT   27
#define ROOTCFG_RPIFR1_INT_ASSERT_SHIFT 29
#define ROOTCFG_RPIFR1_INT_VALID_SHIFT  31
    /* Root Port Interrupt FIFO Read Register 2 */
    ROOTCFG_RPIFR2              = 0x15c,
};

static void xilinx_pcie_update_intr(XilinxPCIEHost *s,
                                    uint32_t set, uint32_t clear)
{
    int level;

    s->intr |= set;
    s->intr &= ~clear;

    if (s->intr_fifo_r != s->intr_fifo_w) {
        s->intr |= ROOTCFG_INTMASK_INTX;
    }

    level = !!(s->intr & s->intr_mask);
    qemu_set_irq(s->irq, level);
}

static void xilinx_pcie_queue_intr(XilinxPCIEHost *s,
                                   uint32_t fifo_reg1, uint32_t fifo_reg2)
{
    XilinxPCIEInt *intr;
    unsigned int new_w;

    new_w = (s->intr_fifo_w + 1) % ARRAY_SIZE(s->intr_fifo);
    if (new_w == s->intr_fifo_r) {
        s->rpscr |= ROOTCFG_RPSCR_INTOVF;
        return;
    }

    intr = &s->intr_fifo[s->intr_fifo_w];
    s->intr_fifo_w = new_w;

    intr->fifo_reg1 = fifo_reg1;
    intr->fifo_reg2 = fifo_reg2;

    xilinx_pcie_update_intr(s, ROOTCFG_INTMASK_INTX, 0);
}

static void xilinx_pcie_set_irq(void *opaque, int irq_num, int level)
{
    XilinxPCIEHost *s = XILINX_PCIE_HOST(opaque);

    xilinx_pcie_queue_intr(s,
       (irq_num << ROOTCFG_RPIFR1_INT_LANE_SHIFT) |
           (level << ROOTCFG_RPIFR1_INT_ASSERT_SHIFT) |
           (1 << ROOTCFG_RPIFR1_INT_VALID_SHIFT),
       0);
}

static void xilinx_pcie_host_realize(DeviceState *dev, Error **errp)
{
    PCIHostState *pci = PCI_HOST_BRIDGE(dev);
    XilinxPCIEHost *s = XILINX_PCIE_HOST(dev);
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);

    snprintf(s->name, sizeof(s->name), "pcie%u", s->bus_nr);

    /* PCI configuration space */
    pcie_host_mmcfg_init(pex, s->cfg_size);

    /* MMIO region */
    memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX);
    memory_region_set_enabled(&s->mmio, false);

    /* dummy I/O region */
    memory_region_init_ram_nomigrate(&s->io, OBJECT(s), "io", 16, NULL);
    memory_region_set_enabled(&s->io, false);

    /* interrupt out */
    qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1);

    sysbus_init_mmio(sbd, &pex->mmio);
    sysbus_init_mmio(sbd, &s->mmio);

    pci->bus = pci_register_bus(dev, s->name, xilinx_pcie_set_irq,
                                pci_swizzle_map_irq_fn, s, &s->mmio,
                                &s->io, 0, 4, TYPE_PCIE_BUS);

    qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus));
    qdev_init_nofail(DEVICE(&s->root));
}

static const char *xilinx_pcie_host_root_bus_path(PCIHostState *host_bridge,
                                                  PCIBus *rootbus)
{
    return "0000:00";
}

static void xilinx_pcie_host_init(Object *obj)
{
    XilinxPCIEHost *s = XILINX_PCIE_HOST(obj);
    XilinxPCIERoot *root = &s->root;

    object_initialize(root, sizeof(*root), TYPE_XILINX_PCIE_ROOT);
    object_property_add_child(obj, "root", OBJECT(root), NULL);
    qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
    qdev_prop_set_bit(DEVICE(root), "multifunction", false);
}

static Property xilinx_pcie_host_props[] = {
    DEFINE_PROP_UINT32("bus_nr", XilinxPCIEHost, bus_nr, 0),
    DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0),
    DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 << 20),
    DEFINE_PROP_SIZE("mmio_base", XilinxPCIEHost, mmio_base, 0),
    DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 << 20),
    DEFINE_PROP_BOOL("link_up", XilinxPCIEHost, link_up, true),
    DEFINE_PROP_END_OF_LIST(),
};

static void xilinx_pcie_host_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);

    hc->root_bus_path = xilinx_pcie_host_root_bus_path;
    dc->realize = xilinx_pcie_host_realize;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
    dc->fw_name = "pci";
    dc->props = xilinx_pcie_host_props;
}

static const TypeInfo xilinx_pcie_host_info = {
    .name       = TYPE_XILINX_PCIE_HOST,
    .parent     = TYPE_PCIE_HOST_BRIDGE,
    .instance_size = sizeof(XilinxPCIEHost),
    .instance_init = xilinx_pcie_host_init,
    .class_init = xilinx_pcie_host_class_init,
};

static uint32_t xilinx_pcie_root_config_read(PCIDevice *d,
                                             uint32_t address, int len)
{
    XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent);
    uint32_t val;

    switch (address) {
    case ROOTCFG_INTDEC:
        val = s->intr;
        break;
    case ROOTCFG_INTMASK:
        val = s->intr_mask;
        break;
    case ROOTCFG_PSCR:
        val = s->link_up ? ROOTCFG_PSCR_LINK_UP : 0;
        break;
    case ROOTCFG_RPSCR:
        if (s->intr_fifo_r != s->intr_fifo_w) {
            s->rpscr &= ~ROOTCFG_RPSCR_INTNEMPTY;
        } else {
            s->rpscr |= ROOTCFG_RPSCR_INTNEMPTY;
        }
        val = s->rpscr;
        break;
    case ROOTCFG_RPIFR1:
        if (s->intr_fifo_w == s->intr_fifo_r) {
            /* FIFO empty */
            val = 0;
        } else {
            val = s->intr_fifo[s->intr_fifo_r].fifo_reg1;
        }
        break;
    case ROOTCFG_RPIFR2:
        if (s->intr_fifo_w == s->intr_fifo_r) {
            /* FIFO empty */
            val = 0;
        } else {
            val = s->intr_fifo[s->intr_fifo_r].fifo_reg2;
        }
        break;
    default:
        val = pci_default_read_config(d, address, len);
        break;
    }
    return val;
}

static void xilinx_pcie_root_config_write(PCIDevice *d, uint32_t address,
                                          uint32_t val, int len)
{
    XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent);
    switch (address) {
    case ROOTCFG_INTDEC:
        xilinx_pcie_update_intr(s, 0, val);
        break;
    case ROOTCFG_INTMASK:
        s->intr_mask = val;
        xilinx_pcie_update_intr(s, 0, 0);
        break;
    case ROOTCFG_RPSCR:
        s->rpscr &= ~ROOTCFG_RPSCR_BRIDGEEN;
        s->rpscr |= val & ROOTCFG_RPSCR_BRIDGEEN;
        memory_region_set_enabled(&s->mmio, val & ROOTCFG_RPSCR_BRIDGEEN);

        if (val & ROOTCFG_INTMASK_INTX) {
            s->rpscr &= ~ROOTCFG_INTMASK_INTX;
        }
        break;
    case ROOTCFG_RPIFR1:
    case ROOTCFG_RPIFR2:
        if (s->intr_fifo_w == s->intr_fifo_r) {
            /* FIFO empty */
            return;
        } else {
            s->intr_fifo_r = (s->intr_fifo_r + 1) % ARRAY_SIZE(s->intr_fifo);
        }
        break;
    default:
        pci_default_write_config(d, address, val, len);
        break;
    }
}

static int xilinx_pcie_root_init(PCIDevice *dev)
{
    BusState *bus = qdev_get_parent_bus(DEVICE(dev));
    XilinxPCIEHost *s = XILINX_PCIE_HOST(bus->parent);

    pci_set_word(dev->config + PCI_COMMAND,
                 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
    pci_set_word(dev->config + PCI_MEMORY_BASE, s->mmio_base >> 16);
    pci_set_word(dev->config + PCI_MEMORY_LIMIT,
                 ((s->mmio_base + s->mmio_size - 1) >> 16) & 0xfff0);

    pci_bridge_initfn(dev, TYPE_PCI_BUS);

    if (pcie_endpoint_cap_v1_init(dev, 0x80) < 0) {
        hw_error("Failed to initialize PCIe capability");
    }

    return 0;
}

static void xilinx_pcie_root_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
    dc->desc = "Xilinx AXI-PCIe Host Bridge";
    k->vendor_id = PCI_VENDOR_ID_XILINX;
    k->device_id = 0x7021;
    k->revision = 0;
    k->class_id = PCI_CLASS_BRIDGE_HOST;
    k->is_express = true;
    k->is_bridge = true;
    k->init = xilinx_pcie_root_init;
    k->exit = pci_bridge_exitfn;
    dc->reset = pci_bridge_reset;
    k->config_read = xilinx_pcie_root_config_read;
    k->config_write = xilinx_pcie_root_config_write;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->user_creatable = false;
}

static const TypeInfo xilinx_pcie_root_info = {
    .name = TYPE_XILINX_PCIE_ROOT,
    .parent = TYPE_PCI_BRIDGE,
    .instance_size = sizeof(XilinxPCIERoot),
    .class_init = xilinx_pcie_root_class_init,
};

static void xilinx_pcie_register(void)
{
    type_register_static(&xilinx_pcie_root_info);
    type_register_static(&xilinx_pcie_host_info);
}

type_init(xilinx_pcie_register)
Commit	Line	Data
62be3934 PB	1	/*
	2	* Xilinx PCIe host controller emulation.
	3	*
	4	* Copyright (c) 2016 Imagination Technologies
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "qemu/osdep.h"
	21	#include "hw/pci/pci_bridge.h"
	22	#include "hw/pci-host/xilinx-pcie.h"
	23
	24	enum root_cfg_reg {
	25	/* Interrupt Decode Register */
	26	ROOTCFG_INTDEC = 0x138,
	27
	28	/* Interrupt Mask Register */
	29	ROOTCFG_INTMASK = 0x13c,
	30	/* INTx Interrupt Received */
	31	#define ROOTCFG_INTMASK_INTX (1 << 16)
	32	/* MSI Interrupt Received */
	33	#define ROOTCFG_INTMASK_MSI (1 << 17)
	34
	35	/* PHY Status/Control Register */
	36	ROOTCFG_PSCR = 0x144,
	37	/* Link Up */
	38	#define ROOTCFG_PSCR_LINK_UP (1 << 11)
	39
	40	/* Root Port Status/Control Register */
	41	ROOTCFG_RPSCR = 0x148,
	42	/* Bridge Enable */
	43	#define ROOTCFG_RPSCR_BRIDGEEN (1 << 0)
	44	/* Interrupt FIFO Not Empty */
	45	#define ROOTCFG_RPSCR_INTNEMPTY (1 << 18)
	46	/* Interrupt FIFO Overflow */
	47	#define ROOTCFG_RPSCR_INTOVF (1 << 19)
	48
	49	/* Root Port Interrupt FIFO Read Register 1 */
	50	ROOTCFG_RPIFR1 = 0x158,
	51	#define ROOTCFG_RPIFR1_INT_LANE_SHIFT 27
	52	#define ROOTCFG_RPIFR1_INT_ASSERT_SHIFT 29
	53	#define ROOTCFG_RPIFR1_INT_VALID_SHIFT 31
	54	/* Root Port Interrupt FIFO Read Register 2 */
	55	ROOTCFG_RPIFR2 = 0x15c,
	56	};
	57
	58	static void xilinx_pcie_update_intr(XilinxPCIEHost *s,
	59	uint32_t set, uint32_t clear)
	60	{
	61	int level;
	62
	63	s->intr \|= set;
	64	s->intr &= ~clear;
65
66	if (s->intr_fifo_r != s->intr_fifo_w) {
67	s->intr \|= ROOTCFG_INTMASK_INTX;
68	}
69
70	level = !!(s->intr & s->intr_mask);
71	qemu_set_irq(s->irq, level);
72	}
73
74	static void xilinx_pcie_queue_intr(XilinxPCIEHost *s,
75	uint32_t fifo_reg1, uint32_t fifo_reg2)
76	{
77	XilinxPCIEInt *intr;
78	unsigned int new_w;
79
80	new_w = (s->intr_fifo_w + 1) % ARRAY_SIZE(s->intr_fifo);
81	if (new_w == s->intr_fifo_r) {
82	s->rpscr \|= ROOTCFG_RPSCR_INTOVF;
83	return;
84	}
85
86	intr = &s->intr_fifo[s->intr_fifo_w];
87	s->intr_fifo_w = new_w;
88
89	intr->fifo_reg1 = fifo_reg1;
90	intr->fifo_reg2 = fifo_reg2;
91
92	xilinx_pcie_update_intr(s, ROOTCFG_INTMASK_INTX, 0);
93	}
94
95	static void xilinx_pcie_set_irq(void *opaque, int irq_num, int level)
96	{
97	XilinxPCIEHost *s = XILINX_PCIE_HOST(opaque);
98
99	xilinx_pcie_queue_intr(s,
100	(irq_num << ROOTCFG_RPIFR1_INT_LANE_SHIFT) \|
101	(level << ROOTCFG_RPIFR1_INT_ASSERT_SHIFT) \|
102	(1 << ROOTCFG_RPIFR1_INT_VALID_SHIFT),
103	0);
104	}
105
106	static void xilinx_pcie_host_realize(DeviceState dev, Error *errp)
107	{
108	PCIHostState *pci = PCI_HOST_BRIDGE(dev);
109	XilinxPCIEHost *s = XILINX_PCIE_HOST(dev);
110	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
111	PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
112
113	snprintf(s->name, sizeof(s->name), "pcie%u", s->bus_nr);
114
115	/* PCI configuration space */
116	pcie_host_mmcfg_init(pex, s->cfg_size);
117
118	/* MMIO region */
119	memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX);
120	memory_region_set_enabled(&s->mmio, false);
121
122	/* dummy I/O region */
1cfe48c1	123	memory_region_init_ram_nomigrate(&s->io, OBJECT(s), "io", 16, NULL);
62be3934 PB	124	memory_region_set_enabled(&s->io, false);
	125
	126	/* interrupt out */
	127	qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1);
	128
	129	sysbus_init_mmio(sbd, &pex->mmio);
	130	sysbus_init_mmio(sbd, &s->mmio);
	131
	132	pci->bus = pci_register_bus(dev, s->name, xilinx_pcie_set_irq,
	133	pci_swizzle_map_irq_fn, s, &s->mmio,
	134	&s->io, 0, 4, TYPE_PCIE_BUS);
	135
	136	qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus));
	137	qdev_init_nofail(DEVICE(&s->root));
	138	}
	139
	140	static const char xilinx_pcie_host_root_bus_path(PCIHostState host_bridge,
	141	PCIBus *rootbus)
	142	{
	143	return "0000:00";
	144	}
	145
	146	static void xilinx_pcie_host_init(Object *obj)
	147	{
	148	XilinxPCIEHost *s = XILINX_PCIE_HOST(obj);
	149	XilinxPCIERoot *root = &s->root;
	150
	151	object_initialize(root, sizeof(*root), TYPE_XILINX_PCIE_ROOT);
	152	object_property_add_child(obj, "root", OBJECT(root), NULL);
446de8b6	153	qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
62be3934 PB	154	qdev_prop_set_bit(DEVICE(root), "multifunction", false);
	155	}
	156
	157	static Property xilinx_pcie_host_props[] = {
	158	DEFINE_PROP_UINT32("bus_nr", XilinxPCIEHost, bus_nr, 0),
	159	DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0),
	160	DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 << 20),
	161	DEFINE_PROP_SIZE("mmio_base", XilinxPCIEHost, mmio_base, 0),
	162	DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 << 20),
	163	DEFINE_PROP_BOOL("link_up", XilinxPCIEHost, link_up, true),
	164	DEFINE_PROP_END_OF_LIST(),
	165	};
	166
	167	static void xilinx_pcie_host_class_init(ObjectClass klass, void data)
	168	{
	169	DeviceClass *dc = DEVICE_CLASS(klass);
	170	PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
	171
	172	hc->root_bus_path = xilinx_pcie_host_root_bus_path;
	173	dc->realize = xilinx_pcie_host_realize;
	174	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
	175	dc->fw_name = "pci";
	176	dc->props = xilinx_pcie_host_props;
	177	}
	178
	179	static const TypeInfo xilinx_pcie_host_info = {
	180	.name = TYPE_XILINX_PCIE_HOST,
	181	.parent = TYPE_PCIE_HOST_BRIDGE,
	182	.instance_size = sizeof(XilinxPCIEHost),
	183	.instance_init = xilinx_pcie_host_init,
	184	.class_init = xilinx_pcie_host_class_init,
	185	};
	186
	187	static uint32_t xilinx_pcie_root_config_read(PCIDevice *d,
	188	uint32_t address, int len)
	189	{
	190	XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent);
	191	uint32_t val;
	192
	193	switch (address) {
	194	case ROOTCFG_INTDEC:
	195	val = s->intr;
	196	break;
	197	case ROOTCFG_INTMASK:
	198	val = s->intr_mask;
	199	break;
	200	case ROOTCFG_PSCR:
	201	val = s->link_up ? ROOTCFG_PSCR_LINK_UP : 0;
	202	break;
	203	case ROOTCFG_RPSCR:
	204	if (s->intr_fifo_r != s->intr_fifo_w) {
	205	s->rpscr &= ~ROOTCFG_RPSCR_INTNEMPTY;
	206	} else {
	207	s->rpscr \|= ROOTCFG_RPSCR_INTNEMPTY;
	208	}
	209	val = s->rpscr;
	210	break;
	211	case ROOTCFG_RPIFR1:
	212	if (s->intr_fifo_w == s->intr_fifo_r) {
	213	/* FIFO empty */
	214	val = 0;
	215	} else {
	216	val = s->intr_fifo[s->intr_fifo_r].fifo_reg1;
	217	}
218	break;
219	case ROOTCFG_RPIFR2:
220	if (s->intr_fifo_w == s->intr_fifo_r) {
221	/* FIFO empty */
222	val = 0;
223	} else {
224	val = s->intr_fifo[s->intr_fifo_r].fifo_reg2;
225	}
226	break;
227	default:
228	val = pci_default_read_config(d, address, len);
229	break;
230	}
231	return val;
232	}
233
234	static void xilinx_pcie_root_config_write(PCIDevice *d, uint32_t address,
235	uint32_t val, int len)
236	{
237	XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent);
238	switch (address) {
239	case ROOTCFG_INTDEC:
240	xilinx_pcie_update_intr(s, 0, val);
241	break;
242	case ROOTCFG_INTMASK:
243	s->intr_mask = val;
244	xilinx_pcie_update_intr(s, 0, 0);
245	break;
246	case ROOTCFG_RPSCR:
247	s->rpscr &= ~ROOTCFG_RPSCR_BRIDGEEN;
248	s->rpscr \|= val & ROOTCFG_RPSCR_BRIDGEEN;
249	memory_region_set_enabled(&s->mmio, val & ROOTCFG_RPSCR_BRIDGEEN);
250
251	if (val & ROOTCFG_INTMASK_INTX) {
252	s->rpscr &= ~ROOTCFG_INTMASK_INTX;
253	}
254	break;
255	case ROOTCFG_RPIFR1:
256	case ROOTCFG_RPIFR2:
257	if (s->intr_fifo_w == s->intr_fifo_r) {
258	/* FIFO empty */
259	return;
260	} else {
261	s->intr_fifo_r = (s->intr_fifo_r + 1) % ARRAY_SIZE(s->intr_fifo);
262	}
263	break;
264	default:
265	pci_default_write_config(d, address, val, len);
266	break;
267	}
268	}
269
270	static int xilinx_pcie_root_init(PCIDevice *dev)
271	{
272	BusState *bus = qdev_get_parent_bus(DEVICE(dev));
273	XilinxPCIEHost *s = XILINX_PCIE_HOST(bus->parent);
274
275	pci_set_word(dev->config + PCI_COMMAND,
276	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
277	pci_set_word(dev->config + PCI_MEMORY_BASE, s->mmio_base >> 16);
278	pci_set_word(dev->config + PCI_MEMORY_LIMIT,
279	((s->mmio_base + s->mmio_size - 1) >> 16) & 0xfff0);
280
281	pci_bridge_initfn(dev, TYPE_PCI_BUS);
282
283	if (pcie_endpoint_cap_v1_init(dev, 0x80) < 0) {
284	hw_error("Failed to initialize PCIe capability");
285	}
286
287	return 0;
288	}
289
290	static void xilinx_pcie_root_class_init(ObjectClass klass, void data)
291	{
292	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
293	DeviceClass *dc = DEVICE_CLASS(klass);
294
295	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
296	dc->desc = "Xilinx AXI-PCIe Host Bridge";
297	k->vendor_id = PCI_VENDOR_ID_XILINX;
298	k->device_id = 0x7021;
299	k->revision = 0;
300	k->class_id = PCI_CLASS_BRIDGE_HOST;
301	k->is_express = true;
302	k->is_bridge = true;
303	k->init = xilinx_pcie_root_init;
304	k->exit = pci_bridge_exitfn;
305	dc->reset = pci_bridge_reset;
306	k->config_read = xilinx_pcie_root_config_read;
307	k->config_write = xilinx_pcie_root_config_write;
308	/*
309	* PCI-facing part of the host bridge, not usable without the
310	* host-facing part, which can't be device_add'ed, yet.
311	*/
e90f2a8c	312	dc->user_creatable = false;
62be3934 PB	313	}
	314
	315	static const TypeInfo xilinx_pcie_root_info = {
	316	.name = TYPE_XILINX_PCIE_ROOT,
	317	.parent = TYPE_PCI_BRIDGE,
	318	.instance_size = sizeof(XilinxPCIERoot),
	319	.class_init = xilinx_pcie_root_class_init,
	320	};
	321
	322	static void xilinx_pcie_register(void)
	323	{
	324	type_register_static(&xilinx_pcie_root_info);
	325	type_register_static(&xilinx_pcie_host_info);
	326	}
	327
	328	type_init(xilinx_pcie_register)