[qemu.git] / hw / misc / pci-testdev.c

/*
 * QEMU PCI test device
 *
 * Copyright (c) 2012 Red Hat Inc.
 * Author: Michael S. Tsirkin <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/pci/pci.h"
#include "qemu/event_notifier.h"
#include "sysemu/kvm.h"

typedef struct PCITestDevHdr {
    uint8_t test;
    uint8_t width;
    uint8_t pad0[2];
    uint32_t offset;
    uint8_t data;
    uint8_t pad1[3];
    uint32_t count;
    uint8_t name[];
} PCITestDevHdr;

typedef struct IOTest {
    MemoryRegion *mr;
    EventNotifier notifier;
    bool hasnotifier;
    unsigned size;
    bool match_data;
    PCITestDevHdr *hdr;
    unsigned bufsize;
} IOTest;

#define IOTEST_DATAMATCH 0xFA
#define IOTEST_NOMATCH   0xCE

#define IOTEST_IOSIZE 128
#define IOTEST_MEMSIZE 2048

static const char *iotest_test[] = {
    "no-eventfd",
    "wildcard-eventfd",
    "datamatch-eventfd"
};

static const char *iotest_type[] = {
    "mmio",
    "portio"
};

#define IOTEST_TEST(i) (iotest_test[((i) % ARRAY_SIZE(iotest_test))])
#define IOTEST_TYPE(i) (iotest_type[((i) / ARRAY_SIZE(iotest_test))])
#define IOTEST_MAX_TEST (ARRAY_SIZE(iotest_test))
#define IOTEST_MAX_TYPE (ARRAY_SIZE(iotest_type))
#define IOTEST_MAX (IOTEST_MAX_TEST * IOTEST_MAX_TYPE)

enum {
    IOTEST_ACCESS_NAME,
    IOTEST_ACCESS_DATA,
    IOTEST_ACCESS_MAX,
};

#define IOTEST_ACCESS_TYPE uint8_t
#define IOTEST_ACCESS_WIDTH (sizeof(uint8_t))

typedef struct PCITestDevState {
    /*< private >*/
    PCIDevice parent_obj;
    /*< public >*/

    MemoryRegion mmio;
    MemoryRegion portio;
    IOTest *tests;
    int current;
} PCITestDevState;

#define TYPE_PCI_TEST_DEV "pci-testdev"

#define PCI_TEST_DEV(obj) \
    OBJECT_CHECK(PCITestDevState, (obj), TYPE_PCI_TEST_DEV)

#define IOTEST_IS_MEM(i) (strcmp(IOTEST_TYPE(i), "portio"))
#define IOTEST_REGION(d, i) (IOTEST_IS_MEM(i) ?  &(d)->mmio : &(d)->portio)
#define IOTEST_SIZE(i) (IOTEST_IS_MEM(i) ? IOTEST_MEMSIZE : IOTEST_IOSIZE)
#define IOTEST_PCI_BAR(i) (IOTEST_IS_MEM(i) ? PCI_BASE_ADDRESS_SPACE_MEMORY : \
                           PCI_BASE_ADDRESS_SPACE_IO)

static int pci_testdev_start(IOTest *test)
{
    test->hdr->count = 0;
    if (!test->hasnotifier) {
        return 0;
    }
    event_notifier_test_and_clear(&test->notifier);
    memory_region_add_eventfd(test->mr,
                              le32_to_cpu(test->hdr->offset),
                              test->size,
                              test->match_data,
                              test->hdr->data,
                              &test->notifier);
    return 0;
}

static void pci_testdev_stop(IOTest *test)
{
    if (!test->hasnotifier) {
        return;
    }
    memory_region_del_eventfd(test->mr,
                              le32_to_cpu(test->hdr->offset),
                              test->size,
                              test->match_data,
                              test->hdr->data,
                              &test->notifier);
}

static void
pci_testdev_reset(PCITestDevState *d)
{
    if (d->current == -1) {
        return;
    }
    pci_testdev_stop(&d->tests[d->current]);
    d->current = -1;
}

static void pci_testdev_inc(IOTest *test, unsigned inc)
{
    uint32_t c = le32_to_cpu(test->hdr->count);
    test->hdr->count = cpu_to_le32(c + inc);
}

static void
pci_testdev_write(void *opaque, hwaddr addr, uint64_t val,
                  unsigned size, int type)
{
    PCITestDevState *d = opaque;
    IOTest *test;
    int t, r;

    if (addr == offsetof(PCITestDevHdr, test)) {
        pci_testdev_reset(d);
        if (val >= IOTEST_MAX_TEST) {
            return;
        }
        t = type * IOTEST_MAX_TEST + val;
        r = pci_testdev_start(&d->tests[t]);
        if (r < 0) {
            return;
        }
        d->current = t;
        return;
    }
    if (d->current < 0) {
        return;
    }
    test = &d->tests[d->current];
    if (addr != le32_to_cpu(test->hdr->offset)) {
        return;
    }
    if (test->match_data && test->size != size) {
        return;
    }
    if (test->match_data && val != test->hdr->data) {
        return;
    }
    pci_testdev_inc(test, 1);
}

static uint64_t
pci_testdev_read(void *opaque, hwaddr addr, unsigned size)
{
    PCITestDevState *d = opaque;
    const char *buf;
    IOTest *test;
    if (d->current < 0) {
        return 0;
    }
    test = &d->tests[d->current];
    buf = (const char *)test->hdr;
    if (addr + size >= test->bufsize) {
        return 0;
    }
    if (test->hasnotifier) {
        event_notifier_test_and_clear(&test->notifier);
    }
    return buf[addr];
}

static void
pci_testdev_mmio_write(void *opaque, hwaddr addr, uint64_t val,
                       unsigned size)
{
    pci_testdev_write(opaque, addr, val, size, 0);
}

static void
pci_testdev_pio_write(void *opaque, hwaddr addr, uint64_t val,
                       unsigned size)
{
    pci_testdev_write(opaque, addr, val, size, 1);
}

static const MemoryRegionOps pci_testdev_mmio_ops = {
    .read = pci_testdev_read,
    .write = pci_testdev_mmio_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
};

static const MemoryRegionOps pci_testdev_pio_ops = {
    .read = pci_testdev_read,
    .write = pci_testdev_pio_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
};

static void pci_testdev_realize(PCIDevice *pci_dev, Error **errp)
{
    PCITestDevState *d = PCI_TEST_DEV(pci_dev);
    uint8_t *pci_conf;
    char *name;
    int r, i;
    bool fastmmio = kvm_ioeventfd_any_length_enabled();

    pci_conf = pci_dev->config;

    pci_conf[PCI_INTERRUPT_PIN] = 0; /* no interrupt pin */

    memory_region_init_io(&d->mmio, OBJECT(d), &pci_testdev_mmio_ops, d,
                          "pci-testdev-mmio", IOTEST_MEMSIZE * 2);
    memory_region_init_io(&d->portio, OBJECT(d), &pci_testdev_pio_ops, d,
                          "pci-testdev-portio", IOTEST_IOSIZE * 2);
    pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
    pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->portio);

    d->current = -1;
    d->tests = g_malloc0(IOTEST_MAX * sizeof *d->tests);
    for (i = 0; i < IOTEST_MAX; ++i) {
        IOTest *test = &d->tests[i];
        name = g_strdup_printf("%s-%s", IOTEST_TYPE(i), IOTEST_TEST(i));
        test->bufsize = sizeof(PCITestDevHdr) + strlen(name) + 1;
        test->hdr = g_malloc0(test->bufsize);
        memcpy(test->hdr->name, name, strlen(name) + 1);
        g_free(name);
        test->hdr->offset = cpu_to_le32(IOTEST_SIZE(i) + i * IOTEST_ACCESS_WIDTH);
        test->match_data = strcmp(IOTEST_TEST(i), "wildcard-eventfd");
        if (fastmmio && IOTEST_IS_MEM(i) && !test->match_data) {
            test->size = 0;
        } else {
            test->size = IOTEST_ACCESS_WIDTH;
        }
        test->hdr->test = i;
        test->hdr->data = test->match_data ? IOTEST_DATAMATCH : IOTEST_NOMATCH;
        test->hdr->width = IOTEST_ACCESS_WIDTH;
        test->mr = IOTEST_REGION(d, i);
        if (!strcmp(IOTEST_TEST(i), "no-eventfd")) {
            test->hasnotifier = false;
            continue;
        }
        r = event_notifier_init(&test->notifier, 0);
        assert(r >= 0);
        test->hasnotifier = true;
    }
}

static void
pci_testdev_uninit(PCIDevice *dev)
{
    PCITestDevState *d = PCI_TEST_DEV(dev);
    int i;

    pci_testdev_reset(d);
    for (i = 0; i < IOTEST_MAX; ++i) {
        if (d->tests[i].hasnotifier) {
            event_notifier_cleanup(&d->tests[i].notifier);
        }
        g_free(d->tests[i].hdr);
    }
    g_free(d->tests);
}

static void qdev_pci_testdev_reset(DeviceState *dev)
{
    PCITestDevState *d = PCI_TEST_DEV(dev);
    pci_testdev_reset(d);
}

static void pci_testdev_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = pci_testdev_realize;
    k->exit = pci_testdev_uninit;
    k->vendor_id = PCI_VENDOR_ID_REDHAT;
    k->device_id = PCI_DEVICE_ID_REDHAT_TEST;
    k->revision = 0x00;
    k->class_id = PCI_CLASS_OTHERS;
    dc->desc = "PCI Test Device";
    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
    dc->reset = qdev_pci_testdev_reset;
}

static const TypeInfo pci_testdev_info = {
    .name          = TYPE_PCI_TEST_DEV,
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCITestDevState),
    .class_init    = pci_testdev_class_init,
};

static void pci_testdev_register_types(void)
{
    type_register_static(&pci_testdev_info);
}

type_init(pci_testdev_register_types)
Commit	Line	Data
22773d60 MT	1	/*
	2	* QEMU PCI test device
	3	*
	4	* Copyright (c) 2012 Red Hat Inc.
	5	* Author: Michael S. Tsirkin <[email protected]>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along
	18	* with this program; if not, see <http://www.gnu.org/licenses/>.
	19	*/
97d5408f	20	#include "qemu/osdep.h"
22773d60 MT	21	#include "hw/hw.h"
	22	#include "hw/pci/pci.h"
	23	#include "qemu/event_notifier.h"
77ac58dd	24	#include "sysemu/kvm.h"
22773d60 MT	25
	26	typedef struct PCITestDevHdr {
	27	uint8_t test;
	28	uint8_t width;
	29	uint8_t pad0[2];
	30	uint32_t offset;
	31	uint8_t data;
	32	uint8_t pad1[3];
	33	uint32_t count;
	34	uint8_t name[];
	35	} PCITestDevHdr;
	36
	37	typedef struct IOTest {
	38	MemoryRegion *mr;
	39	EventNotifier notifier;
	40	bool hasnotifier;
	41	unsigned size;
	42	bool match_data;
	43	PCITestDevHdr *hdr;
	44	unsigned bufsize;
	45	} IOTest;
	46
	47	#define IOTEST_DATAMATCH 0xFA
	48	#define IOTEST_NOMATCH 0xCE
	49
	50	#define IOTEST_IOSIZE 128
	51	#define IOTEST_MEMSIZE 2048
	52
	53	static const char *iotest_test[] = {
	54	"no-eventfd",
	55	"wildcard-eventfd",
	56	"datamatch-eventfd"
	57	};
	58
	59	static const char *iotest_type[] = {
	60	"mmio",
	61	"portio"
	62	};
	63
	64	#define IOTEST_TEST(i) (iotest_test[((i) % ARRAY_SIZE(iotest_test))])
	65	#define IOTEST_TYPE(i) (iotest_type[((i) / ARRAY_SIZE(iotest_test))])
	66	#define IOTEST_MAX_TEST (ARRAY_SIZE(iotest_test))
	67	#define IOTEST_MAX_TYPE (ARRAY_SIZE(iotest_type))
	68	#define IOTEST_MAX (IOTEST_MAX_TEST * IOTEST_MAX_TYPE)
	69
	70	enum {
	71	IOTEST_ACCESS_NAME,
	72	IOTEST_ACCESS_DATA,
	73	IOTEST_ACCESS_MAX,
	74	};
	75
	76	#define IOTEST_ACCESS_TYPE uint8_t
	77	#define IOTEST_ACCESS_WIDTH (sizeof(uint8_t))
	78
	79	typedef struct PCITestDevState {
6d27a409 AF	80	/< private >/
	81	PCIDevice parent_obj;
	82	/< public >/
	83
22773d60 MT	84	MemoryRegion mmio;
	85	MemoryRegion portio;
	86	IOTest *tests;
	87	int current;
	88	} PCITestDevState;
	89
40108d0a PC	90	#define TYPE_PCI_TEST_DEV "pci-testdev"
	91
	92	#define PCI_TEST_DEV(obj) \
	93	OBJECT_CHECK(PCITestDevState, (obj), TYPE_PCI_TEST_DEV)
	94
22773d60 MT	95	#define IOTEST_IS_MEM(i) (strcmp(IOTEST_TYPE(i), "portio"))
	96	#define IOTEST_REGION(d, i) (IOTEST_IS_MEM(i) ? &(d)->mmio : &(d)->portio)
	97	#define IOTEST_SIZE(i) (IOTEST_IS_MEM(i) ? IOTEST_MEMSIZE : IOTEST_IOSIZE)
	98	#define IOTEST_PCI_BAR(i) (IOTEST_IS_MEM(i) ? PCI_BASE_ADDRESS_SPACE_MEMORY : \
	99	PCI_BASE_ADDRESS_SPACE_IO)
	100
	101	static int pci_testdev_start(IOTest *test)
	102	{
	103	test->hdr->count = 0;
	104	if (!test->hasnotifier) {
	105	return 0;
	106	}
	107	event_notifier_test_and_clear(&test->notifier);
	108	memory_region_add_eventfd(test->mr,
	109	le32_to_cpu(test->hdr->offset),
	110	test->size,
	111	test->match_data,
	112	test->hdr->data,
	113	&test->notifier);
	114	return 0;
	115	}
	116
	117	static void pci_testdev_stop(IOTest *test)
	118	{
	119	if (!test->hasnotifier) {
	120	return;
	121	}
	122	memory_region_del_eventfd(test->mr,
	123	le32_to_cpu(test->hdr->offset),
	124	test->size,
	125	test->match_data,
	126	test->hdr->data,
	127	&test->notifier);
	128	}
	129
	130	static void
	131	pci_testdev_reset(PCITestDevState *d)
	132	{
	133	if (d->current == -1) {
	134	return;
	135	}
	136	pci_testdev_stop(&d->tests[d->current]);
	137	d->current = -1;
	138	}
	139
	140	static void pci_testdev_inc(IOTest *test, unsigned inc)
	141	{
	142	uint32_t c = le32_to_cpu(test->hdr->count);
	143	test->hdr->count = cpu_to_le32(c + inc);
	144	}
	145
	146	static void
	147	pci_testdev_write(void *opaque, hwaddr addr, uint64_t val,
	148	unsigned size, int type)
	149	{
	150	PCITestDevState *d = opaque;
	151	IOTest *test;
	152	int t, r;
	153
	154	if (addr == offsetof(PCITestDevHdr, test)) {
	155	pci_testdev_reset(d);
	156	if (val >= IOTEST_MAX_TEST) {
	157	return;
	158	}
159	t = type * IOTEST_MAX_TEST + val;
160	r = pci_testdev_start(&d->tests[t]);
161	if (r < 0) {
162	return;
163	}
164	d->current = t;
165	return;
166	}
167	if (d->current < 0) {
168	return;
169	}
170	test = &d->tests[d->current];
171	if (addr != le32_to_cpu(test->hdr->offset)) {
172	return;
173	}
174	if (test->match_data && test->size != size) {
175	return;
176	}
177	if (test->match_data && val != test->hdr->data) {
178	return;
179	}
180	pci_testdev_inc(test, 1);
181	}
182
183	static uint64_t
184	pci_testdev_read(void *opaque, hwaddr addr, unsigned size)
185	{
186	PCITestDevState *d = opaque;
187	const char *buf;
188	IOTest *test;
189	if (d->current < 0) {
190	return 0;
191	}
192	test = &d->tests[d->current];
193	buf = (const char *)test->hdr;
194	if (addr + size >= test->bufsize) {
195	return 0;
196	}
197	if (test->hasnotifier) {
198	event_notifier_test_and_clear(&test->notifier);
199	}
200	return buf[addr];
201	}
202
203	static void
204	pci_testdev_mmio_write(void *opaque, hwaddr addr, uint64_t val,
205	unsigned size)
206	{
207	pci_testdev_write(opaque, addr, val, size, 0);
208	}
209
210	static void
211	pci_testdev_pio_write(void *opaque, hwaddr addr, uint64_t val,
212	unsigned size)
213	{
214	pci_testdev_write(opaque, addr, val, size, 1);
215	}
216
217	static const MemoryRegionOps pci_testdev_mmio_ops = {
218	.read = pci_testdev_read,
219	.write = pci_testdev_mmio_write,
220	.endianness = DEVICE_LITTLE_ENDIAN,
221	.impl = {
222	.min_access_size = 1,
223	.max_access_size = 1,
224	},
225	};
226
227	static const MemoryRegionOps pci_testdev_pio_ops = {
228	.read = pci_testdev_read,
229	.write = pci_testdev_pio_write,
230	.endianness = DEVICE_LITTLE_ENDIAN,
231	.impl = {
232	.min_access_size = 1,
233	.max_access_size = 1,
234	},
235	};
236
9af21dbe	237	static void pci_testdev_realize(PCIDevice pci_dev, Error *errp)
22773d60	238	{
40108d0a	239	PCITestDevState *d = PCI_TEST_DEV(pci_dev);
22773d60 MT	240	uint8_t *pci_conf;
	241	char *name;
	242	int r, i;
45aa4e8e	243	bool fastmmio = kvm_ioeventfd_any_length_enabled();
22773d60	244
6d27a409	245	pci_conf = pci_dev->config;
22773d60 MT	246
	247	pci_conf[PCI_INTERRUPT_PIN] = 0; /* no interrupt pin */
	248
3c161542	249	memory_region_init_io(&d->mmio, OBJECT(d), &pci_testdev_mmio_ops, d,
22773d60	250	"pci-testdev-mmio", IOTEST_MEMSIZE * 2);
3c161542	251	memory_region_init_io(&d->portio, OBJECT(d), &pci_testdev_pio_ops, d,
22773d60	252	"pci-testdev-portio", IOTEST_IOSIZE * 2);
6d27a409 AF	253	pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
6d27a409 AF	254	pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->portio);
22773d60 MT	255
	256	d->current = -1;
	257	d->tests = g_malloc0(IOTEST_MAX * sizeof *d->tests);
	258	for (i = 0; i < IOTEST_MAX; ++i) {
	259	IOTest *test = &d->tests[i];
	260	name = g_strdup_printf("%s-%s", IOTEST_TYPE(i), IOTEST_TEST(i));
	261	test->bufsize = sizeof(PCITestDevHdr) + strlen(name) + 1;
	262	test->hdr = g_malloc0(test->bufsize);
	263	memcpy(test->hdr->name, name, strlen(name) + 1);
	264	g_free(name);
	265	test->hdr->offset = cpu_to_le32(IOTEST_SIZE(i) + i * IOTEST_ACCESS_WIDTH);
22773d60	266	test->match_data = strcmp(IOTEST_TEST(i), "wildcard-eventfd");
45aa4e8e MT	267	if (fastmmio && IOTEST_IS_MEM(i) && !test->match_data) {
	268	test->size = 0;
	269	} else {
	270	test->size = IOTEST_ACCESS_WIDTH;
	271	}
22773d60 MT	272	test->hdr->test = i;
	273	test->hdr->data = test->match_data ? IOTEST_DATAMATCH : IOTEST_NOMATCH;
	274	test->hdr->width = IOTEST_ACCESS_WIDTH;
	275	test->mr = IOTEST_REGION(d, i);
	276	if (!strcmp(IOTEST_TEST(i), "no-eventfd")) {
	277	test->hasnotifier = false;
	278	continue;
	279	}
	280	r = event_notifier_init(&test->notifier, 0);
	281	assert(r >= 0);
	282	test->hasnotifier = true;
	283	}
22773d60 MT	284	}
	285
	286	static void
	287	pci_testdev_uninit(PCIDevice *dev)
	288	{
40108d0a	289	PCITestDevState *d = PCI_TEST_DEV(dev);
22773d60 MT	290	int i;
	291
	292	pci_testdev_reset(d);
	293	for (i = 0; i < IOTEST_MAX; ++i) {
	294	if (d->tests[i].hasnotifier) {
	295	event_notifier_cleanup(&d->tests[i].notifier);
	296	}
	297	g_free(d->tests[i].hdr);
	298	}
	299	g_free(d->tests);
22773d60 MT	300	}
	301
	302	static void qdev_pci_testdev_reset(DeviceState *dev)
	303	{
40108d0a	304	PCITestDevState *d = PCI_TEST_DEV(dev);
22773d60 MT	305	pci_testdev_reset(d);
	306	}
	307
	308	static void pci_testdev_class_init(ObjectClass klass, void data)
	309	{
	310	DeviceClass *dc = DEVICE_CLASS(klass);
	311	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	312
9af21dbe	313	k->realize = pci_testdev_realize;
22773d60 MT	314	k->exit = pci_testdev_uninit;
	315	k->vendor_id = PCI_VENDOR_ID_REDHAT;
	316	k->device_id = PCI_DEVICE_ID_REDHAT_TEST;
	317	k->revision = 0x00;
	318	k->class_id = PCI_CLASS_OTHERS;
	319	dc->desc = "PCI Test Device";
125ee0ed	320	set_bit(DEVICE_CATEGORY_MISC, dc->categories);
22773d60 MT	321	dc->reset = qdev_pci_testdev_reset;
	322	}
	323
	324	static const TypeInfo pci_testdev_info = {
40108d0a	325	.name = TYPE_PCI_TEST_DEV,
22773d60 MT	326	.parent = TYPE_PCI_DEVICE,
	327	.instance_size = sizeof(PCITestDevState),
	328	.class_init = pci_testdev_class_init,
	329	};
	330
	331	static void pci_testdev_register_types(void)
	332	{
	333	type_register_static(&pci_testdev_info);
	334	}
	335
	336	type_init(pci_testdev_register_types)