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Commit | Line | Data |
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5fafdf24 | 1 | /* |
423f0742 PB |
2 | * General purpose implementation of a simple periodic countdown timer. |
3 | * | |
4 | * Copyright (c) 2007 CodeSourcery. | |
5 | * | |
8e31bf38 | 6 | * This code is licensed under the GNU LGPL. |
423f0742 | 7 | */ |
18c86e2b | 8 | #include "qemu/osdep.h" |
83c9f4ca | 9 | #include "hw/hw.h" |
1de7afc9 | 10 | #include "qemu/timer.h" |
83c9f4ca | 11 | #include "hw/ptimer.h" |
1de7afc9 | 12 | #include "qemu/host-utils.h" |
8a354bd9 | 13 | #include "sysemu/replay.h" |
2a8b5870 | 14 | #include "sysemu/qtest.h" |
072bdb07 | 15 | #include "block/aio.h" |
d2528bdc | 16 | #include "sysemu/cpus.h" |
423f0742 | 17 | |
22471b8a DO |
18 | #define DELTA_ADJUST 1 |
19 | #define DELTA_NO_ADJUST -1 | |
2b5c0322 | 20 | |
423f0742 PB |
21 | struct ptimer_state |
22 | { | |
852f771e | 23 | uint8_t enabled; /* 0 = disabled, 1 = periodic, 2 = oneshot. */ |
8d05ea8a BS |
24 | uint64_t limit; |
25 | uint64_t delta; | |
423f0742 PB |
26 | uint32_t period_frac; |
27 | int64_t period; | |
28 | int64_t last_event; | |
29 | int64_t next_event; | |
e7ea81c3 | 30 | uint8_t policy_mask; |
423f0742 PB |
31 | QEMUBH *bh; |
32 | QEMUTimer *timer; | |
33 | }; | |
34 | ||
35 | /* Use a bottom-half routine to avoid reentrancy issues. */ | |
36 | static void ptimer_trigger(ptimer_state *s) | |
37 | { | |
38 | if (s->bh) { | |
8a354bd9 | 39 | replay_bh_schedule_event(s->bh); |
423f0742 PB |
40 | } |
41 | } | |
42 | ||
2b5c0322 | 43 | static void ptimer_reload(ptimer_state *s, int delta_adjust) |
423f0742 | 44 | { |
e91171e3 DO |
45 | uint32_t period_frac = s->period_frac; |
46 | uint64_t period = s->period; | |
2b5c0322 | 47 | uint64_t delta = s->delta; |
e91171e3 | 48 | |
22471b8a | 49 | if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) { |
423f0742 | 50 | ptimer_trigger(s); |
22471b8a DO |
51 | } |
52 | ||
3f6e6a13 | 53 | if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_RELOAD)) { |
2b5c0322 | 54 | delta = s->delta = s->limit; |
423f0742 | 55 | } |
ef0a9984 DO |
56 | |
57 | if (s->period == 0) { | |
2a8b5870 DO |
58 | if (!qtest_enabled()) { |
59 | fprintf(stderr, "Timer with period zero, disabling\n"); | |
60 | } | |
780d23e5 | 61 | timer_del(s->timer); |
423f0742 PB |
62 | s->enabled = 0; |
63 | return; | |
64 | } | |
65 | ||
2b5c0322 | 66 | if (s->policy_mask & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD) { |
22471b8a DO |
67 | if (delta_adjust != DELTA_NO_ADJUST) { |
68 | delta += delta_adjust; | |
69 | } | |
2b5c0322 DO |
70 | } |
71 | ||
ef0a9984 DO |
72 | if (delta == 0 && (s->policy_mask & PTIMER_POLICY_CONTINUOUS_TRIGGER)) { |
73 | if (s->enabled == 1 && s->limit == 0) { | |
74 | delta = 1; | |
75 | } | |
76 | } | |
77 | ||
22471b8a DO |
78 | if (delta == 0 && (s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) { |
79 | if (delta_adjust != DELTA_NO_ADJUST) { | |
80 | delta = 1; | |
81 | } | |
82 | } | |
83 | ||
3f6e6a13 DO |
84 | if (delta == 0 && (s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_RELOAD)) { |
85 | if (s->enabled == 1 && s->limit != 0) { | |
86 | delta = 1; | |
87 | } | |
88 | } | |
89 | ||
ef0a9984 DO |
90 | if (delta == 0) { |
91 | if (!qtest_enabled()) { | |
92 | fprintf(stderr, "Timer with delta zero, disabling\n"); | |
93 | } | |
94 | timer_del(s->timer); | |
95 | s->enabled = 0; | |
96 | return; | |
97 | } | |
98 | ||
e91171e3 DO |
99 | /* |
100 | * Artificially limit timeout rate to something | |
101 | * achievable under QEMU. Otherwise, QEMU spends all | |
102 | * its time generating timer interrupts, and there | |
103 | * is no forward progress. | |
104 | * About ten microseconds is the fastest that really works | |
105 | * on the current generation of host machines. | |
106 | */ | |
107 | ||
2b5c0322 DO |
108 | if (s->enabled == 1 && (delta * period < 10000) && !use_icount) { |
109 | period = 10000 / delta; | |
e91171e3 DO |
110 | period_frac = 0; |
111 | } | |
112 | ||
423f0742 | 113 | s->last_event = s->next_event; |
2b5c0322 | 114 | s->next_event = s->last_event + delta * period; |
e91171e3 | 115 | if (period_frac) { |
2b5c0322 | 116 | s->next_event += ((int64_t)period_frac * delta) >> 32; |
423f0742 | 117 | } |
bc72ad67 | 118 | timer_mod(s->timer, s->next_event); |
423f0742 PB |
119 | } |
120 | ||
121 | static void ptimer_tick(void *opaque) | |
122 | { | |
123 | ptimer_state *s = (ptimer_state *)opaque; | |
3f6e6a13 DO |
124 | bool trigger = true; |
125 | ||
423f0742 | 126 | if (s->enabled == 2) { |
3f6e6a13 | 127 | s->delta = 0; |
423f0742 PB |
128 | s->enabled = 0; |
129 | } else { | |
ef0a9984 DO |
130 | int delta_adjust = DELTA_ADJUST; |
131 | ||
3f6e6a13 | 132 | if (s->delta == 0 || s->limit == 0) { |
ef0a9984 | 133 | /* If a "continuous trigger" policy is not used and limit == 0, |
3f6e6a13 DO |
134 | we should error out. delta == 0 means that this tick is |
135 | caused by a "no immediate reload" policy, so it shouldn't | |
136 | be adjusted. */ | |
22471b8a | 137 | delta_adjust = DELTA_NO_ADJUST; |
ef0a9984 DO |
138 | } |
139 | ||
3f6e6a13 DO |
140 | if (!(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) { |
141 | /* Avoid re-trigger on deferred reload if "no immediate trigger" | |
142 | policy isn't used. */ | |
143 | trigger = (delta_adjust == DELTA_ADJUST); | |
144 | } | |
145 | ||
146 | s->delta = s->limit; | |
147 | ||
ef0a9984 | 148 | ptimer_reload(s, delta_adjust); |
423f0742 | 149 | } |
3f6e6a13 DO |
150 | |
151 | if (trigger) { | |
152 | ptimer_trigger(s); | |
153 | } | |
423f0742 PB |
154 | } |
155 | ||
8d05ea8a | 156 | uint64_t ptimer_get_count(ptimer_state *s) |
423f0742 | 157 | { |
8d05ea8a | 158 | uint64_t counter; |
423f0742 | 159 | |
ef0a9984 | 160 | if (s->enabled && s->delta != 0) { |
5a50307b DO |
161 | int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
162 | int64_t next = s->next_event; | |
2b5c0322 | 163 | int64_t last = s->last_event; |
5a50307b DO |
164 | bool expired = (now - next >= 0); |
165 | bool oneshot = (s->enabled == 2); | |
166 | ||
423f0742 | 167 | /* Figure out the current counter value. */ |
56215da3 | 168 | if (expired) { |
423f0742 PB |
169 | /* Prevent timer underflowing if it should already have |
170 | triggered. */ | |
171 | counter = 0; | |
172 | } else { | |
8d05ea8a BS |
173 | uint64_t rem; |
174 | uint64_t div; | |
d0a981b2 PB |
175 | int clz1, clz2; |
176 | int shift; | |
e91171e3 DO |
177 | uint32_t period_frac = s->period_frac; |
178 | uint64_t period = s->period; | |
179 | ||
5a50307b | 180 | if (!oneshot && (s->delta * period < 10000) && !use_icount) { |
e91171e3 DO |
181 | period = 10000 / s->delta; |
182 | period_frac = 0; | |
183 | } | |
d0a981b2 PB |
184 | |
185 | /* We need to divide time by period, where time is stored in | |
186 | rem (64-bit integer) and period is stored in period/period_frac | |
187 | (64.32 fixed point). | |
2b5c0322 | 188 | |
d0a981b2 PB |
189 | Doing full precision division is hard, so scale values and |
190 | do a 64-bit division. The result should be rounded down, | |
191 | so that the rounding error never causes the timer to go | |
192 | backwards. | |
193 | */ | |
423f0742 | 194 | |
56215da3 | 195 | rem = next - now; |
e91171e3 | 196 | div = period; |
d0a981b2 PB |
197 | |
198 | clz1 = clz64(rem); | |
199 | clz2 = clz64(div); | |
200 | shift = clz1 < clz2 ? clz1 : clz2; | |
201 | ||
202 | rem <<= shift; | |
203 | div <<= shift; | |
204 | if (shift >= 32) { | |
e91171e3 | 205 | div |= ((uint64_t)period_frac << (shift - 32)); |
d0a981b2 PB |
206 | } else { |
207 | if (shift != 0) | |
e91171e3 | 208 | div |= (period_frac >> (32 - shift)); |
d0a981b2 PB |
209 | /* Look at remaining bits of period_frac and round div up if |
210 | necessary. */ | |
e91171e3 | 211 | if ((uint32_t)(period_frac << shift)) |
d0a981b2 PB |
212 | div += 1; |
213 | } | |
423f0742 | 214 | counter = rem / div; |
2b5c0322 DO |
215 | |
216 | if (s->policy_mask & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD) { | |
217 | /* Before wrapping around, timer should stay with counter = 0 | |
218 | for a one period. */ | |
219 | if (!oneshot && s->delta == s->limit) { | |
220 | if (now == last) { | |
221 | /* Counter == delta here, check whether it was | |
222 | adjusted and if it was, then right now it is | |
223 | that "one period". */ | |
224 | if (counter == s->limit + DELTA_ADJUST) { | |
225 | return 0; | |
226 | } | |
227 | } else if (counter == s->limit) { | |
228 | /* Since the counter is rounded down and now != last, | |
229 | the counter == limit means that delta was adjusted | |
230 | by +1 and right now it is that adjusted period. */ | |
231 | return 0; | |
232 | } | |
233 | } | |
234 | } | |
423f0742 | 235 | } |
5580ea45 DO |
236 | |
237 | if (s->policy_mask & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN) { | |
238 | /* If now == last then delta == limit, i.e. the counter already | |
239 | represents the correct value. It would be rounded down a 1ns | |
240 | later. */ | |
241 | if (now != last) { | |
242 | counter += 1; | |
243 | } | |
244 | } | |
423f0742 PB |
245 | } else { |
246 | counter = s->delta; | |
247 | } | |
248 | return counter; | |
249 | } | |
250 | ||
8d05ea8a | 251 | void ptimer_set_count(ptimer_state *s, uint64_t count) |
423f0742 PB |
252 | { |
253 | s->delta = count; | |
254 | if (s->enabled) { | |
bc72ad67 | 255 | s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
2b5c0322 | 256 | ptimer_reload(s, 0); |
423f0742 PB |
257 | } |
258 | } | |
259 | ||
260 | void ptimer_run(ptimer_state *s, int oneshot) | |
261 | { | |
869e92b5 DO |
262 | bool was_disabled = !s->enabled; |
263 | ||
264 | if (was_disabled && s->period == 0) { | |
2a8b5870 DO |
265 | if (!qtest_enabled()) { |
266 | fprintf(stderr, "Timer with period zero, disabling\n"); | |
267 | } | |
423f0742 PB |
268 | return; |
269 | } | |
270 | s->enabled = oneshot ? 2 : 1; | |
869e92b5 DO |
271 | if (was_disabled) { |
272 | s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | |
2b5c0322 | 273 | ptimer_reload(s, 0); |
869e92b5 | 274 | } |
423f0742 PB |
275 | } |
276 | ||
8d05ea8a | 277 | /* Pause a timer. Note that this may cause it to "lose" time, even if it |
423f0742 PB |
278 | is immediately restarted. */ |
279 | void ptimer_stop(ptimer_state *s) | |
280 | { | |
281 | if (!s->enabled) | |
282 | return; | |
283 | ||
284 | s->delta = ptimer_get_count(s); | |
bc72ad67 | 285 | timer_del(s->timer); |
423f0742 PB |
286 | s->enabled = 0; |
287 | } | |
288 | ||
289 | /* Set counter increment interval in nanoseconds. */ | |
290 | void ptimer_set_period(ptimer_state *s, int64_t period) | |
291 | { | |
7ef6e3cf | 292 | s->delta = ptimer_get_count(s); |
423f0742 PB |
293 | s->period = period; |
294 | s->period_frac = 0; | |
8d05ea8a | 295 | if (s->enabled) { |
bc72ad67 | 296 | s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
2b5c0322 | 297 | ptimer_reload(s, 0); |
8d05ea8a | 298 | } |
423f0742 PB |
299 | } |
300 | ||
301 | /* Set counter frequency in Hz. */ | |
302 | void ptimer_set_freq(ptimer_state *s, uint32_t freq) | |
303 | { | |
7ef6e3cf | 304 | s->delta = ptimer_get_count(s); |
423f0742 PB |
305 | s->period = 1000000000ll / freq; |
306 | s->period_frac = (1000000000ll << 32) / freq; | |
8d05ea8a | 307 | if (s->enabled) { |
bc72ad67 | 308 | s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
2b5c0322 | 309 | ptimer_reload(s, 0); |
8d05ea8a | 310 | } |
423f0742 PB |
311 | } |
312 | ||
313 | /* Set the initial countdown value. If reload is nonzero then also set | |
314 | count = limit. */ | |
8d05ea8a | 315 | void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload) |
423f0742 | 316 | { |
423f0742 PB |
317 | s->limit = limit; |
318 | if (reload) | |
319 | s->delta = limit; | |
62ea5b0b | 320 | if (s->enabled && reload) { |
bc72ad67 | 321 | s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
2b5c0322 | 322 | ptimer_reload(s, 0); |
8d05ea8a BS |
323 | } |
324 | } | |
325 | ||
578c4b2f DO |
326 | uint64_t ptimer_get_limit(ptimer_state *s) |
327 | { | |
328 | return s->limit; | |
329 | } | |
330 | ||
852f771e | 331 | const VMStateDescription vmstate_ptimer = { |
55a6e51f | 332 | .name = "ptimer", |
852f771e JQ |
333 | .version_id = 1, |
334 | .minimum_version_id = 1, | |
35d08458 | 335 | .fields = (VMStateField[]) { |
852f771e JQ |
336 | VMSTATE_UINT8(enabled, ptimer_state), |
337 | VMSTATE_UINT64(limit, ptimer_state), | |
338 | VMSTATE_UINT64(delta, ptimer_state), | |
339 | VMSTATE_UINT32(period_frac, ptimer_state), | |
340 | VMSTATE_INT64(period, ptimer_state), | |
341 | VMSTATE_INT64(last_event, ptimer_state), | |
342 | VMSTATE_INT64(next_event, ptimer_state), | |
e720677e | 343 | VMSTATE_TIMER_PTR(timer, ptimer_state), |
852f771e JQ |
344 | VMSTATE_END_OF_LIST() |
345 | } | |
55a6e51f BS |
346 | }; |
347 | ||
e7ea81c3 | 348 | ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask) |
423f0742 PB |
349 | { |
350 | ptimer_state *s; | |
351 | ||
7267c094 | 352 | s = (ptimer_state *)g_malloc0(sizeof(ptimer_state)); |
423f0742 | 353 | s->bh = bh; |
bc72ad67 | 354 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s); |
e7ea81c3 | 355 | s->policy_mask = policy_mask; |
423f0742 PB |
356 | return s; |
357 | } | |
072bdb07 MAL |
358 | |
359 | void ptimer_free(ptimer_state *s) | |
360 | { | |
361 | qemu_bh_delete(s->bh); | |
362 | timer_free(s->timer); | |
363 | g_free(s); | |
364 | } |