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87ecb68b PB |
1 | #ifndef QEMU_SH_H |
2 | #define QEMU_SH_H | |
3 | /* Definitions for SH board emulation. */ | |
4 | ||
703243a0 AZ |
5 | #include "sh_intc.h" |
6 | ||
5c16736a AZ |
7 | #define A7ADDR(x) ((x) & 0x1fffffff) |
8 | #define P4ADDR(x) ((x) | 0xe0000000) | |
9 | ||
87ecb68b PB |
10 | /* sh7750.c */ |
11 | struct SH7750State; | |
12 | ||
13 | struct SH7750State *sh7750_init(CPUState * cpu); | |
14 | ||
15 | typedef struct { | |
16 | /* The callback will be triggered if any of the designated lines change */ | |
17 | uint16_t portamask_trigger; | |
18 | uint16_t portbmask_trigger; | |
19 | /* Return 0 if no action was taken */ | |
20 | int (*port_change_cb) (uint16_t porta, uint16_t portb, | |
21 | uint16_t * periph_pdtra, | |
22 | uint16_t * periph_portdira, | |
23 | uint16_t * periph_pdtrb, | |
24 | uint16_t * periph_portdirb); | |
25 | } sh7750_io_device; | |
26 | ||
27 | int sh7750_register_io_device(struct SH7750State *s, | |
28 | sh7750_io_device * device); | |
29 | /* sh_timer.c */ | |
30 | #define TMU012_FEAT_TOCR (1 << 0) | |
31 | #define TMU012_FEAT_3CHAN (1 << 1) | |
32 | #define TMU012_FEAT_EXTCLK (1 << 2) | |
c227f099 | 33 | void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq, |
96e2fc41 AJ |
34 | qemu_irq ch0_irq, qemu_irq ch1_irq, |
35 | qemu_irq ch2_irq0, qemu_irq ch2_irq1); | |
703243a0 | 36 | |
87ecb68b PB |
37 | |
38 | /* sh_serial.c */ | |
39 | #define SH_SERIAL_FEAT_SCIF (1 << 0) | |
c227f099 | 40 | void sh_serial_init (target_phys_addr_t base, int feat, |
bf5b7423 | 41 | uint32_t freq, CharDriverState *chr, |
4e7ed2d1 AJ |
42 | qemu_irq eri_source, |
43 | qemu_irq rxi_source, | |
44 | qemu_irq txi_source, | |
45 | qemu_irq tei_source, | |
46 | qemu_irq bri_source); | |
87ecb68b | 47 | |
c6d86a33 AZ |
48 | /* sh7750.c */ |
49 | qemu_irq sh7750_irl(struct SH7750State *s); | |
50 | ||
87ecb68b | 51 | /* tc58128.c */ |
7ccfb2eb | 52 | int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2); |
87ecb68b PB |
53 | |
54 | #endif |