[qemu.git] / hw / pxa2xx_mmci.c

/*
 * Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <[email protected]>
 *
 * This code is licensed under the GPLv2.
 */

#include "hw.h"
#include "pxa.h"
#include "sd.h"
#include "qdev.h"

struct PXA2xxMMCIState {
    qemu_irq irq;
    qemu_irq rx_dma;
    qemu_irq tx_dma;

    SDState *card;

    uint32_t status;
    uint32_t clkrt;
    uint32_t spi;
    uint32_t cmdat;
    uint32_t resp_tout;
    uint32_t read_tout;
    int blklen;
    int numblk;
    uint32_t intmask;
    uint32_t intreq;
    int cmd;
    uint32_t arg;

    int active;
    int bytesleft;
    uint8_t tx_fifo[64];
    int tx_start;
    int tx_len;
    uint8_t rx_fifo[32];
    int rx_start;
    int rx_len;
    uint16_t resp_fifo[9];
    int resp_len;

    int cmdreq;
    int ac_width;
};

#define MMC_STRPCL	0x00	/* MMC Clock Start/Stop register */
#define MMC_STAT	0x04	/* MMC Status register */
#define MMC_CLKRT	0x08	/* MMC Clock Rate register */
#define MMC_SPI		0x0c	/* MMC SPI Mode register */
#define MMC_CMDAT	0x10	/* MMC Command/Data register */
#define MMC_RESTO	0x14	/* MMC Response Time-Out register */
#define MMC_RDTO	0x18	/* MMC Read Time-Out register */
#define MMC_BLKLEN	0x1c	/* MMC Block Length register */
#define MMC_NUMBLK	0x20	/* MMC Number of Blocks register */
#define MMC_PRTBUF	0x24	/* MMC Buffer Partly Full register */
#define MMC_I_MASK	0x28	/* MMC Interrupt Mask register */
#define MMC_I_REG	0x2c	/* MMC Interrupt Request register */
#define MMC_CMD		0x30	/* MMC Command register */
#define MMC_ARGH	0x34	/* MMC Argument High register */
#define MMC_ARGL	0x38	/* MMC Argument Low register */
#define MMC_RES		0x3c	/* MMC Response FIFO */
#define MMC_RXFIFO	0x40	/* MMC Receive FIFO */
#define MMC_TXFIFO	0x44	/* MMC Transmit FIFO */
#define MMC_RDWAIT	0x48	/* MMC RD_WAIT register */
#define MMC_BLKS_REM	0x4c	/* MMC Blocks Remaining register */

/* Bitfield masks */
#define STRPCL_STOP_CLK	(1 << 0)
#define STRPCL_STRT_CLK	(1 << 1)
#define STAT_TOUT_RES	(1 << 1)
#define STAT_CLK_EN	(1 << 8)
#define STAT_DATA_DONE	(1 << 11)
#define STAT_PRG_DONE	(1 << 12)
#define STAT_END_CMDRES	(1 << 13)
#define SPI_SPI_MODE	(1 << 0)
#define CMDAT_RES_TYPE	(3 << 0)
#define CMDAT_DATA_EN	(1 << 2)
#define CMDAT_WR_RD	(1 << 3)
#define CMDAT_DMA_EN	(1 << 7)
#define CMDAT_STOP_TRAN	(1 << 10)
#define INT_DATA_DONE	(1 << 0)
#define INT_PRG_DONE	(1 << 1)
#define INT_END_CMD	(1 << 2)
#define INT_STOP_CMD	(1 << 3)
#define INT_CLK_OFF	(1 << 4)
#define INT_RXFIFO_REQ	(1 << 5)
#define INT_TXFIFO_REQ	(1 << 6)
#define INT_TINT	(1 << 7)
#define INT_DAT_ERR	(1 << 8)
#define INT_RES_ERR	(1 << 9)
#define INT_RD_STALLED	(1 << 10)
#define INT_SDIO_INT	(1 << 11)
#define INT_SDIO_SACK	(1 << 12)
#define PRTBUF_PRT_BUF	(1 << 0)

/* Route internal interrupt lines to the global IC and DMA */
static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
{
    uint32_t mask = s->intmask;
    if (s->cmdat & CMDAT_DMA_EN) {
        mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;

        qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
        qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
    }

    qemu_set_irq(s->irq, !!(s->intreq & ~mask));
}

static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
{
    if (!s->active)
        return;

    if (s->cmdat & CMDAT_WR_RD) {
        while (s->bytesleft && s->tx_len) {
            sd_write_data(s->card, s->tx_fifo[s->tx_start ++]);
            s->tx_start &= 0x1f;
            s->tx_len --;
            s->bytesleft --;
        }
        if (s->bytesleft)
            s->intreq |= INT_TXFIFO_REQ;
    } else
        while (s->bytesleft && s->rx_len < 32) {
            s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
                sd_read_data(s->card);
            s->bytesleft --;
            s->intreq |= INT_RXFIFO_REQ;
        }

    if (!s->bytesleft) {
        s->active = 0;
        s->intreq |= INT_DATA_DONE;
        s->status |= STAT_DATA_DONE;

        if (s->cmdat & CMDAT_WR_RD) {
            s->intreq |= INT_PRG_DONE;
            s->status |= STAT_PRG_DONE;
        }
    }

    pxa2xx_mmci_int_update(s);
}

static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
{
    int rsplen, i;
    SDRequest request;
    uint8_t response[16];

    s->active = 1;
    s->rx_len = 0;
    s->tx_len = 0;
    s->cmdreq = 0;

    request.cmd = s->cmd;
    request.arg = s->arg;
    request.crc = 0;	/* FIXME */

    rsplen = sd_do_command(s->card, &request, response);
    s->intreq |= INT_END_CMD;

    memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
    switch (s->cmdat & CMDAT_RES_TYPE) {
#define PXAMMCI_RESP(wd, value0, value1)	\
        s->resp_fifo[(wd) + 0] |= (value0);	\
        s->resp_fifo[(wd) + 1] |= (value1) << 8;
    case 0:	/* No response */
        goto complete;

    case 1:	/* R1, R4, R5 or R6 */
        if (rsplen < 4)
            goto timeout;
        goto complete;

    case 2:	/* R2 */
        if (rsplen < 16)
            goto timeout;
        goto complete;

    case 3:	/* R3 */
        if (rsplen < 4)
            goto timeout;
        goto complete;

    complete:
        for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
            PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
        }
        s->status |= STAT_END_CMDRES;

        if (!(s->cmdat & CMDAT_DATA_EN))
            s->active = 0;
        else
            s->bytesleft = s->numblk * s->blklen;

        s->resp_len = 0;
        break;

    timeout:
        s->active = 0;
        s->status |= STAT_TOUT_RES;
        break;
    }

    pxa2xx_mmci_fifo_update(s);
}

static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    uint32_t ret;

    switch (offset) {
    case MMC_STRPCL:
        return 0;
    case MMC_STAT:
        return s->status;
    case MMC_CLKRT:
        return s->clkrt;
    case MMC_SPI:
        return s->spi;
    case MMC_CMDAT:
        return s->cmdat;
    case MMC_RESTO:
        return s->resp_tout;
    case MMC_RDTO:
        return s->read_tout;
    case MMC_BLKLEN:
        return s->blklen;
    case MMC_NUMBLK:
        return s->numblk;
    case MMC_PRTBUF:
        return 0;
    case MMC_I_MASK:
        return s->intmask;
    case MMC_I_REG:
        return s->intreq;
    case MMC_CMD:
        return s->cmd | 0x40;
    case MMC_ARGH:
        return s->arg >> 16;
    case MMC_ARGL:
        return s->arg & 0xffff;
    case MMC_RES:
        if (s->resp_len < 9)
            return s->resp_fifo[s->resp_len ++];
        return 0;
    case MMC_RXFIFO:
        ret = 0;
        while (s->ac_width -- && s->rx_len) {
            ret |= s->rx_fifo[s->rx_start ++] << (s->ac_width << 3);
            s->rx_start &= 0x1f;
            s->rx_len --;
        }
        s->intreq &= ~INT_RXFIFO_REQ;
        pxa2xx_mmci_fifo_update(s);
        return ret;
    case MMC_RDWAIT:
        return 0;
    case MMC_BLKS_REM:
        return s->numblk;
    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }

    return 0;
}

static void pxa2xx_mmci_write(void *opaque,
                target_phys_addr_t offset, uint32_t value)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;

    switch (offset) {
    case MMC_STRPCL:
        if (value & STRPCL_STRT_CLK) {
            s->status |= STAT_CLK_EN;
            s->intreq &= ~INT_CLK_OFF;

            if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
                s->status &= STAT_CLK_EN;
                pxa2xx_mmci_wakequeues(s);
            }
        }

        if (value & STRPCL_STOP_CLK) {
            s->status &= ~STAT_CLK_EN;
            s->intreq |= INT_CLK_OFF;
            s->active = 0;
        }

        pxa2xx_mmci_int_update(s);
        break;

    case MMC_CLKRT:
        s->clkrt = value & 7;
        break;

    case MMC_SPI:
        s->spi = value & 0xf;
        if (value & SPI_SPI_MODE)
            printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
        break;

    case MMC_CMDAT:
        s->cmdat = value & 0x3dff;
        s->active = 0;
        s->cmdreq = 1;
        if (!(value & CMDAT_STOP_TRAN)) {
            s->status &= STAT_CLK_EN;

            if (s->status & STAT_CLK_EN)
                pxa2xx_mmci_wakequeues(s);
        }

        pxa2xx_mmci_int_update(s);
        break;

    case MMC_RESTO:
        s->resp_tout = value & 0x7f;
        break;

    case MMC_RDTO:
        s->read_tout = value & 0xffff;
        break;

    case MMC_BLKLEN:
        s->blklen = value & 0xfff;
        break;

    case MMC_NUMBLK:
        s->numblk = value & 0xffff;
        break;

    case MMC_PRTBUF:
        if (value & PRTBUF_PRT_BUF) {
            s->tx_start ^= 32;
            s->tx_len = 0;
        }
        pxa2xx_mmci_fifo_update(s);
        break;

    case MMC_I_MASK:
        s->intmask = value & 0x1fff;
        pxa2xx_mmci_int_update(s);
        break;

    case MMC_CMD:
        s->cmd = value & 0x3f;
        break;

    case MMC_ARGH:
        s->arg &= 0x0000ffff;
        s->arg |= value << 16;
        break;

    case MMC_ARGL:
        s->arg &= 0xffff0000;
        s->arg |= value & 0x0000ffff;
        break;

    case MMC_TXFIFO:
        while (s->ac_width -- && s->tx_len < 0x20)
            s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
                    (value >> (s->ac_width << 3)) & 0xff;
        s->intreq &= ~INT_TXFIFO_REQ;
        pxa2xx_mmci_fifo_update(s);
        break;

    case MMC_RDWAIT:
    case MMC_BLKS_REM:
        break;

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }
}

static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    s->ac_width = 1;
    return pxa2xx_mmci_read(opaque, offset);
}

static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    s->ac_width = 2;
    return pxa2xx_mmci_read(opaque, offset);
}

static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    s->ac_width = 4;
    return pxa2xx_mmci_read(opaque, offset);
}

static CPUReadMemoryFunc * const pxa2xx_mmci_readfn[] = {
    pxa2xx_mmci_readb,
    pxa2xx_mmci_readh,
    pxa2xx_mmci_readw
};

static void pxa2xx_mmci_writeb(void *opaque,
                target_phys_addr_t offset, uint32_t value)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    s->ac_width = 1;
    pxa2xx_mmci_write(opaque, offset, value);
}

static void pxa2xx_mmci_writeh(void *opaque,
                target_phys_addr_t offset, uint32_t value)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    s->ac_width = 2;
    pxa2xx_mmci_write(opaque, offset, value);
}

static void pxa2xx_mmci_writew(void *opaque,
                target_phys_addr_t offset, uint32_t value)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    s->ac_width = 4;
    pxa2xx_mmci_write(opaque, offset, value);
}

static CPUWriteMemoryFunc * const pxa2xx_mmci_writefn[] = {
    pxa2xx_mmci_writeb,
    pxa2xx_mmci_writeh,
    pxa2xx_mmci_writew
};

static void pxa2xx_mmci_save(QEMUFile *f, void *opaque)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    int i;

    qemu_put_be32s(f, &s->status);
    qemu_put_be32s(f, &s->clkrt);
    qemu_put_be32s(f, &s->spi);
    qemu_put_be32s(f, &s->cmdat);
    qemu_put_be32s(f, &s->resp_tout);
    qemu_put_be32s(f, &s->read_tout);
    qemu_put_be32(f, s->blklen);
    qemu_put_be32(f, s->numblk);
    qemu_put_be32s(f, &s->intmask);
    qemu_put_be32s(f, &s->intreq);
    qemu_put_be32(f, s->cmd);
    qemu_put_be32s(f, &s->arg);
    qemu_put_be32(f, s->cmdreq);
    qemu_put_be32(f, s->active);
    qemu_put_be32(f, s->bytesleft);

    qemu_put_byte(f, s->tx_len);
    for (i = 0; i < s->tx_len; i ++)
        qemu_put_byte(f, s->tx_fifo[(s->tx_start + i) & 63]);

    qemu_put_byte(f, s->rx_len);
    for (i = 0; i < s->rx_len; i ++)
        qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 31]);

    qemu_put_byte(f, s->resp_len);
    for (i = s->resp_len; i < 9; i ++)
        qemu_put_be16s(f, &s->resp_fifo[i]);
}

static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    int i;

    qemu_get_be32s(f, &s->status);
    qemu_get_be32s(f, &s->clkrt);
    qemu_get_be32s(f, &s->spi);
    qemu_get_be32s(f, &s->cmdat);
    qemu_get_be32s(f, &s->resp_tout);
    qemu_get_be32s(f, &s->read_tout);
    s->blklen = qemu_get_be32(f);
    s->numblk = qemu_get_be32(f);
    qemu_get_be32s(f, &s->intmask);
    qemu_get_be32s(f, &s->intreq);
    s->cmd = qemu_get_be32(f);
    qemu_get_be32s(f, &s->arg);
    s->cmdreq = qemu_get_be32(f);
    s->active = qemu_get_be32(f);
    s->bytesleft = qemu_get_be32(f);

    s->tx_len = qemu_get_byte(f);
    s->tx_start = 0;
    if (s->tx_len >= sizeof(s->tx_fifo) || s->tx_len < 0)
        return -EINVAL;
    for (i = 0; i < s->tx_len; i ++)
        s->tx_fifo[i] = qemu_get_byte(f);

    s->rx_len = qemu_get_byte(f);
    s->rx_start = 0;
    if (s->rx_len >= sizeof(s->rx_fifo) || s->rx_len < 0)
        return -EINVAL;
    for (i = 0; i < s->rx_len; i ++)
        s->rx_fifo[i] = qemu_get_byte(f);

    s->resp_len = qemu_get_byte(f);
    if (s->resp_len > 9 || s->resp_len < 0)
        return -EINVAL;
    for (i = s->resp_len; i < 9; i ++)
         qemu_get_be16s(f, &s->resp_fifo[i]);

    return 0;
}

PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
                BlockDriverState *bd, qemu_irq irq,
                qemu_irq rx_dma, qemu_irq tx_dma)
{
    int iomemtype;
    PXA2xxMMCIState *s;

    s = (PXA2xxMMCIState *) g_malloc0(sizeof(PXA2xxMMCIState));
    s->irq = irq;
    s->rx_dma = rx_dma;
    s->tx_dma = tx_dma;

    iomemtype = cpu_register_io_memory(pxa2xx_mmci_readfn,
                    pxa2xx_mmci_writefn, s, DEVICE_NATIVE_ENDIAN);
    cpu_register_physical_memory(base, 0x00100000, iomemtype);

    /* Instantiate the actual storage */
    s->card = sd_init(bd, 0);

    register_savevm(NULL, "pxa2xx_mmci", 0, 0,
                    pxa2xx_mmci_save, pxa2xx_mmci_load, s);

    return s;
}

void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
                qemu_irq coverswitch)
{
    sd_set_cb(s->card, readonly, coverswitch);
}
Commit	Line	Data
a171fe39 AZ	1	/*
	2	* Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <[email protected]>
	6	*
	7	* This code is licensed under the GPLv2.
	8	*/
	9
87ecb68b PB	10	#include "hw.h"
87ecb68b PB	11	#include "pxa.h"
a171fe39	12	#include "sd.h"
2115c019	13	#include "qdev.h"
a171fe39	14
bc24a225	15	struct PXA2xxMMCIState {
a171fe39	16	qemu_irq irq;
2115c019 AZ	17	qemu_irq rx_dma;
2115c019 AZ	18	qemu_irq tx_dma;
a171fe39 AZ	19
	20	SDState *card;
	21
	22	uint32_t status;
	23	uint32_t clkrt;
	24	uint32_t spi;
	25	uint32_t cmdat;
	26	uint32_t resp_tout;
	27	uint32_t read_tout;
	28	int blklen;
	29	int numblk;
	30	uint32_t intmask;
	31	uint32_t intreq;
	32	int cmd;
	33	uint32_t arg;
	34
	35	int active;
	36	int bytesleft;
	37	uint8_t tx_fifo[64];
	38	int tx_start;
	39	int tx_len;
	40	uint8_t rx_fifo[32];
	41	int rx_start;
	42	int rx_len;
	43	uint16_t resp_fifo[9];
	44	int resp_len;
	45
	46	int cmdreq;
	47	int ac_width;
	48	};
	49
	50	#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */
	51	#define MMC_STAT 0x04 /* MMC Status register */
	52	#define MMC_CLKRT 0x08 /* MMC Clock Rate register */
	53	#define MMC_SPI 0x0c /* MMC SPI Mode register */
	54	#define MMC_CMDAT 0x10 /* MMC Command/Data register */
	55	#define MMC_RESTO 0x14 /* MMC Response Time-Out register */
	56	#define MMC_RDTO 0x18 /* MMC Read Time-Out register */
	57	#define MMC_BLKLEN 0x1c /* MMC Block Length register */
	58	#define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */
	59	#define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */
	60	#define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */
	61	#define MMC_I_REG 0x2c /* MMC Interrupt Request register */
	62	#define MMC_CMD 0x30 /* MMC Command register */
	63	#define MMC_ARGH 0x34 /* MMC Argument High register */
	64	#define MMC_ARGL 0x38 /* MMC Argument Low register */
	65	#define MMC_RES 0x3c /* MMC Response FIFO */
	66	#define MMC_RXFIFO 0x40 /* MMC Receive FIFO */
	67	#define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */
	68	#define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */
	69	#define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */
	70
	71	/* Bitfield masks */
	72	#define STRPCL_STOP_CLK (1 << 0)
	73	#define STRPCL_STRT_CLK (1 << 1)
	74	#define STAT_TOUT_RES (1 << 1)
	75	#define STAT_CLK_EN (1 << 8)
	76	#define STAT_DATA_DONE (1 << 11)
	77	#define STAT_PRG_DONE (1 << 12)
	78	#define STAT_END_CMDRES (1 << 13)
	79	#define SPI_SPI_MODE (1 << 0)
	80	#define CMDAT_RES_TYPE (3 << 0)
	81	#define CMDAT_DATA_EN (1 << 2)
	82	#define CMDAT_WR_RD (1 << 3)
83	#define CMDAT_DMA_EN (1 << 7)
84	#define CMDAT_STOP_TRAN (1 << 10)
85	#define INT_DATA_DONE (1 << 0)
86	#define INT_PRG_DONE (1 << 1)
87	#define INT_END_CMD (1 << 2)
88	#define INT_STOP_CMD (1 << 3)
89	#define INT_CLK_OFF (1 << 4)
90	#define INT_RXFIFO_REQ (1 << 5)
91	#define INT_TXFIFO_REQ (1 << 6)
92	#define INT_TINT (1 << 7)
93	#define INT_DAT_ERR (1 << 8)
94	#define INT_RES_ERR (1 << 9)
95	#define INT_RD_STALLED (1 << 10)
96	#define INT_SDIO_INT (1 << 11)
97	#define INT_SDIO_SACK (1 << 12)
98	#define PRTBUF_PRT_BUF (1 << 0)
99
100	/* Route internal interrupt lines to the global IC and DMA */
bc24a225	101	static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
a171fe39 AZ	102	{
	103	uint32_t mask = s->intmask;
	104	if (s->cmdat & CMDAT_DMA_EN) {
	105	mask \|= INT_RXFIFO_REQ \| INT_TXFIFO_REQ;
	106
2115c019 AZ	107	qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
2115c019 AZ	108	qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
a171fe39 AZ	109	}
	110
	111	qemu_set_irq(s->irq, !!(s->intreq & ~mask));
	112	}
	113
bc24a225	114	static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
a171fe39 AZ	115	{
	116	if (!s->active)
	117	return;
	118
	119	if (s->cmdat & CMDAT_WR_RD) {
	120	while (s->bytesleft && s->tx_len) {
	121	sd_write_data(s->card, s->tx_fifo[s->tx_start ++]);
	122	s->tx_start &= 0x1f;
	123	s->tx_len --;
	124	s->bytesleft --;
	125	}
	126	if (s->bytesleft)
	127	s->intreq \|= INT_TXFIFO_REQ;
	128	} else
	129	while (s->bytesleft && s->rx_len < 32) {
	130	s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
	131	sd_read_data(s->card);
	132	s->bytesleft --;
	133	s->intreq \|= INT_RXFIFO_REQ;
	134	}
	135
	136	if (!s->bytesleft) {
	137	s->active = 0;
	138	s->intreq \|= INT_DATA_DONE;
	139	s->status \|= STAT_DATA_DONE;
	140
	141	if (s->cmdat & CMDAT_WR_RD) {
	142	s->intreq \|= INT_PRG_DONE;
	143	s->status \|= STAT_PRG_DONE;
	144	}
	145	}
	146
	147	pxa2xx_mmci_int_update(s);
	148	}
	149
bc24a225	150	static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
a171fe39 AZ	151	{
a171fe39 AZ	152	int rsplen, i;
bc24a225	153	SDRequest request;
a171fe39 AZ	154	uint8_t response[16];
	155
	156	s->active = 1;
	157	s->rx_len = 0;
	158	s->tx_len = 0;
	159	s->cmdreq = 0;
	160
	161	request.cmd = s->cmd;
	162	request.arg = s->arg;
	163	request.crc = 0; /* FIXME */
	164
	165	rsplen = sd_do_command(s->card, &request, response);
	166	s->intreq \|= INT_END_CMD;
	167
	168	memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
	169	switch (s->cmdat & CMDAT_RES_TYPE) {
	170	#define PXAMMCI_RESP(wd, value0, value1) \
	171	s->resp_fifo[(wd) + 0] \|= (value0); \
	172	s->resp_fifo[(wd) + 1] \|= (value1) << 8;
	173	case 0: /* No response */
	174	goto complete;
	175
	176	case 1: /* R1, R4, R5 or R6 */
	177	if (rsplen < 4)
	178	goto timeout;
	179	goto complete;
	180
	181	case 2: /* R2 */
	182	if (rsplen < 16)
	183	goto timeout;
	184	goto complete;
	185
	186	case 3: /* R3 */
	187	if (rsplen < 4)
	188	goto timeout;
	189	goto complete;
	190
	191	complete:
	192	for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
	193	PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
	194	}
	195	s->status \|= STAT_END_CMDRES;
	196
	197	if (!(s->cmdat & CMDAT_DATA_EN))
	198	s->active = 0;
	199	else
	200	s->bytesleft = s->numblk * s->blklen;
	201
	202	s->resp_len = 0;
	203	break;
	204
	205	timeout:
	206	s->active = 0;
	207	s->status \|= STAT_TOUT_RES;
	208	break;
	209	}
	210
	211	pxa2xx_mmci_fifo_update(s);
	212	}
	213
c227f099	214	static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
a171fe39	215	{
bc24a225	216	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
a171fe39	217	uint32_t ret;
a171fe39 AZ	218
	219	switch (offset) {
	220	case MMC_STRPCL:
	221	return 0;
	222	case MMC_STAT:
	223	return s->status;
	224	case MMC_CLKRT:
	225	return s->clkrt;
	226	case MMC_SPI:
	227	return s->spi;
	228	case MMC_CMDAT:
	229	return s->cmdat;
	230	case MMC_RESTO:
	231	return s->resp_tout;
	232	case MMC_RDTO:
	233	return s->read_tout;
	234	case MMC_BLKLEN:
	235	return s->blklen;
	236	case MMC_NUMBLK:
	237	return s->numblk;
	238	case MMC_PRTBUF:
	239	return 0;
	240	case MMC_I_MASK:
	241	return s->intmask;
	242	case MMC_I_REG:
	243	return s->intreq;
	244	case MMC_CMD:
	245	return s->cmd \| 0x40;
	246	case MMC_ARGH:
	247	return s->arg >> 16;
	248	case MMC_ARGL:
	249	return s->arg & 0xffff;
	250	case MMC_RES:
	251	if (s->resp_len < 9)
	252	return s->resp_fifo[s->resp_len ++];
	253	return 0;
	254	case MMC_RXFIFO:
	255	ret = 0;
	256	while (s->ac_width -- && s->rx_len) {
	257	ret \|= s->rx_fifo[s->rx_start ++] << (s->ac_width << 3);
	258	s->rx_start &= 0x1f;
	259	s->rx_len --;
	260	}
	261	s->intreq &= ~INT_RXFIFO_REQ;
	262	pxa2xx_mmci_fifo_update(s);
	263	return ret;
	264	case MMC_RDWAIT:
	265	return 0;
	266	case MMC_BLKS_REM:
	267	return s->numblk;
	268	default:
2ac71179	269	hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
a171fe39 AZ	270	}
	271
	272	return 0;
	273	}
	274
	275	static void pxa2xx_mmci_write(void *opaque,
c227f099	276	target_phys_addr_t offset, uint32_t value)
a171fe39	277	{
bc24a225	278	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
a171fe39 AZ	279
	280	switch (offset) {
	281	case MMC_STRPCL:
	282	if (value & STRPCL_STRT_CLK) {
	283	s->status \|= STAT_CLK_EN;
	284	s->intreq &= ~INT_CLK_OFF;
	285
	286	if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
	287	s->status &= STAT_CLK_EN;
	288	pxa2xx_mmci_wakequeues(s);
	289	}
	290	}
	291
	292	if (value & STRPCL_STOP_CLK) {
	293	s->status &= ~STAT_CLK_EN;
	294	s->intreq \|= INT_CLK_OFF;
	295	s->active = 0;
	296	}
	297
	298	pxa2xx_mmci_int_update(s);
	299	break;
	300
	301	case MMC_CLKRT:
	302	s->clkrt = value & 7;
	303	break;
	304
	305	case MMC_SPI:
	306	s->spi = value & 0xf;
	307	if (value & SPI_SPI_MODE)
	308	printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
	309	break;
	310
	311	case MMC_CMDAT:
	312	s->cmdat = value & 0x3dff;
	313	s->active = 0;
	314	s->cmdreq = 1;
	315	if (!(value & CMDAT_STOP_TRAN)) {
	316	s->status &= STAT_CLK_EN;
	317
	318	if (s->status & STAT_CLK_EN)
	319	pxa2xx_mmci_wakequeues(s);
	320	}
	321
	322	pxa2xx_mmci_int_update(s);
	323	break;
	324
	325	case MMC_RESTO:
	326	s->resp_tout = value & 0x7f;
	327	break;
	328
	329	case MMC_RDTO:
	330	s->read_tout = value & 0xffff;
	331	break;
	332
	333	case MMC_BLKLEN:
	334	s->blklen = value & 0xfff;
	335	break;
	336
	337	case MMC_NUMBLK:
	338	s->numblk = value & 0xffff;
	339	break;
	340
	341	case MMC_PRTBUF:
	342	if (value & PRTBUF_PRT_BUF) {
343	s->tx_start ^= 32;
344	s->tx_len = 0;
345	}
346	pxa2xx_mmci_fifo_update(s);
347	break;
348
349	case MMC_I_MASK:
350	s->intmask = value & 0x1fff;
351	pxa2xx_mmci_int_update(s);
352	break;
353
354	case MMC_CMD:
355	s->cmd = value & 0x3f;
356	break;
357
358	case MMC_ARGH:
359	s->arg &= 0x0000ffff;
360	s->arg \|= value << 16;
361	break;
362
363	case MMC_ARGL:
364	s->arg &= 0xffff0000;
365	s->arg \|= value & 0x0000ffff;
366	break;
367
368	case MMC_TXFIFO:
369	while (s->ac_width -- && s->tx_len < 0x20)
370	s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
371	(value >> (s->ac_width << 3)) & 0xff;
372	s->intreq &= ~INT_TXFIFO_REQ;
373	pxa2xx_mmci_fifo_update(s);
374	break;
375
376	case MMC_RDWAIT:
377	case MMC_BLKS_REM:
378	break;
379
380	default:
2ac71179	381	hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
a171fe39 AZ	382	}
	383	}
	384
c227f099	385	static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset)
a171fe39	386	{
bc24a225	387	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
a171fe39 AZ	388	s->ac_width = 1;
	389	return pxa2xx_mmci_read(opaque, offset);
	390	}
	391
c227f099	392	static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset)
a171fe39	393	{
bc24a225	394	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
a171fe39 AZ	395	s->ac_width = 2;
	396	return pxa2xx_mmci_read(opaque, offset);
	397	}
	398
c227f099	399	static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset)
a171fe39	400	{
bc24a225	401	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
a171fe39 AZ	402	s->ac_width = 4;
	403	return pxa2xx_mmci_read(opaque, offset);
	404	}
	405
d60efc6b	406	static CPUReadMemoryFunc * const pxa2xx_mmci_readfn[] = {
a171fe39 AZ	407	pxa2xx_mmci_readb,
	408	pxa2xx_mmci_readh,
	409	pxa2xx_mmci_readw
	410	};
	411
	412	static void pxa2xx_mmci_writeb(void *opaque,
c227f099	413	target_phys_addr_t offset, uint32_t value)
a171fe39	414	{
bc24a225	415	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
a171fe39 AZ	416	s->ac_width = 1;
	417	pxa2xx_mmci_write(opaque, offset, value);
	418	}
	419
	420	static void pxa2xx_mmci_writeh(void *opaque,
c227f099	421	target_phys_addr_t offset, uint32_t value)
a171fe39	422	{
bc24a225	423	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
a171fe39 AZ	424	s->ac_width = 2;
	425	pxa2xx_mmci_write(opaque, offset, value);
	426	}
	427
	428	static void pxa2xx_mmci_writew(void *opaque,
c227f099	429	target_phys_addr_t offset, uint32_t value)
a171fe39	430	{
bc24a225	431	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
a171fe39 AZ	432	s->ac_width = 4;
	433	pxa2xx_mmci_write(opaque, offset, value);
	434	}
	435
d60efc6b	436	static CPUWriteMemoryFunc * const pxa2xx_mmci_writefn[] = {
a171fe39 AZ	437	pxa2xx_mmci_writeb,
	438	pxa2xx_mmci_writeh,
	439	pxa2xx_mmci_writew
	440	};
	441
aa941b94 AZ	442	static void pxa2xx_mmci_save(QEMUFile f, void opaque)
aa941b94 AZ	443	{
bc24a225	444	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
aa941b94 AZ	445	int i;
	446
	447	qemu_put_be32s(f, &s->status);
	448	qemu_put_be32s(f, &s->clkrt);
	449	qemu_put_be32s(f, &s->spi);
	450	qemu_put_be32s(f, &s->cmdat);
	451	qemu_put_be32s(f, &s->resp_tout);
	452	qemu_put_be32s(f, &s->read_tout);
	453	qemu_put_be32(f, s->blklen);
	454	qemu_put_be32(f, s->numblk);
	455	qemu_put_be32s(f, &s->intmask);
	456	qemu_put_be32s(f, &s->intreq);
	457	qemu_put_be32(f, s->cmd);
	458	qemu_put_be32s(f, &s->arg);
	459	qemu_put_be32(f, s->cmdreq);
	460	qemu_put_be32(f, s->active);
	461	qemu_put_be32(f, s->bytesleft);
	462
	463	qemu_put_byte(f, s->tx_len);
	464	for (i = 0; i < s->tx_len; i ++)
	465	qemu_put_byte(f, s->tx_fifo[(s->tx_start + i) & 63]);
	466
	467	qemu_put_byte(f, s->rx_len);
	468	for (i = 0; i < s->rx_len; i ++)
	469	qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 31]);
	470
	471	qemu_put_byte(f, s->resp_len);
	472	for (i = s->resp_len; i < 9; i ++)
	473	qemu_put_be16s(f, &s->resp_fifo[i]);
	474	}
	475
	476	static int pxa2xx_mmci_load(QEMUFile f, void opaque, int version_id)
	477	{
bc24a225	478	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
aa941b94 AZ	479	int i;
	480
	481	qemu_get_be32s(f, &s->status);
	482	qemu_get_be32s(f, &s->clkrt);
	483	qemu_get_be32s(f, &s->spi);
	484	qemu_get_be32s(f, &s->cmdat);
	485	qemu_get_be32s(f, &s->resp_tout);
	486	qemu_get_be32s(f, &s->read_tout);
	487	s->blklen = qemu_get_be32(f);
	488	s->numblk = qemu_get_be32(f);
	489	qemu_get_be32s(f, &s->intmask);
	490	qemu_get_be32s(f, &s->intreq);
	491	s->cmd = qemu_get_be32(f);
	492	qemu_get_be32s(f, &s->arg);
	493	s->cmdreq = qemu_get_be32(f);
	494	s->active = qemu_get_be32(f);
	495	s->bytesleft = qemu_get_be32(f);
	496
	497	s->tx_len = qemu_get_byte(f);
	498	s->tx_start = 0;
	499	if (s->tx_len >= sizeof(s->tx_fifo) \|\| s->tx_len < 0)
	500	return -EINVAL;
	501	for (i = 0; i < s->tx_len; i ++)
	502	s->tx_fifo[i] = qemu_get_byte(f);
	503
	504	s->rx_len = qemu_get_byte(f);
	505	s->rx_start = 0;
	506	if (s->rx_len >= sizeof(s->rx_fifo) \|\| s->rx_len < 0)
	507	return -EINVAL;
	508	for (i = 0; i < s->rx_len; i ++)
	509	s->rx_fifo[i] = qemu_get_byte(f);
	510
	511	s->resp_len = qemu_get_byte(f);
	512	if (s->resp_len > 9 \|\| s->resp_len < 0)
	513	return -EINVAL;
	514	for (i = s->resp_len; i < 9; i ++)
	515	qemu_get_be16s(f, &s->resp_fifo[i]);
	516
	517	return 0;
	518	}
	519
c227f099	520	PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
2115c019 AZ	521	BlockDriverState *bd, qemu_irq irq,
2115c019 AZ	522	qemu_irq rx_dma, qemu_irq tx_dma)
a171fe39 AZ	523	{
a171fe39 AZ	524	int iomemtype;
bc24a225	525	PXA2xxMMCIState *s;
a171fe39	526
7267c094	527	s = (PXA2xxMMCIState *) g_malloc0(sizeof(PXA2xxMMCIState));
a171fe39	528	s->irq = irq;
2115c019 AZ	529	s->rx_dma = rx_dma;
2115c019 AZ	530	s->tx_dma = tx_dma;
a171fe39	531
1eed09cb	532	iomemtype = cpu_register_io_memory(pxa2xx_mmci_readfn,
2507c12a	533	pxa2xx_mmci_writefn, s, DEVICE_NATIVE_ENDIAN);
187337f8	534	cpu_register_physical_memory(base, 0x00100000, iomemtype);
a171fe39 AZ	535
a171fe39 AZ	536	/* Instantiate the actual storage */
c81b7401	537	s->card = sd_init(bd, 0);
a171fe39	538
0be71e32	539	register_savevm(NULL, "pxa2xx_mmci", 0, 0,
aa941b94 AZ	540	pxa2xx_mmci_save, pxa2xx_mmci_load, s);
aa941b94 AZ	541
a171fe39 AZ	542	return s;
	543	}
	544
bc24a225	545	void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
02ce600c	546	qemu_irq coverswitch)
a171fe39	547	{
e1dad5a6	548	sd_set_cb(s->card, readonly, coverswitch);
a171fe39	549	}